KR102484988B1 - Composition for etching and manufacturing method of semiconductor device using the same - Google Patents

Composition for etching and manufacturing method of semiconductor device using the same Download PDF

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KR102484988B1
KR102484988B1 KR1020170183806A KR20170183806A KR102484988B1 KR 102484988 B1 KR102484988 B1 KR 102484988B1 KR 1020170183806 A KR1020170183806 A KR 1020170183806A KR 20170183806 A KR20170183806 A KR 20170183806A KR 102484988 B1 KR102484988 B1 KR 102484988B1
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etching
group
formula
composition
hydrogen
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KR20190081343A (en
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유호성
이준은
장평화
한승현
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오씨아이 주식회사
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    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09KMATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00Etching, surface-brightening or pickling compositions
    • C09K13/04Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/06Etching, surface-brightening or pickling compositions containing an inorganic acid with organic material
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09KMATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00Etching, surface-brightening or pickling compositions
    • C09K13/04Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/08Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means

Abstract

하기 화학식 1로 표시되는 아미노-실록산 화합물 및 용제를 포함하는 식각용 조성물에 관한 것으로 본 발명의 식각용 조성물은 산화막의 식각율을 최소화하면서 질화막을 선택적으로 제거할 수 있으며, 소자 특성에 악영향을 미치는 파티클 발생을 억제하는 효과가 탁월하다.
[화학식 1]

Figure 112017131044892-pat00015
It relates to an etching composition comprising an amino-siloxane compound represented by Formula 1 and a solvent. The etching composition of the present invention can selectively remove a nitride film while minimizing the etching rate of an oxide film, and adversely affects device characteristics. The effect of suppressing particle generation is excellent.
[Formula 1]
Figure 112017131044892-pat00015

Description

식각용 조성물 및 이를 이용한 반도체 소자의 제조방법 {COMPOSITION FOR ETCHING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME}Composition for etching and method for manufacturing a semiconductor device using the same

본 발명은 식각용 조성물, 특히 산화막의 식각율을 최소화하면서 질화막을 선택적으로 제거할 수 있는 고선택비의 식각용 조성물 및 이 식각용 조성물을 이용한 식각 공정을 포함하는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to an etching composition, particularly a high-selectivity etching composition capable of selectively removing a nitride film while minimizing an etching rate of an oxide film, and a method for manufacturing a semiconductor device including an etching process using the etching composition. .

반도체 제조 공정에 있어서, 실리콘 산화막(SiO2) 등의 산화막 및 실리콘 질화막(SiNx) 등의 질화막은 대표적인 절연막으로 각각 단독으로, 또는 1층 이상의 막들이 교대로 적층되어 사용된다. 상기 실리콘 질화막은 실리콘 산화막, 폴리 실리콘막, 실리콘 웨이퍼 표면 등과 접촉하는 구조로 CVD (Chemical vapor deposition) 공정을 통해서 증착되며, 이는 건식 식각 및 습식 식각을 통해서 제거되는데, 인산(phosphoric acid)을 이용한 습식 식각이 널리 이용되고 있다. In a semiconductor manufacturing process, an oxide film such as a silicon oxide film (SiO 2 ) and a nitride film such as a silicon nitride film (SiN x ) are representative insulating films that are used alone or alternately stacked with one or more layers. The silicon nitride film is deposited through a CVD (Chemical Vapor Deposition) process in a structure in contact with a silicon oxide film, a polysilicon film, a silicon wafer surface, etc., and is removed through dry etching and wet etching. Wet using phosphoric acid Etching is widely used.

상기 실리콘 질화막을 제거하기 위한 습식 식각 공정에서는 일반적으로 인산과 탈이온수(deionized water)의 혼합물이 사용되고 있다. 상기 탈이온수는 식각율 감소 및 산화막에 대한 식각 선택성의 변화를 방지하기 위하여 첨가되는 것이나, 공급되는 탈이온수의 양의 미세한 변화에도 질화막 식각 제거 공정에 불량이 발생하는 문제가 있다. 또한, 인산은 강산으로서 부식성을 가지고 있어 취급에 어려움이 있다.In the wet etching process for removing the silicon nitride film, a mixture of phosphoric acid and deionized water is generally used. The deionized water is added to prevent a decrease in the etching rate and a change in etching selectivity for the oxide film, but there is a problem in that defects occur in the nitride film etching removal process even with a slight change in the amount of deionized water supplied. In addition, since phosphoric acid is a strong acid and has corrosive properties, it is difficult to handle.

대한민국 등록특허 제 1380487호(실리콘 질화막의 식각 용액)에서는 실리콘 질화막을 선택적으로 식각하는 식각용 조성물에 관한 것으로, 디램(DRAM) 및 낸드플래시 메모리의 STI (Shallow Trench Isolation) 및 게이트 전극 형성 공정 등 반도체 제조 공정에서 사용되는 실리콘 질화막을 선택적으로 식각하는데 습식 식각용 조성물에 대하여 개시하고 있다.Republic of Korea Patent Registration No. 1380487 (Etching Solution for Silicon Nitride Film) relates to an etching composition for selectively etching silicon nitride films, such as shallow trench isolation (STI) and gate electrode formation processes for DRAM and NAND flash memory semiconductors. A wet etching composition for selectively etching a silicon nitride film used in a manufacturing process is disclosed.

대한민국 공개특허공보 제2015-0045331호(식각액 조성물 및 이를 이용한 금속 패턴 제조방법)에서는 과산화이황산 암모늄, 인산 또는 아인산 화합물, 염소산염계화합물, 질산 또는 술폰산 화합물, 아졸계 화합물, 불소화합물 및 물을 포함하는 식각용 조성물에 대하여 개시하고 있다.Republic of Korea Patent Publication No. 2015-0045331 (etchant composition and metal pattern manufacturing method using the same) discloses ammonium peroxydisulfate, phosphoric acid or phosphorous acid compound, chlorate-based compound, nitric acid or sulfonic acid compound, azole-based compound, fluorine compound and water containing A composition for etching is disclosed.

한편, 반도체에서 실리콘 질화막과 실리콘 산화막을 제거하는 방법에 있어서 산화막의 식각률은 낮추고 질화막의 식각률을 높이기 위하여 다각도의 측면에서 연구가 시도되고 있으며, 그 중 하나의 방법으로 식각용 조성물 내에 실리콘 함유 화합물을 식각용 조성물의 첨가제로 사용하고 있다. 그러나, 이러한 실리콘 함유 화합물은 기판에 영향을 줄 수 있는 파티클을 유발함으로써, 오히려 반도체 공정의 안정성 및 신뢰성을 저하시키는 문제점이 있다.On the other hand, in the method of removing silicon nitride and silicon oxide films from semiconductors, research is being attempted from various angles in order to lower the etching rate of the oxide film and increase the etching rate of the nitride film, and one of them is to prepare a silicon-containing compound in an etching composition. It is used as an additive for etching compositions. However, these silicon-containing compounds have a problem in that stability and reliability of semiconductor processes are rather deteriorated by causing particles that may affect the substrate.

본 발명은 반도체 공정에서 실리콘 산화막에 비해 실리콘 질화막에 대한 식각 선택비가 높은 식각용 조성물을 제공하고자 한다.An object of the present invention is to provide an etching composition having a higher etching selectivity for a silicon nitride film than for a silicon oxide film in a semiconductor process.

또 한편으론, 본 발명은 실리콘 웨이퍼 식각시 실리콘 산화막의 식각 속도를 감소시키는 동시에 산화막에서의 파티클의 응집을 방지가능한 식각용 조성물을 제공하고자 한다.On the other hand, the present invention is to provide an etching composition capable of reducing the etching rate of a silicon oxide film during etching of a silicon wafer and at the same time preventing aggregation of particles in the oxide film.

본 발명은 상기 식각용 조성물을 이용하여 높은 안정성 및 신뢰성을 보장하는 식각 방법을 제공하고자 한다.An object of the present invention is to provide an etching method that ensures high stability and reliability using the etching composition.

본 발명은 하기 화학식 1로 표시되는 아미노-실록산 화합물 및 용제를 포함하는 식각용 조성물을 제공한다. The present invention provides an etching composition comprising an amino-siloxane compound represented by Formula 1 below and a solvent.

[화학식 1] [Formula 1]

Figure 112017131044892-pat00001
Figure 112017131044892-pat00001

상기 식에서, R1은 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기 및 C1-C10 알킬아미노기로 이루어진 군으로부터 선택되며, R2는 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기, C1-C10 알킬아미노기 및

Figure 112017131044892-pat00002
로 이루어진 군으로부터 선택되며, 상기 R1 및 R2의 적어도 하나는 C1-C10 알킬아미노기이며, R3은 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기 및 C1-C10 미노알킬기로 이루어진 군으로부터 선택된다. In the above formula, R 1 is each independently selected from the group consisting of hydrogen, halogen, hydroxyl group, C1-C10 alkyl group, C1-C10 alkoxy group and C1-C10 alkylamino group, R 2 are each independently hydrogen, halogen, A hydroxyl group, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C1-C10 alkylamino group, and
Figure 112017131044892-pat00002
is selected from the group consisting of, wherein at least one of R 1 and R 2 is a C1-C10 alkylamino group, and R 3 are each independently hydrogen, halogen, hydroxy group, C1-C10 alkyl group, C1-C10 alkoxy group and C1 -C10 It is selected from the group consisting of minoalkyl groups.

본 발명의 일 구현예에서, 상기 화학식 1이 하기 화학식 2로 표시될 수 있다. In one embodiment of the present invention, Formula 1 may be represented by Formula 2 below.

[화학식 2] [Formula 2]

Figure 112017131044892-pat00003
Figure 112017131044892-pat00003

상기 식에서, In the above formula,

R1 및 R2는 제1항에서 정의한 바와 동일하고, R4는 각각 독립적으로 수소 또는 C1-C10 알킬기이며, 상기 R4의 적어도 하나는 수소이며, n 및 m은 각각 1 내지 10의 정수이다. R 1 and R 2 are the same as defined in claim 1, R 4 are each independently hydrogen or a C1-C10 alkyl group, at least one of R 4 is hydrogen, and n and m are each an integer of 1 to 10. .

본 발명의 일 구현예에서, 상기 화학식 1이 하기 화학식 3으로 표시될 수 있다. In one embodiment of the present invention, Formula 1 may be represented by Formula 3 below.

[화학식 3] [Formula 3]

Figure 112017131044892-pat00004
Figure 112017131044892-pat00004

상기 식에서, n 및 m은 각각 1 내지 5의 정수이다. In the above formula, n and m are each an integer of 1 to 5.

본 발명의 일 구현예에서, 상기 식각용 조성물은 상기 식각용 조성물 전체에 대하여 상기 화학식 1로 표시되는 아미노-실록산 화합물을 200 내지 50000 ppm로 포함할 수 있다. In one embodiment of the present invention, the etching composition may include the amino-siloxane compound represented by Chemical Formula 1 in an amount of 200 to 50000 ppm based on the total amount of the etching composition.

본 발명의 일 구현예에서, 상기 식각용 조성물은 식각용 조성물 전체에 대하여 불소계 화합물을 0.01 내지 1 중량%로 더 포함할 수 있다.In one embodiment of the present invention, the composition for etching may further include 0.01 to 1% by weight of a fluorine-based compound with respect to the total composition for etching.

본 발명은 인산에 상기 화학식 1로 표시되는 화합물을 첨가한 식각용 조성물을 제공함으로써, 실리콘 산화막의 식각 속도를 낮추고 질화막을 선택적으로 제거할 수 있는 식각용 조성물을 제공한다. The present invention provides an etching composition capable of reducing the etching rate of a silicon oxide film and selectively removing a nitride film by providing a composition for etching in which the compound represented by Formula 1 is added to phosphoric acid.

본 발명은 실리콘 함유 화합물 포함시 생성될 수 있는 파티클의 발생을 억제하므로써, 파티클에 의해 소자의 특성이 저하되는 것을 방지할 수 있다. The present invention suppresses the generation of particles that may be generated when the silicon-containing compound is included, thereby preventing deterioration in device characteristics due to the particles.

이하, 본 발명의 구현예를 상세히 설명하기로 한다. 다만, 이는 예시로서 제시되는 것으로, 이에 의해 본 발명이 제한되지는 않으며 본 발명은 후술할 청구범위의 범주에 의해 정의될 뿐이다.Hereinafter, embodiments of the present invention will be described in detail. However, this is presented as an example, and the present invention is not limited thereby, and the present invention is only defined by the scope of the claims to be described later.

본 발명에서 "할로겐"은 불소, 염소, 브롬 또는 요오드이다."Halogen" in the present invention is fluorine, chlorine, bromine or iodine.

본 발명에서 "알킬기"는 특별한 언급이 없으면, C1-C30의 직쇄 또는 측쇄의 포화 탄화수소에서 유래되는 1가의 치환기를 의미한다. 이의 예로는 메틸, 에틸, 프로필, 이소부틸, 이소프로필, tert-부틸, sec-부틸, 펜틸, 헥실 등을 들 수 있으나, 이에 한정되지는 않는다.In the present invention, "alkyl group" means a monovalent substituent derived from a C1-C30 linear or branched saturated hydrocarbon, unless otherwise specified. Examples thereof include, but are not limited to, methyl, ethyl, propyl, isobutyl, isopropyl, tert-butyl, sec-butyl, pentyl, hexyl, and the like.

본 발명에서 "알콕시"는 R'O-로 표시되는 1가의 치환기로, 상기 R'는 C1-C30의 알킬기를 의미하며, 직쇄(linear), 측쇄(branched) 또는 사이클릭(cyclic) 구조를 포함할 수 있다. 알킬옥시의 예로는 메톡시, 에톡시, n-프로폭시, 1-프로폭시, t-부톡시, n-부톡시, 펜톡시 등을 들 수 있으나, 이에 한정되지는 않는다.In the present invention, "alkoxy" is a monovalent substituent represented by R'O-, wherein R' means a C1-C30 alkyl group, and includes a linear, branched or cyclic structure. can do. Examples of alkyloxy include, but are not limited to, methoxy, ethoxy, n-propoxy, 1-propoxy, t-butoxy, n-butoxy, pentoxy, and the like.

본 발명에서 "알킬아미노기"는 알킬기로 치환된 아미노기를 의미한다.In the present invention, "alkylamino group" means an amino group substituted with an alkyl group.

본 발명은 하기 화학식 1로 표시되는 아미노-실록산 화합물 및 용제를 포함하는 식각용 조성물을 제공한다. The present invention provides an etching composition comprising an amino-siloxane compound represented by Formula 1 below and a solvent.

[화학식 1] [Formula 1]

Figure 112017131044892-pat00005
Figure 112017131044892-pat00005

상기 식에서, R1은 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기 및 C1-C10 알킬아미노기로 이루어진 군으로부터 선택되며, R2는 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기, C1-C10 알킬아미노기 및

Figure 112017131044892-pat00006
로 이루어진 군으로부터 선택되며, 상기 R1 및 R2의 적어도 하나는 C1-C10 알킬아미노기이다. In the above formula, R 1 is each independently selected from the group consisting of hydrogen, halogen, hydroxyl group, C1-C10 alkyl group, C1-C10 alkoxy group and C1-C10 alkylamino group, R 2 are each independently hydrogen, halogen, A hydroxyl group, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C1-C10 alkylamino group, and
Figure 112017131044892-pat00006
It is selected from the group consisting of, wherein at least one of R 1 and R 2 is a C1-C10 alkylamino group.

상기 R3은 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기 및 C1-C10 미노알킬기로 이루어진 군으로부터 선택된다. Each R 3 is independently selected from the group consisting of hydrogen, halogen, hydroxyl group, C1-C10 alkyl group, C1-C10 alkoxy group and C1-C10 minoalkyl group.

상기 화학식 1로 표시되는 아미노-실록산 화합물은 실리콘 산화막에 대한 식각율을 최소화 하고, 실리콘 질화막을 실리콘 산화막의 식각 속도 이상으로 빠르게 제거하여 선택적으로 실리콘 질화막을 제거한다. 더욱이, 상기 화학식 1로 표시되는 아미노-실록산 화합물은 식각 공정에 이후의 공정에 영향을 줄 수 있는 파티클이 석출되거나, 웨이퍼 상에 잔존하는 것을 방지함으로써, 고온에서 사용되는 인산 식각 공정의 안정성 및 신뢰성을 부여할 수 있다. The amino-siloxane compound represented by Chemical Formula 1 minimizes the etching rate of the silicon oxide layer and selectively removes the silicon nitride layer by removing the silicon nitride layer faster than the etching rate of the silicon oxide layer. Furthermore, the amino-siloxane compound represented by Formula 1 prevents particles that may affect the subsequent process from being deposited or remaining on the wafer during the etching process, thereby increasing the stability and reliability of the phosphoric acid etching process used at high temperatures. can be granted.

본 발명의 바람직한 일 구현예에 있어서, 상기 화학식 1이 하기 화학식 2로 표시될 수 있다. In a preferred embodiment of the present invention, Formula 1 may be represented by Formula 2 below.

[화학식 2] [Formula 2]

Figure 112017131044892-pat00007
Figure 112017131044892-pat00007

상기 식에서, R1 및 R2는 전술한 바와 동일하고, R4는 각각 독립적으로 수소 또는 C1-C10 알킬기이며, 상기 R4의 적어도 하나는 수소이며, n 및 m은 각각 1 내지 10의 정수이다. In the above formula, R 1 and R 2 are the same as described above, R 4 are each independently hydrogen or a C1-C10 alkyl group, at least one of R 4 is hydrogen, and n and m are each an integer of 1 to 10. .

본 발명의 바람직한 일 구현예에 있어서, 상기 화학식 1이 하기 화학식 3으로 표시될 수 있다. In a preferred embodiment of the present invention, Formula 1 may be represented by Formula 3 below.

[화학식 3] [Formula 3]

Figure 112017131044892-pat00008
Figure 112017131044892-pat00008

상기 식에서, n 및 m은 각각 1 내지 5의 정수이다. In the above formula, n and m are each an integer of 1 to 5.

상기 화학식 3은 보다 바람직하게, 1,3-비스(3-아미노프로필)테트라메틸디실록산일 수 있다. Formula 3 may be more preferably 1,3-bis(3-aminopropyl)tetramethyldisiloxane.

본 발명의 바람직한 일 구현예에 있어서, 하기 화학식 1로 표시되는 아미노-실록산 화합물은 식각용 조성물의 전체 중량에 대해서 200 내지 50000 ppm으로 포함될 수 있으며, 더욱 바람직하게는 1000 내지 20000 ppm으로 포함된다. In a preferred embodiment of the present invention, the amino-siloxane compound represented by Formula 1 may be included in an amount of 200 to 50000 ppm, more preferably 1000 to 20000 ppm, based on the total weight of the composition for etching.

본 발명에 따른 하기 화학식 1로 표시되는 아미노-실록산 화합물의 함량이 너무 낮은 경우에는, 실리콘 산화막 및 실리콘 질화막의 식각이 동시에 일어나며 공정에 적합한 수준의 실리콘 산화막 식각속도 수준의 결과를 얻을 수 없으며, 반대로 아미노-실록산 화합물의 함량이 너무 높은 경우에는, 실리콘 질화막의 식각속도와 실리콘 산화막의 식각 속도가 함께 줄어들어 선택비의 차가 줄어드나, 본 발명에 따른 하기 화학식 1로 표시되는 아미노-실록산 화합물의 함량이 상기의 범위에 포함하는 경우 실리콘 산화막에 대한 실리콘 질화막의 식각 속도가 높게 유지될 수 있다. If the content of the amino-siloxane compound represented by Formula 1 according to the present invention is too low, the silicon oxide film and the silicon nitride film are etched simultaneously, and the silicon oxide etch rate suitable for the process cannot be obtained. Conversely, When the content of the amino-siloxane compound is too high, the etching rate of the silicon nitride film and the etching rate of the silicon oxide film are reduced together to reduce the difference in selectivity, but the content of the amino-siloxane compound represented by Formula 1 according to the present invention When included in the above range, the etching rate of the silicon nitride film to the silicon oxide film can be maintained high.

본 발명에 따른 식각용 조성물을 사용하여 산화막을 식각하는 경우, 종래 실리콘 함유 화합물, 예를 들면 규산 및 규산염을 첨가하는 방법에서 발생되는 파티클이 형성되지 않으며, 높은 선택비로 실리콘 질화막을 식각할 수 있다. When an oxide film is etched using the etching composition according to the present invention, particles generated in the conventional method of adding silicon-containing compounds, for example, silicic acid and silicate, are not formed, and the silicon nitride film can be etched with a high selectivity. .

본 발명의 다른 구현예에 있어서, 상기 식각용 조성물은 식각용 조성물의 전체 중량에 대해서 불소계 화합물을 추가적으로 포함할 수 있다. 또한, 상기 불소계 화합물은 0.01 내지 1 중량%, 바람직하게는 0.1 내지 0.5 중량%로 포함될 수 있으며, 상기 불소계 화합물은 예를 들어 불화수소, 불화암모늄, 불화수소암모늄 등일 수 있으나 이에 제한되지 않는다. In another embodiment of the present invention, the etching composition may additionally include a fluorine-based compound based on the total weight of the etching composition. In addition, the fluorine-based compound may be included in an amount of 0.01 to 1% by weight, preferably 0.1 to 0.5% by weight, and the fluorine-based compound may be, for example, hydrogen fluoride, ammonium fluoride, ammonium hydrogen fluoride, etc., but is not limited thereto.

본 발명의 또 다른 구현예는 전술한 식각용 조성물을 이용하여 수행되는 식각 공정을 포함하는 반도체 소자의 제조 방법을 제공할 수 있다. Another embodiment of the present invention may provide a method of manufacturing a semiconductor device including an etching process performed using the above-described composition for etching.

일 구현예로서, 본 발명의 식각용 조성물은 식각하고자 하는 실리콘 질화막에 도포 하기 전에 100 내지 180℃로 예열한 뒤 사용될 수 있으며, 실리콘 질화막층과 실리콘 산화막층이 교차하여 적층하거나, 혼재하여 사용될 경우 실리콘 질화막의 완전한 제거를 위해 추가 시간 공정을 진행하여도 실리콘 산화막에는 식각의 효과가 거의 없어 우수한 실리콘 질화막 제거 효과를 얻을 수 있다. As an embodiment, the etching composition of the present invention may be used after being preheated to 100 to 180 ° C. before being applied to a silicon nitride film to be etched, and when a silicon nitride film layer and a silicon oxide film layer are alternately laminated or used in combination. Even if an additional time process is performed for complete removal of the silicon nitride layer, an excellent silicon nitride layer removal effect can be obtained because there is little etching effect on the silicon oxide layer.

본 발명의 식각용 조성물을 이용하여 식각을 실시하는 경우, 산화막의 식각 속도를 낮춤으로써, 상기 산화막에 대한 질화막의 선택비가 5 내지 30으로 높다. When etching is performed using the composition for etching of the present invention, by lowering the etching rate of the oxide film, the selectivity of the nitride film to the oxide film is high, such as 5 to 30.

이하, 실시예에 의해 본 발명을 보다 상세히 설명하나, 이는 발명의 구성 및 효과를 이해시키기 위한 것일 뿐, 본 발명의 범위를 제한하고자 하는 것은 아니다.Hereinafter, the present invention will be described in more detail by examples, but this is only for understanding the configuration and effects of the present invention, and is not intended to limit the scope of the present invention.

실시예Example : : 식각용for etching 조성물의 제조 preparation of the composition

실시예Example 1: One:

농도 85%인 인산 수용액에 1,3-비스(3-아미노프로필)테트라메틸디실록산을 2,000ppm농도로 80 oC에서 3시간 동안 교반하여 식각용 조성물을 제조하였다.An etching composition was prepared by stirring 1,3-bis(3-aminopropyl)tetramethyldisiloxane at a concentration of 2,000 ppm in an 85% phosphoric acid aqueous solution at 80 ° C. for 3 hours.

비교예comparative example 1: One:

농도 85%인 인산 수용액을 식각용 조성물로 준비하였다. A phosphoric acid aqueous solution having a concentration of 85% was prepared as an etching composition.

비교예comparative example 2: 2:

농도 85%인 인산 수용액에 트리메틸실라놀(trimethylsilanol)을 2,000ppm농도로 첨가하여, 80oC에서 30분 동안 교반하여 식각용 조성물을 제조하였다.A composition for etching was prepared by adding trimethylsilanol at a concentration of 2,000 ppm to an aqueous phosphoric acid solution having a concentration of 85% and stirring at 80 ° C for 30 minutes.

Figure 112017131044892-pat00009
Figure 112017131044892-pat00009

트리메틸실라놀(trimethylsilanol)trimethylsilanol

비교예comparative example 3: 3:

농도 85%인 인산 수용액에 하기 화학식으로 표시되는 화합물을 2,000ppm농도로 첨가하여, 80oC에서 30분 동안 교반하여 식각용 조성물을 제조하였다.An etching composition was prepared by adding a compound represented by the formula below to a phosphoric acid aqueous solution having a concentration of 85% at a concentration of 2,000 ppm and stirring at 80 ° C for 30 minutes.

Figure 112017131044892-pat00010
Figure 112017131044892-pat00010

3-(1,1,3,3,3-펜타메틸디실록사닐)프로판-1-아민3-(1,1,3,3,3-pentamethyldisiloxanyl)propan-1-amine

특성 평가 Characteristic evaluation

선택비 측정 selectivity measurement

실시예 및 비교예 1 내지 3에서 준비한 식각용 조성물을 각각 160 내지 180 ℃로 가열한 뒤, ALD SiOx에 대해 식각을 실시하였고, 박막 두께 측정 장비인 엘립소미터(NANO VIEW, SEMG-1000)를 이용하여 산화막에 대한 식각률 (etching rate, E/R)을 측정하였다. 하기 표 1에 기재된 식각률은 상기 방법으로 5회 측정하여, 평균된 식각률이다. After heating the compositions for etching prepared in Examples and Comparative Examples 1 to 3 at 160 to 180 ° C, respectively, etching was performed on ALD SiO x , and thin film thickness measuring equipment, an ellipsometer (NANO VIEW, SEMG-1000) The etching rate (E/R) for the oxide film was measured using . The etching rate shown in Table 1 below is an average etching rate obtained by measuring 5 times by the above method.

막질membranous 식각전 두께thickness before etching 식각후 두께thickness after etching E/RE/R 실시예Example 1 One ALD siox ALD sio x 503.44503.44 497.66497.66 5.785.78 비교예comparative example 1 One ALD siox ALD sio x 501.94501.94 481.40481.40 20.5420.54 비교예comparative example 2 2 ALD siox ALD sio x 502.44502.44 486.67486.67 15.7715.77 비교예comparative example 3 3 ALD siox ALD sio x 500.38500.38 490.27490.27 10.1110.11

실시예 1은 비교예 1 내지 3에 비해, 산화막의 식각 속도가 상당히 낮음을 확인하였다. In Example 1, it was confirmed that the etching rate of the oxide film was significantly lower than that of Comparative Examples 1 to 3.

비교예 2의 트리메틸실라놀(trimethylsilanol)은 끓는점이 낮아 식각용 조성물을 사용하기 전에 예열하는 공정에서부터 인산 수용액 내의 트리메틸실라놀(trimethylsilanol)의 농도가 급격하게 감소하게 됨에 따라 산화막의 식각 속도의 제어가 어려워지게 되었다. Trimethylsilanol of Comparative Example 2 has a low boiling point, and as the concentration of trimethylsilanol in the aqueous phosphoric acid solution rapidly decreases from the preheating process before using the etching composition, the control of the etching rate of the oxide film is possible. it became difficult

비교예 3의 상기 실리콘 함유 화합물은 식각용 조성물을 가열하게 됨에 따라, 트리메틸실라놀과 (3-아미노프로필)(디메틸)실라놀로 가수분해됨으로써, 비교예 1과 동일한 이유로 산화막의 식각 속도의 제어가 어려워지게 되었다. As the etching composition is heated, the silicon-containing compound of Comparative Example 3 is hydrolyzed into trimethylsilanol and (3-aminopropyl) (dimethyl)silanol, so that the etching rate of the oxide film can be controlled for the same reason as in Comparative Example 1. it became difficult

[ [ 파티클particle 형성 관측] formation observation]

전술한 방법에 따라 실시예 및 비교예에 따라 제조된 식각용 조성물을 이용하여 식각을 진행하하고, 식각 후 생성된 파티클의 사이즈를 PSA (particle size analyzer)로 이용하여 측정, 200 ㎛ 초과 및 10 ㎛ 미만의 파티클의 생성 여부 및 그의 입자크기를 측정하여, 하기 표 2에 결과값을 나타내었다.Etching was performed using the etching composition prepared according to Examples and Comparative Examples according to the method described above, and the size of particles generated after etching was measured using a particle size analyzer (PSA), exceeding 200 μm and 10 By measuring whether or not particles smaller than ㎛ were generated and their particle size, the results are shown in Table 2 below.

200 초과 파티클More than 200 Particles 200 미만 파티클less than 200 particles 실시예Example 1 One -- <0.01 μm<0.01 μm 비교예comparative example 1 One 210, 310 μm210, 310 μm 15, 87, 185 μm15, 87, 185 μm 비교예comparative example 2 2 -- <0.5 μm<0.5 μm 비교예comparative example 3 3 -- <0.1 μm<0.1 μm

상기 표 2에 나타난 바와 같이 본 발명에 따른 하기 화학식 1로 표시되는 아미노-실록산 화합물을 포함한 식각용 조성물의 경우, 실시예 1은 200 초과 파티클이 전혀 발견되지 않았으며 직경이 0.01 μm 미만의 파티클만이 소량 발견됨으로써, 비교예 1 내지 3에 비하여 파티클 발생이 방지되고 궁극적으로 소자에 부정적인 영향을 미칠 수 있는 요소를 제거하였다. 됨을 확인할 수 있다. As shown in Table 2, in the case of the etching composition including the amino-siloxane compound represented by Formula 1 according to the present invention, in Example 1, no particles exceeding 200 were found, and only particles with a diameter of less than 0.01 μm were found. By finding a small amount of this, the generation of particles is prevented compared to Comparative Examples 1 to 3, and elements that may ultimately have a negative effect on the device are removed. can confirm that it is.

Claims (8)

하기 화학식 2로 표시되는 아미노-실록산 화합물 및 용제를 포함하는 식각용 조성물:
[화학식 2]
Figure 112022074334223-pat00016

상기 식에서,
R1은 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기 및 C1-C10 알킬아미노기로 이루어진 군으로부터 선택되며,
R2는 각각 독립적으로 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기, C1-C10 알킬아미노기 및
Figure 112022074334223-pat00012
로 이루어진 군으로부터 선택되며,
상기 R1 및 R2의 적어도 하나는 C1-C10 알킬아미노기이며,
R3은 수소, 할로겐, 하이드록시기, C1-C10 알킬기, C1-C10 알콕시기 및 C1-C10 미노알킬기로 이루어진 군으로부터 선택되며,
R4는 각각 독립적으로 수소 또는 C1-C10 알킬기이며, 상기 R4의 적어도 하나는 수소이며,
n 및 m은 각각 1 내지 10의 정수이다.
An etching composition comprising an amino-siloxane compound represented by Formula 2 and a solvent:
[Formula 2]
Figure 112022074334223-pat00016

In the above formula,
R 1 is each independently selected from the group consisting of hydrogen, halogen, hydroxyl group, C1-C10 alkyl group, C1-C10 alkoxy group and C1-C10 alkylamino group;
R 2 are each independently hydrogen, halogen, a hydroxyl group, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C1-C10 alkylamino group, and
Figure 112022074334223-pat00012
It is selected from the group consisting of
At least one of R 1 and R 2 is a C1-C10 alkylamino group,
R 3 is selected from the group consisting of hydrogen, halogen, hydroxyl group, C1-C10 alkyl group, C1-C10 alkoxy group and C1-C10 minoalkyl group;
R 4 are each independently hydrogen or a C1-C10 alkyl group, and at least one of R4 is hydrogen;
n and m are each an integer from 1 to 10;
삭제delete 제1항에 있어서,
상기 화학식 2가 하기 화학식 3으로 표시되는 식각용 조성물:
[화학식 3]
Figure 112022074334223-pat00014

상기 식에서,
n 및 m은 각각 1 내지 5의 정수이다.
According to claim 1,
An etching composition in which Formula 2 is represented by Formula 3 below:
[Formula 3]
Figure 112022074334223-pat00014

In the above formula,
n and m are each an integer from 1 to 5;
제1항에 있어서,
상기 식각용 조성물 전체에 대하여 상기 화학식 1로 표시되는 아미노-실록산 화합물을 200 내지 50000 ppm로 포함하는 식각용 조성물:
According to claim 1,
An etching composition comprising 200 to 50000 ppm of the amino-siloxane compound represented by Formula 1 with respect to the entire composition for etching:
제1항에 있어서,
상기 식각용 조성물 전체에 대하여 불소계 화합물을 0.01 내지 1 중량%로 더 포함하는 식각용 조성물.
According to claim 1,
An etching composition further comprising 0.01 to 1% by weight of a fluorine-based compound based on the total weight of the etching composition.
제 5 항에 있어서,
상기 불소계 화합물은 불화수소, 불화암모늄, 불화수소암모늄 및 이들의 혼합물로 이루어진 군에서 선택되는 어느 하나인 것인 식각용 조성물.
According to claim 5,
The fluorine-based compound is any one selected from the group consisting of hydrogen fluoride, ammonium fluoride, ammonium hydrogen fluoride, and mixtures thereof, the composition for etching.
제 1 항 또는 제 6 항 중 어느 한 항에 따른 식각용 조성물을 이용하여 수행되는 식각 공정을 포함하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device comprising an etching process performed using the composition for etching according to any one of claims 1 to 6. 제 7 항에 있어서,
상기 식각 공정은 산화막에 대하여 질화막을 선택적으로 식각하는 것이며,
상기 식각 공정에 의한 상기 산화막에 대한 질화막의 선택비가 5 내지 30인 반도체 소자의 제조 방법.
According to claim 7,
The etching process is to selectively etch the nitride film with respect to the oxide film,
A method of manufacturing a semiconductor device in which the selectivity of the nitride film to the oxide film by the etching process is 5 to 30.
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