KR102473648B1 - Sensor Package and Method of Manufacturing the Same - Google Patents

Abstract

A sensor package capable of preventing drift or warpage of a semiconductor chip and a manufacturing method thereof are disclosed. This can improve heat dissipation characteristics because the heat generated in the semiconductor chip can be efficiently transferred to the outside by placing the semiconductor chip on a metal frame having an I/O pad and a heat sink. Movement or warping of the semiconductor chip, which may occur due to thermal deformation, may be prevented.

Description

Sensor package and manufacturing method thereof {Sensor Package and Method of Manufacturing the Same}

The present invention relates to a sensor package and a method for manufacturing the same, and more particularly, to a sensor package capable of increasing heat dissipation efficiency and preventing drift or warpage of a semiconductor chip and a method for manufacturing the same. .

In recent semiconductor devices, the chip size is reduced due to the miniaturization of process technology and the diversification of functions, and the number of input/output terminals increases. As the electrode pad pitch is gradually refined, and as the convergence of various functions accelerates, multiple devices can be integrated into one package. A system-level packaging technology that integrates within the system is emerging. In addition, system level packaging technology is changing into a 3D stacking technology capable of maintaining a short signal distance in order to minimize noise between operations and improve signal speed.

On the other hand, in semiconductor packages having a conventional fan-out structure, separated semiconductor chips are rearranged on a separate large-diameter panel, molded with EMC (Epoxy Molding Compound) to integrate them, and then a wiring circuit is created on the pad surface of the semiconductor chip. It is common to perform a build-up process that

However, in the process of molding with EMC, a phenomenon (drift) in which the semiconductor chip moves unintentionally occurs due to the flow of EMC or thermal deformation. Such movement of the chip causes misalignment between the chip pad and the circuit formed through the build-up process, and there is a problem in that it is difficult to respond to a fine pad pitch. In addition, a structure that encapsulates a semiconductor chip with EMC has a problem in that it is difficult to dissipate heat by EMC having high thermal resistance.

Korea Patent Registration 10-1664411

A first technical problem to be achieved by the present invention is to provide a sensor package capable of increasing heat dissipation efficiency of a package and preventing movement or warping of a semiconductor chip.

In addition, a second technical problem to be achieved by the present invention is to provide a method for manufacturing a sensor package to achieve the first technical problem.

The sensor package of the present invention for achieving the above-described first technical problem is a metal frame having a first surface exposed to the outside and a second surface opposite to the first surface, disposed on the second surface of the metal frame. A semiconductor chip, a molding layer that buries the semiconductor chip, and a wiring part electrically connected to a pad of the semiconductor chip and formed on the molding layer, wherein the molding layer is electrically connected to the wiring part and a through-via and a normal A via is included, and the metal frame includes an I/O pad connected to the through via, a heat sink on which the semiconductor chip is seated, and a molding member surrounding side surfaces of the I/O pad and the heat sink.

The I/O pads may be spaced apart from each other on both sides of the heat sink.

The molding member may be formed to cover both sides of the I/O pad.

The through via may be formed to be connected to the I/O pad, and the normal via may be formed to be connected to a pad of the semiconductor chip.

The I/O pad may include a protrusion protruding from the second surface of the metal frame.

The protrusion may be electrically connected to the through via.

The I/O pad may be formed to extend along the second surface of the metal frame to a side surface, and the molding member may be formed to fill a lower portion of the extended I/O pad.

The height of the molding member filled in the lower portion of the extended I/O pad may be formed to be 30% or more of the height of the metal frame.

The molding member may be formed to be exposed on the first surface adjacent to the side surface of the metal frame.

The semiconductor chip may include a first semiconductor chip electrically connected to the through-via and a second semiconductor chip disposed adjacent to the first semiconductor chip and electrically connected to the first semiconductor chip through the wiring part. .

In order to achieve the above-described second technical problem, a method for manufacturing a sensor package of the present invention includes preparing a metal frame having an I/O pad and a heat sink and having a molding member formed thereon, so that the first surface of the metal frame is in contact with the first surface of the metal frame. Disposing a metal frame on a carrier substrate, disposing a semiconductor chip on a second surface opposite to the first surface of the metal frame, burying the semiconductor chip with a molding layer, forming through vias and through-vias on the molding layer The method may include forming a normal via and forming a wiring part on the molding layer to electrically connect the semiconductor chip and the I/O pad.

In the forming of the through vias and the normal vias, the through vias may be formed to be connected to the I/O pads, and the normal vias may be formed to be connected to pads of the semiconductor chip.

According to the present invention described above, by disposing the semiconductor chip on the metal frame having the I/O pad and the heat sink, heat generated in the semiconductor chip can be efficiently transferred to the outside, and thus heat dissipation characteristics can be improved.

In addition, since the semiconductor chips are arranged so as to be seated on the metal frame, drift or warpage of the semiconductor chips, which may occur due to the flow of the molding layer or thermal deformation during the manufacturing process, can be prevented. have.

In addition, even if an external impact is applied to the package, the metal frame primarily absorbs and disperses the impact to reduce the impact applied to the semiconductor chip, thereby increasing the rigidity of the package itself.

In addition, by using polyimide (PI) as the molding layer, consumption of the insulating layer can be reduced and process time can be shortened because a separate insulating layer is not required under the wiring layer when forming the wiring part. Accordingly, the manufacturing cost can be reduced because the step of forming the semiconductor package is simplified.

In addition, since the wiring layer can be directly formed on the molding layer, the thickness of the package can be reduced due to the reduction of the insulating layer.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a cross-sectional view showing a first embodiment according to the sensor package of the present invention.
2 is a cross-sectional view showing a second embodiment according to the sensor package of the present invention.
3 is a cross-sectional view showing a third embodiment according to the sensor package of the present invention.
4 is a cross-sectional view showing a fourth embodiment according to the sensor package of the present invention.
5 is a cross-sectional view showing a fifth embodiment according to the sensor package of the present invention.
6 is a cross-sectional view showing a sixth embodiment according to the sensor package of the present invention.
7 to 11 are cross-sectional views for explaining a method of manufacturing the sensor package shown in FIG. 1 according to a first preferred embodiment of the present invention.
12 to 14 are cross-sectional views for explaining a method of manufacturing the sensor package shown in FIG. 3 according to a third preferred embodiment of the present invention.

Since the present invention may have various changes and various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals have been used for like elements throughout the description of each figure.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, they should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail.

Example

1 is a cross-sectional view showing a first embodiment according to the sensor package of the present invention.

Referring to FIG. 1 , a sensor package according to a first embodiment of the present invention includes a metal frame 100 , a semiconductor chip 200 , a molding layer 300 and a wiring unit 400 .

The metal frame 100 may be formed in a flat plate shape. In addition, the upper and lower surfaces of the metal frame 100 may have a rectangular shape, but are not limited thereto.

The metal frame 100 may include a plurality of frame structures. For example, the metal frame 100 may include an I/O pad 110 and a heat sink 120 . The I/O pads 110 may be spaced apart from each other on both sides of the heat sink 120 . The I/O pad 110 can be used to input/output signals or supply power, and the heat sink 120 can easily dissipate heat generated from the semiconductor chip 200 seated on the heat sink 120 to the outside. can function as much as possible. Accordingly, the metal frame 100 may function as an embedded ground plane (EGP) and dissipate heat.

The material of the metal frame 100 may be formed of electroless nickel immersion gold (ENIG) to prevent corrosion of the contact portion and improve contact performance. Also, side surfaces of the I/O pad 110 and the heat sink 120 may be filled with the molding member 130 . Thus, the I/O pad 110 and the heat sink 120 may be insulated from each other.

The metal frame 100 has a first surface 101 with an open bottom and a second surface 102 that faces the first surface 101 . That is, lower surfaces of the I/O pad 110 and the heat sink 120 may be exposed to the outside, and the second surface 102 may be filled with a molding layer 300 to be described later. Here, the I/O pad 110, which is the second surface 102 of the metal frame 100, and the upper surface of the heat sink 120 may be formed to be on the same plane.

Here, the metal frame 100 according to the first embodiment is formed so that the molding member 130 surrounds the side surface 103 of the metal frame 100, and the I/O pad 110 is formed of the metal frame 100. It may be formed to extend to the side surface 103 along the second surface 102 . That is, the molding member 130 formed on the side surface 103 of the metal frame 100 may be formed to fill the lower portion of the extended I/O pad 110 .

At this time, the height (h) of the molding member 130 formed on the side surface 103 of the metal frame 100 is the height (H) of the metal frame 100, that is, from the first surface 101 of the metal frame 100 It may be formed to be 30% or more of the height up to the second surface 102. More specifically, it may have a height ranging from 30% to 100%. If the height (h) of the molding member 130 is less than 30%, a peeling shape in which the molding member 130 is detached from the metal frame 100 may occur. In addition, as an example, when the height (h) of the molding member 130 becomes 100% of the height (H) of the metal frame 100, the configuration of the metal frame 100 according to the second and third embodiments to be described later. can have

For example, the height (H) of the metal frame 100 preferably has a height of 50 μm to 1000 μm, whereas the height (h) of the molding member 130 is 30% of the height of the metal frame 100. It is desirable to have more than one.

The semiconductor chip 200 may be disposed on the metal frame 100 . For example, one surface of the semiconductor chip 200 may be an active surface including an active region where a circuit is formed. Meanwhile, a rear surface opposite to the active surface of the semiconductor chip 200 may be an inactive surface. Unlike this, both sides of the semiconductor chip 200 include a case where both surfaces are provided as active surfaces. A single or multiple pads for exchanging signals with the outside may be provided on the active surface of the semiconductor chip 200, and the pads may be formed of a conductive material film such as aluminum (Al). The pad includes one integrally formed with the semiconductor chip 200 .

An active surface of the semiconductor chip 200 on which pads are formed may face the wiring unit 400 . That is, the inactive surface of the semiconductor chip 200 may be disposed to face the metal frame 100 through the adhesive layer 500 formed below the inactive surface.

In addition, the semiconductor chip 200 of the sensor package according to the present invention may include light sensing, fingerprint sensing, electromagnetic sensing, and medical sensing chips. When the semiconductor chip 200 is applied as an optical sensor, irradiated light may be detected, and an electrical signal of a corresponding state may be generated and output according to the detected light. When the semiconductor chip 200 is applied as a fingerprint sensor, a sensing unit for detecting a fingerprint may be included on an active surface of the semiconductor chip 200 . The sensing unit may be formed in various forms, and may be formed using, for example, a conductor. Accordingly, the active surface of the semiconductor chip 200 according to the present invention may be formed in an open form with respect to the wiring unit 400, and external information, for example, information of incident light or user information, may be formed by the open active surface. Fingerprint information by a finger may be collected.

The semiconductor chip 200 according to the present invention may include a plurality of semiconductor chips 200 , and may include, for example, a first semiconductor chip 210 and a second semiconductor chip 220 . The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on the metal frame 100 and spaced apart from each other. Here, the first semiconductor chip 210 may have a plurality of pads 211 and 212 , and the second semiconductor chip 220 may have a single pad 221 . Also, the first semiconductor chip 210 and the second semiconductor chip 220 may be electrically connected to each other through the wiring unit 400 .

The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed to face the heat sink 120 of the metal frame 100 through the adhesive layer 500 . Accordingly, since heat generated in the first semiconductor chip 210 and the second semiconductor chip 220 can be efficiently or forcibly transferred to the outside, heat dissipation characteristics can be improved.

In addition, since the semiconductor chips 200 are arranged to be seated on the metal frame 100, reliability of the semiconductor chips 200 may be improved during manufacturing. That is, in the process of molding using the molding layer 300, the molding layer 300 flows or thermal deformation occurs, causing drift or warpage of the semiconductor chip 200 to occur unintentionally ( Warpage) can be prevented. Moreover, even if an external impact is applied to the package, the impact applied to the semiconductor chip 200 can be reduced by primarily absorbing and dispersing the impact by the metal frame 100, thereby increasing the rigidity of the package itself. There are advantages.

A molding layer 300 may be formed on the metal frame 100 and the semiconductor chip 200 . In addition, the molding layer 300 may be formed to bury the top and side surfaces of the active surface of the semiconductor chip 200 and the top of the metal frame 100 . That is, the first surface 101 of the metal frame 100 may be exposed from the molding layer 300 .

In addition, the molding layer 300 may include through vias 310 and normal vias 320 . The through via 310 and the normal via 320 are filled with a conductive material, and the through via 310 may be formed to electrically connect the I/O pad 110 and the wiring unit 400, and the normal via ( 320 may be formed to connect a pad of the semiconductor chip 200 and the wiring unit 400 . Accordingly, the first semiconductor chip 210 may be electrically connected to the I/O pad 110 and the second semiconductor chip 220 may be electrically connected to the first semiconductor chip 210 .

The molding layer 300 is an insulating film such as PI (Polyimide), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole) rather than conventionally used epoxy mold compound (EMC) or encapsulant , BT (Bismaleimide Triazine), phenolic resin, or epoxy. Therefore, in the wiring part 400 process to be described later, the wiring layer 410 may be directly formed on the molding layer 300 without the conventional insulating layer formed under the wiring layer. That is, since the wiring layer 410 can be directly formed on the molding layer 300 without consuming a separate insulating layer on the molding layer 300, the process of forming a separate insulating layer under the wiring layer 410 is not necessary. may be omitted. Therefore, it is possible to reduce the consumption of the insulating layer, shorten the process time, and have an effect of reducing the thickness of the package according to the reduction of the insulating layer.

In addition, the molding layer 300 according to the present invention may have light transmission properties. Since a conventional sensor package forms a molding layer with a molding compound (EMC) and an insulating layer is formed on the active layer of the semiconductor chip 200, the molding layer does not need to be light-transmitting, but the sensor package according to the present invention is a semiconductor chip ( 200) is a molding layer (300) formed of PI (Polyimide), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (Bismaleimide Triazine), phenolic resin, or epoxy. ) and since the insulating layer 420 surrounding the wiring layer 410 is formed on the molding layer 300, the molding layer 300 may have light-transmitting properties in order to function as a sensor package in the package according to the present invention. have.

The wiring unit 400 may be formed on the molding layer 300 . For example, the wiring unit 400 may include a wiring layer 410 and an insulating layer 420 . The insulating layer 420 is formed of an insulating material to insulate the wiring layer 410 .

The wiring layer 410 includes a conductive material and may be formed on the molding layer 300 through a rearrangement process. However, when the semiconductor chip 200 of the sensor package according to the present invention functions as an optical sensor or a fingerprint sensor, the wiring layer 410 is formed such that the active surface of the semiconductor chip 200 is open so that the semiconductor chip 200 ) It is preferable to have the active side of the open form. For example, the first semiconductor chip 210 may be electrically connected to the I/O pad 110 through the normal via 320, the wiring layer 410, and the through via 310, and the normal via 320 and the wiring layer It may be electrically connected to the second semiconductor chip 220 through 410 .

The wiring layer 410 may include metal as a conductive material. For example, it may include copper, copper alloys, aluminum, or aluminum alloys.

The insulating layer 420 may be formed on the wiring layer 410 to insulate the wiring layer 410 from the outside. That is, the insulating layer 420 may be stacked on the exposed surfaces of the molding layer 300 and the wiring layer 410 . However, although the drawing shows that the insulating layer 420 seals the wiring layer 410, the insulating layer 420 may be provided to expose a part of the wiring layer 410, otherwise the exposed wiring layer 410 It can be electrically connected to the outside (main board, semiconductor chip, package, etc.) through. That is, a POP (Package On Package) structure or a SIP (System in Package) structure in which packages are stacked on a package may be taken. Also, a plurality of semiconductor chips may be disposed adjacent to or in contact with each other in the width direction.

Various types of patterns 600 for sensing may be formed on the insulating layer 420 . For example, a lens pattern or a guide pattern may be formed.

2 is a cross-sectional view showing a second embodiment according to the sensor package of the present invention.

Referring to FIG. 2 , a sensor package according to a second embodiment of the present invention includes a metal frame 100 , a semiconductor chip 200 , a molding layer 300 and a wiring unit 400 .

As in the first embodiment, the metal frame 100 according to the second embodiment may include I/O pads 110 spaced apart from both sides around the heat sink 120 .

However, the metal frame 100 according to the second embodiment may be formed such that the molding member 130 surrounds all of the side surfaces 103 of the metal frame 100 . That is, the molding member 130 is formed to surround the side surface of the I/O pad 110, and both the first surface 101 and the second surface 102 adjacent to the side surface 103 of the metal frame 100 are molded. It may be formed to be filled with the member 130 . In this case, the upper surface of the I/O pad 110 may be formed to be flush with the second surface 102 of the metal frame 100 .

In addition, since the semiconductor chip 200 and the wiring unit 400 may have the same shape as the first embodiment, the heat dissipation effect of the heat sink 120 of the metal frame 100 and the movement of the semiconductor chip 200 may occur. And it has the effect of preventing the occurrence of warping.

3 is a cross-sectional view showing a third embodiment according to the sensor package of the present invention.

Referring to FIG. 3 , a sensor package according to a third embodiment of the present invention includes a metal frame 100 , a semiconductor chip 200 , a molding layer 300 and a wiring unit 400 .

As in the first embodiment, the metal frame 100 according to the third embodiment may include I/O pads 110 spaced apart from both sides around the heat sink 120 .

However, in the metal frame 100 according to the third embodiment, as in the second embodiment, the molding member 130 is formed to surround all the side surfaces 103 of the metal frame 100, and the I/O pad ( 110 may include a protrusion 111 protruding from the second surface 102 of the metal frame 100 toward the molding layer 300 . That is, one side of the I/O pad 110 is exposed to the outside, but the other side protrudes into the molding layer 300 by the protrusion 111 and is connected to the through via 310 of the molding layer 300. can take

Therefore, when forming a pattern for the through vias 310 of the molding layer 300, the stability of pattern formation according to the high thickness of the molding layer 300 can be secured, and the electrical characteristics can be improved by shortening the distance to the wiring unit 400. can improve Here, the height of the protruding portion 111 is selected according to the thickness of the semiconductor chip 200 or the thickness of the molding layer 300, but preferably has a height lower than that of the molding layer 300. A side surface of the I/O pad 110 and a side surface of the heat sink 120 excluding the protrusion 111 may be filled with the molding member 130 .

In addition, the molding layer 300 is formed on the metal frame 100 to bury the protrusions 111 of the first semiconductor chip 210, the second semiconductor chip 220, and the I/O pad 110. It can be. Thus, the through vias 310 formed in the molding layer 300 may be formed to expose the upper surface of the protruding portion 111 .

In addition, since the semiconductor chip 200 and the wiring unit 400 may have the same shape as the first embodiment, the heat dissipation effect of the heat sink 120 of the metal frame 100 and the movement of the semiconductor chip 200 may occur. And it has the effect of preventing the occurrence of warping.

4 is a cross-sectional view showing a fourth embodiment according to the sensor package of the present invention.

Referring to FIG. 4 , a sensor package according to a fourth embodiment of the present invention includes a metal frame 100 , a semiconductor chip 200 , a molding layer 300 and a wiring unit 400 .

As in the first embodiment, the metal frame 100 according to the fourth embodiment may include I/O pads 110 spaced apart from both sides around the heat sink 120 .

However, in the metal frame 100 according to the fourth embodiment, the molding member 130 is formed to surround the side surface 103 of the metal frame 100, and the I/O pad 110 is formed of the metal frame 100. It may be formed to extend to the side surface 103 along the first surface 101 . That is, the molding member 130 formed on the side surface 103 of the metal frame 100 may be formed to fill the upper portion of the extended I/O pad 110 .

At this time, the height (h) of the molding member 130 formed on the side surface 103 of the metal frame 100 is the height (H) of the metal frame 100, that is, the metal frame 100, as in the first embodiment. It may be formed to be 30% or more of the height from the first surface 101 to the second surface 102 of the. More specifically, it may have a height ranging from 30% to 100%.

In addition, since the semiconductor chip 200 and the wiring unit 400 may have the same shape as the first embodiment, the heat dissipation effect of the heat sink 120 of the metal frame 100 and the movement of the semiconductor chip 200 may occur. And it has the effect of preventing the occurrence of warping.

5 is a cross-sectional view showing a fifth embodiment according to the sensor package of the present invention.

Referring to FIG. 5 , a sensor package according to a fifth embodiment of the present invention includes a metal frame 100 , a semiconductor chip 200 , a molding layer 300 and a wiring unit 400 .

As in the first embodiment, the metal frame 100 according to the fifth embodiment may include I/O pads 110 spaced apart from both sides around the heat sink 120 .

However, in the metal frame 100 according to the fifth embodiment, the I/O pads 110 are formed to extend to the side surfaces 103 of the metal frame 100, and the I/O pads 110 extend to the metal frame 100. ) It may be formed to fill all of the side surfaces 103 of. Accordingly, the first surface 101 adjacent to the side surface 103 of the metal frame 100 may be formed to expose the I/O pads 110, and the second surface 102 may be formed to expose the exposed I/O pads 110. ) may be filled by the molding layer 300 .

In addition, since the semiconductor chip 200 and the wiring unit 400 may have the same shape as the first embodiment, the heat dissipation effect of the heat sink 120 of the metal frame 100 and the movement of the semiconductor chip 200 may occur. And it has the effect of preventing the occurrence of warping.

6 is a cross-sectional view showing a sixth embodiment according to the sensor package of the present invention.

Referring to FIG. 6 , a sensor package according to a sixth embodiment of the present invention includes a metal frame 100 , a semiconductor chip 200 , a molding layer 300 and a wiring unit 400 .

As in the first embodiment, the metal frame 100 according to the sixth embodiment may include I/O pads 110 spaced apart on both sides with the heat sink 120 as the center.

However, the metal frame 100 according to the sixth embodiment is formed such that the I/O pad 110 extends to the side surface 103 of the metal frame 100, as in the fifth embodiment, but the I/O pad 110 may include a protrusion 111 protruding from the second surface 102 of the metal frame 100 toward the molding layer 300 . That is, one side of the I/O pad 110 is exposed to the outside, but the other side protrudes into the molding layer 300 by the protrusion 111 and is connected to the through via 310 of the molding layer 300. can take

Therefore, when forming a pattern for the through vias 310 of the molding layer 300, the stability of pattern formation according to the high thickness of the molding layer 300 can be secured, and the electrical characteristics can be improved by shortening the distance to the wiring unit 400. can improve Here, the height of the protruding portion 111 is selected according to the thickness of the semiconductor chip 200 or the thickness of the molding layer 300, but preferably has a height lower than that of the molding layer 300. A space between the I/O pad 110 and the heat sink 120 excluding the protrusion 111 may be filled by the molding member 130 .

In addition, the molding layer 300 is formed on the metal frame 100 to bury the protrusions 111 of the first semiconductor chip 210, the second semiconductor chip 220, and the I/O pad 110. It can be. Thus, the through vias 310 formed in the molding layer 300 may be formed to expose the upper surface of the protruding portion 111 .

In addition, since the semiconductor chip 200 and the wiring unit 400 may have the same shape as the first embodiment, the heat dissipation effect of the heat sink 120 of the metal frame 100 and the movement of the semiconductor chip 200 may occur. And it has the effect of preventing the occurrence of warping.

As described above, the metal frame 100 according to the present invention may have various shapes. However, the metal frame 100 according to the first to third embodiments is formed such that the molding member 130 is exposed on the first surface 101 adjacent to the side surface 103 of the metal frame 100 . This has the effect of improving the ssoing quality during the sawing process.

For example, the ssoing process proceeds from the first surface 101 of the metal frame 100 to the second surface 102 . That is, when the part where the sawing process starts is formed of a metal material such as the I/O pad 110, the metal part is burr, cracked or delaminated by the sawing process. ) and the like may occur, so that the metal frame 100 may have a quality deterioration problem due to the ssoing process. Therefore, when the first surface 101 adjacent to the side surface 103 of the metal frame 100 is exposed by the molding member 130, like the metal frame 100 according to the first to third embodiments, these It has the effect of preventing the problem of quality deterioration by the sawing process.

7 to 11 are cross-sectional views for explaining a method of manufacturing the sensor package shown in FIG. 1 according to a first preferred embodiment of the present invention.

First, referring to FIG. 7 , a metal frame including an I/O pad 110 and a heat sink 120 and filled with molding members 130 on the side surfaces of the I/O pad 110 and the heat sink 120. (100) is disposed on the carrier substrate (10). In this case, the metal frame 100 may be disposed so that the first surface 101 of the metal frame 100 is in contact with the carrier substrate 10 .

Referring to FIG. 8 , a semiconductor chip 200 is disposed on the second surface 102 of the metal frame 100 . That is, an adhesive layer 500 for adhering the semiconductor chip 200 to the heat sink 120 of the metal frame 100 is formed, and the semiconductor chip 200 is seated and adhered to the adhesive layer 500. . Here, the adhesive layer 500 may be a liquid adhesive or adhesive tape.

The semiconductor chip 200 may include a first semiconductor chip 210 and a second semiconductor chip 220, and the first semiconductor chip 210 may be spaced apart from the second semiconductor chip 220. . In this case, the first semiconductor chip 210 and the second semiconductor chip 220 may be bonded on the adhesive layer 500 such that their inactive surfaces face the heat sink 120 .

Referring to FIG. 9 , a molding layer 300 is formed on the metal frame 100 , the first semiconductor chip 210 and the second semiconductor chip 220 . That is, the molding layer 300 may be formed to bury the top and side surfaces of the active surface of the semiconductor chip 200 and the top of the metal frame 100 .

The molding layer 300 is an insulating film such as PI (Polyimide), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole) rather than conventionally used epoxy mold compound (EMC) or encapsulant , BT (Bismaleimide Triazine), phenolic resin, or epoxy. Therefore, in the wiring part 400 process to be described later, the wiring layer 410 may be directly formed on the molding layer 300 without the conventional insulating layer formed under the wiring layer.

In addition, through vias 310 and normal vias 320 may be formed in the molding layer 300 through a patterning process, as shown in FIG. 9 . Here, the through vias 310 are formed to expose the I/O pads 110, and the normal vias 320 are formed by the pads 211 and 212 of the first semiconductor chip 210 and the pads of the second semiconductor chip 220 ( 221) may be formed to be exposed.

Referring to FIGS. 10 and 11 , a wiring unit 400 is formed on the molding layer 300 . Before the wiring part 400 is formed, the through via 310 and the normal via 320 may be filled with a conductive material. The conductive material may include, for example, copper, copper alloy, aluminum, or aluminum alloy, and another example may be a conductive paste or solder resist ink.

First, as shown in FIG. 10 , the wiring layer 410 is formed to be in contact with the molding layer 300, and the normal via 320 and the through via 310 are connected to form the first semiconductor chip 210 and the I/O The pad 110 may be electrically connected, and the normal via 320 formed on the pad 212 of the first semiconductor chip 210 and the normal via 320 formed on the pad 221 of the second semiconductor chip 220 ) may be connected to electrically connect the first semiconductor chip 210 and the second semiconductor chip 220 .

However, when the semiconductor chip 200 of the sensor package according to the present invention functions as an optical sensor or a fingerprint sensor, the wiring layer 410 is formed such that the active surface of the semiconductor chip 200 is open so that the semiconductor chip 200 ) It is preferable to have the active side of the open form.

The wiring layer 410 may include metal as a conductive material, for example, copper, copper alloy, aluminum, or aluminum alloy, and may be formed using various methods such as deposition, plating, and printing. .

As described above, PI (Polyimide), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (Bismaleimide Triazine), phenolic resin or epoxy as an insulating film as the molding layer 300 The wiring layer 410 can be directly formed on the molding layer 300 without consuming a separate insulating layer on the molding layer as in the prior art. Therefore, since the process of forming a separate insulating layer under the wiring layer 410 can be omitted, the consumption of the insulating layer can be reduced, the process time can be shortened, and the thickness of the package can be reduced due to the reduction of the insulating layer. there is

After the wiring layer 410 is formed, an insulating layer 420 is formed as shown in FIG. 11 . The insulating layer 420 may be stacked on exposed surfaces of the molding layer 300 and the wiring layer 410 . Although the drawing shows that the insulating layer 420 covers the wiring layer 410 so that it is not exposed to the outside, a portion of the insulating layer 420 may be removed to expose the wiring layer 410 to the outside. At this time, the exposed wiring layer 410 can be used as a passage through which it can be electrically connected to the outside.

The insulating layer 420 may include an insulating material, such as oxide, nitride, epoxy molding compound, or polyimide, but is preferably formed of the same material as the molding layer 300 .

After the wiring unit 400 is formed, as shown in FIG. 1 , various types of patterns 600 for sensing are formed on the insulating layer 420 . For example, a lens pattern or a guide pattern may be formed. After the pattern 600 is formed, the carrier substrate 10 may be removed. Accordingly, the first surface 101 of the metal frame 100 is exposed to the outside and may perform a heat dissipation function of dissipating heat generated in the semiconductor chip 200 by the heat sink 120 to the outside.

12 to 14 are cross-sectional views for explaining a method of manufacturing the sensor package shown in FIG. 3 according to a third preferred embodiment of the present invention.

Referring to FIG. 12 , it includes an I/O pad 110 having a protrusion 111 and a heat sink 120, and a molding member 130 is provided on the side of the I/O pad 110 and the heat sink 120. A filled metal frame 100 is disposed on the carrier substrate 10 . In this case, the metal frame 100 may be disposed so that the first surface 101 of the metal frame 100 is in contact with the carrier substrate 10 .

After the metal frame 100 is disposed on the carrier substrate 10 , the first semiconductor chip 210 and the second semiconductor chip 220 are disposed on the second surface 102 of the metal frame 100 . Here, the first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on the heat sink 120 and adhered to the heat sink 120 through the adhesive layer 500 .

Referring to FIG. 13 , a molding layer 300 is formed on the metal frame 100 , the first semiconductor chip 210 and the second semiconductor chip 220 . In this case, the molding layer 300 may be formed to bury the protrusions 111 of the first semiconductor chip 210 , the second semiconductor chip 220 , and the I/O pad 110 . Therefore, the height of the protrusion 111 is preferably lower than that of the molding layer 300 .

In addition, through vias 310 and normal vias 320 may be formed in the molding layer 300 through a patterning process. Here, the through via 310 has a lower height than the through via 310 of the first embodiment because it is formed to expose the protruding portion 111 of the I/O pad 110. Accordingly, stability can be ensured during pattern formation of the through-vias 310, and electrical characteristics can be improved by shortening the distance between the I/O pads 110 and the wiring unit 400 by the protrusions 111.

Referring to FIG. 14 , a wiring unit 400 is formed on the molding layer 300 . Before the wiring part 400 is formed, the through via 310 and the normal via 320 may be filled with a conductive material.

The wiring layer 410 is formed to be in contact with the molding layer 300, and electrically connects the first semiconductor chip 210 and the I/O pad 110 by connecting the normal via 320 and the through via 310. The normal via 320 formed on the pad 212 of the first semiconductor chip 210 and the normal via 320 formed on the pad 221 of the second semiconductor chip 220 are connected to each other so that the first semiconductor chip 210 and the second semiconductor chip 220 may be electrically connected. In addition, it may be electrically connected to various patterns 600 formed on the insulating layer 420 through the wiring layer 410 and the through via 310 .

After the wiring layer 410 is formed, the insulating layer 420 is formed. The insulating layer 420 may be stacked on exposed surfaces of the molding layer 300 and the wiring layer 410 .

After the wiring unit 400 is formed, various types of patterns 600 for sensing are formed on the insulating layer 420 as shown in FIG. 3 . After the pattern 600 is formed, the carrier substrate 10 is removed, and the first surface 101 of the metal frame 100 is exposed.

As described above, the sensor package and method of manufacturing the same according to the present invention arranges the semiconductor chip 200 on the metal frame 100 having the I/O pad 110 and the heat sink 120, so that the semiconductor chip 200 ), heat dissipation characteristics can be improved, and the movement of the semiconductor chip 200, which can occur due to the flow or thermal deformation of the molding layer 300 during the manufacturing process, can be efficiently transferred to the outside. Drift or warpage can be prevented. In addition, even if an external impact is applied to the package, the impact applied to the semiconductor chip 200 can be reduced by primarily absorbing and dispersing the impact by the metal frame 100, thereby increasing the rigidity of the package itself. There are advantages.

On the other hand, the embodiments of the present invention disclosed in the present specification and drawings are only presented as specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is obvious to those skilled in the art that other modifications based on the technical idea of the present invention can be implemented.

100: metal frame 110: I / O pad
120: heat sink 130: molding member
200: semiconductor chip 300: molding layer
310: through via 320: normal via
400: wiring part 410: wiring layer
420: insulating layer 500: adhesive layer

Claims (12)

a metal frame having a first surface exposed to the outside and a second surface opposite to the first surface;
a semiconductor chip disposed on the second surface of the metal frame;
a molding layer to bury the semiconductor chip; and
a wiring portion electrically connected to a pad of the semiconductor chip and formed on the molding layer;
The metal frame,
a heat sink on which the semiconductor chip is seated;
an I/O pad spaced apart from the heat sink; and
A molding member surrounding side surfaces of the I/O pad and the heat sink,
The molding layer,
a through via electrically connected to the wiring unit and extending to the I/O pad; and
a normal via electrically connected to the wiring unit and extending to a pad of the semiconductor chip;
The I/O pad includes a protruding portion protruding from the second surface of the metal frame, having a height lower than that of the molding layer, and electrically connected to the through-via. According to claim 1,
Wherein the I / O pads are spaced apart from each other on both sides of the heat sink. According to claim 1,
Wherein the molding member is formed to surround both sides of the I/O pad. delete delete delete delete delete According to claim 1,
Wherein the molding member is formed to be exposed on the first surface adjacent to the side surface of the metal frame. The method of claim 1, wherein the semiconductor chip,
a first semiconductor chip electrically connected to the through via; and
A sensor package including a second semiconductor chip disposed adjacent to the first semiconductor chip and electrically connected to the first semiconductor chip through the wiring part. preparing a metal frame having an I/O pad and a heat sink and having a molding member formed thereon;
disposing the metal frame on a carrier substrate so that the first surface of the metal frame is in contact with it;
disposing a semiconductor chip on a second surface opposite to the first surface of the metal frame;
burying the semiconductor chip with a molding layer;
forming through vias on the molding layer to expose the I/O pads and forming normal vias to expose the pads of the semiconductor chip;
filling the through via and the normal via with a conductive material; and
Forming a wiring part on the molding layer to electrically connect the semiconductor chip and the I/O pad;
The I/O pad includes a protruding portion that protrudes from the second surface of the metal frame, has a height lower than that of the molding layer, and is electrically connected to the through-via. delete

Images