KR102456559B1 - Power semiconductor device capable of preventing false turn-on - Google Patents

Abstract

A power semiconductor device having a built-in malfunction turn-on prevention circuit is provided. A power semiconductor device with a built-in malfunction turn-on prevention circuit is formed on a semiconductor substrate, a power semiconductor device having a gate terminal connected to a first node, is formed on the semiconductor substrate, a source is connected to the first node, and a second node a self-turn-on transistor having a gate connected to , a drain connected to a source terminal or an emitter terminal of the power semiconductor device, and connected to the first node and the second node, and transmits a gate-on signal from the second node and a signal transmission device that transmits the signal to the gate terminal and transmits a displacement signal generated when the power semiconductor device is turned off from the gate terminal to the second node.

Description

TECHNICAL FIELD [0001] Power semiconductor device capable of preventing false turn-on

The present invention relates to a power semiconductor device having a built-in malfunction turn-on prevention circuit.

The present invention is the result of the future growth engine of the materials and parts industry of the Korea Institute of Industrial Technology Evaluation and Planning - New industry creation type power semiconductor commercialization technology development project (Project unique number: 10080429, research project name: 1200V high-efficiency Super Junction Trench Si IGBT technology development) to be.

The half-bridge circuit is composed of a high-side power semiconductor device and a low-side power semiconductor device. 1 is a diagram for explaining a malfunctioning turn-on that occurs in a half-bridge circuit, (a) is a diagram for explaining a phenomenon in which a low-side power semiconductor device is turned on erroneously when the high-side power semiconductor device is turned on and (b) is a view for explaining a conventional structure for solving a malfunctioning turn-on.

Referring to FIG. 1A , when the high-side power semiconductor device is turned on in the half-bridge circuit, the collector-emitter voltage V _CE of the low-side power semiconductor device increases. Due to this, the collector-gate capacitance C _GC of the low-side power semiconductor device is discharged, so that a voltage higher than or equal to the threshold voltage can be applied to the gate of the low-side power semiconductor device (the low-side within the rectangle in Fig. 1(a)) V _GE ). When the high-side power semiconductor device and the low-side power semiconductor device are turned on (arm-short phenomenon) at the same time, a considerable amount of current flows when the power supply voltage of the half-bridge circuit is directly applied, and the power semiconductor device is seriously damaged. .

Referring to FIG. 1B , a mirror clamping MOSFET may be connected between the gate and the source of the power semiconductor device in order to prevent malfunctioning turn-on. The mirror clamping MOSFET short-circuits the gate and source of the power semiconductor device when the power semiconductor device is turned off, thereby maintaining the gate voltage of the power semiconductor device at substantially 0 V (strictly, when the clamping MOSFET is turned on, the source- drain voltage V _SD ). Due to this, it is possible to prevent an increase in gate voltage caused by a discharge current due to a decrease in the drain-gate capacitance C _GD when the other connected power semiconductor devices are turned on, thereby preventing a malfunctioning turn-on. However, this method requires a separate drive and control circuit to control the mirror clamping MOSFET.

The above-mentioned background art is technical information possessed by the inventor for the derivation of the present invention or acquired in the process of derivation of the present invention, and cannot necessarily be said to be a known technique disclosed to the general public prior to the filing of the present invention.

Korean Patent Application Laid-Open No. 10-2019-0080764 (Power conversion device and semiconductor device)

An object of the present invention is to provide a solution capable of preventing erroneous turn-on of a power semiconductor device without the need to add a separate driving and control circuit.

Objects other than the present invention will be easily understood through the following description.

According to one aspect of the present invention, a power semiconductor device having a built-in malfunction turn-on prevention circuit is provided. A power semiconductor device with a built-in malfunction turn-on prevention circuit is formed on a semiconductor substrate, a power semiconductor device having a gate terminal connected to a first node, is formed on the semiconductor substrate, a source is connected to the first node, and a second node a self-turn-on transistor having a gate connected to , a drain connected to a source terminal or an emitter terminal of the power semiconductor device, and connected to the first node and the second node, and transmits a gate-on signal from the second node The power semiconductor device may include a signal transmission device that transmits it to a gate terminal and transmits a displacement signal generated when the power semiconductor device is turned off from the gate terminal to the second node. Here, the self-turn-on transistor may be turned off when the gate-on signal is applied, and turned on when the displacement signal is applied to short-circuit the gate terminal and the source terminal or the emitter terminal of the power semiconductor device.

In an embodiment, the signal transmission device may include a first resistor and a first diode connected in series for transmitting the gate-on signal, and a second resistor and a second diode connected in series for transmitting the displacement signal.

In an embodiment, when the voltage of the node 2 is greater than the voltage of the node 1 by the gate-on signal, the self-turn-on transistor is turned off, and the voltage of the node 1 is changed to the voltage of the node 2 by the displacement signal When the threshold voltage of the self-turn-on transistor is greater than the threshold voltage, the self-turn-on transistor may be turned on.

In an embodiment, the self-turn-on transistor may be a P-type MOSFET.

In an embodiment, the absolute value of the threshold voltage of the self-turn-on transistor may be smaller than the threshold voltage of the power semiconductor device.

In an embodiment, a source-drain breakdown voltage of the self-turn-on transistor may be greater than a gate guarantee voltage of the power semiconductor device.

In an embodiment, the power semiconductor device may be a MOSFET transistor.

In an embodiment, the power semiconductor device may be an insulated gate bipolar transistor.

Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

According to an embodiment of the present invention, the malfunction turn-on prevention circuit can prevent the malfunction turn-on of the power semiconductor device without a driving and control circuit for driving it, thereby preventing the power semiconductor device from being damaged. .

1 is an exemplary diagram for explaining a malfunctioning turn-on occurring in a half-bridge circuit.
2 is a circuit diagram showing a power semiconductor device having a built-in malfunction turn-on prevention circuit according to an embodiment of the present invention.
3 is a circuit diagram showing a state before turning on the malfunction turn-on prevention circuit according to an embodiment of the present invention.
Figure 4 is a circuit diagram showing a state after the turn-on erroneous turn-on prevention circuit according to an embodiment of the present invention.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the present invention, if it is determined that a detailed description of a related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

When an element, such as a layer, region, or substrate, is described as being “on” or extending “onto” another element, the element may be directly on or extending directly over the other element and , or an intermediate intervening element may exist. On the other hand, when an element is referred to as being “directly on” or extending “directly onto” another element, the other intermediate elements are absent. Also, when an element is described as being “connected” or “coupled” to another element, that element may be directly connected or coupled directly to the other element, or intervening elements may be present. have. On the other hand, when one element is described as being "directly connected" or "directly coupled" to another element, there is no other intermediate element present.

“below” or “above” or “upper” or “lower” or “horizontal” or “lateral” or “vertical” Relative terms such as "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It should be understood that these terms are intended to encompass other orientations of the device in addition to the orientation depicted in the drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the related drawings.

2 is a circuit diagram illustrating a power semiconductor device having a built-in malfunction turn-on prevention circuit according to an embodiment of the present invention.

Referring to FIG. 2 , the power semiconductor device 100 having a built-in malfunction turn-on prevention circuit includes a power semiconductor device 110 and a malfunction turn-on prevention circuit 120 . The power semiconductor device 110 is a vertical device in which current flows in a vertical direction of the device, and may be, for example, an insulated gate bipolar transistor, a power MOSFET, or the like. Hereinafter, it is assumed that the power semiconductor device is an insulated gate bipolar transistor.

The malfunction turn-on prevention circuit 120 is disposed between the gate terminal (Node 1) and the gate signal input terminal (Node 2) of the power semiconductor device 110 . The malfunction turn-on prevention circuit 120 includes a signal transfer device that transmits a gate signal (a gate-on signal or a gate-off signal) inputted to the node 1 to the node 2 and a displacement signal input to the node 1 to the node 2; The self-turn-on transistor 130 may be turned on and off by the potential difference between the node 1 and the node 2 .

The signal transmission element provides a first signal path and a second signal path. A first signal path includes a turn-on resistor R _on and a diode D _on connected in series, and a second signal path includes a turn-off resistor R _off and a diode D _off connected in series. Here, as will be described below, the resistance value of the resistor R _off and the forward voltage drop of the diode D _off must be designed so that the displacement current is properly branched from the node 1 when the self-turn-on transistor 130 is turned on. In addition, the breakdown voltages of the diode D _on and the diode D _off are preferably higher than the gate insulation guarantee voltage of the power semiconductor device 110 .

The self-turn-on transistor 130 is a P-channel MOSFET. The self-turn-on transistor 130 includes a P-type well formed on the N-type drift layer, an N-type well formed in the P-type well, P+ source and P+ drain formed to extend from the top surface of the N-type well into the N-type well, and A gate may be formed between the P+ source and the P+ drain.

Referring to the cross-sectional shape of the power semiconductor device, it can be seen that the vertical power semiconductor device 110 and the horizontal self-turn-on transistor 130 are formed in the same semiconductor substrate. The power semiconductor device 110 may be formed in the active region, and the self-turn-on transistor 130 may be formed in a peripheral region of the active region. Meanwhile, although not shown, the signal transfer device may be formed on the same semiconductor substrate as the vertical power semiconductor device 110 and the horizontal self-turn-on transistor 130 .

The source, gate, and drain of the self-turn-on transistor 130 are electrically coupled to the node 1 , the node 2 and the emitter terminal of the power semiconductor device 110 , respectively. While the gate signal (gate-on signal) is input to the power semiconductor device 110 , the self-turn-on transistor 130 is turned off.

On the other hand, when the power semiconductor device 110 is turned off, the self-turn-on transistor 130 is turned on by the potential difference between the node 1 and the node 2, that is, the gate terminal and the emitter of the node 1, that is, the power semiconductor device 110 . short the terminals. Due to this, the gate voltage V _GE of the power semiconductor device 110 becomes substantially 0 V (strictly, the source-drain voltage V _SD when the self-turn-on transistor is turned on), and the power semiconductor device 110 is completely turned off. can be The operation of the self-turn-on transistor 130 will be described in detail below with reference to FIGS. 3 and 4 .

The self-turn-on transistor 130 should be designed so as not to affect the characteristics of the power semiconductor device 110 . Accordingly, the self-turn-on transistor 130 may (1) have a breakdown voltage higher than the gate insulation guarantee voltage of the power semiconductor device, and (2) have an absolute value of the threshold voltage equal to or smaller than the threshold voltage of the power semiconductor device. and (3) a source-drain voltage V _DS or an on-state resistance R _ON at turn-on lower than the threshold voltage of the power semiconductor device. In particular, when the absolute value of the threshold voltage of the self-turn-on transistor 130 is less than the threshold voltage of the power semiconductor device 110 , the self-turn-on transistor 130 may be turned on before the power semiconductor device 110 malfunctions. .

3 is a circuit diagram illustrating a state before the malfunction protection circuit is turned on according to an embodiment of the present invention.

Referring to FIG. 3 , a low-side power semiconductor device 100L among two power semiconductor devices connected in series is in an off state by applying a gate-off signal. Here, the power semiconductor device 110 may be an IGBT. At this time, when the gate-on signal is applied to the high-side power semiconductor device 100H and the high-side power semiconductor device 100H starts to be turned on, the collector-emitter voltage V _CE of the low-side semiconductor device 100L is will rise The low-side power semiconductor device 100L maintains an off state, and the self-turn-on transistor 130 is also turned off. A displacement signal I _dis in the form of a current in proportion to the voltage increase rate between the collector-emitter of the low-side semiconductor device (IGBT) is generated through the second signal path 145 in the direction from node 1 to node 2 as shown in FIG. 3 .

While the gate-on signal is applied to the low-side power semiconductor device 100L, the self-turn-on transistor 130 is turned off. Specifically, as the gate-on signal passes through the first signal path 140 , it generates a voltage drop in Ron and a forward voltage drop in Don. As a result, the voltage of node 1 becomes lower than the voltage of node 2 , so that the self-turn-on transistor 130 , which is a P-channel MOSFET, is maintained in a turned-off state.

Specifically, when the gate signal applied to the gate signal input terminal of the low-side power semiconductor device 100L is changed from the gate-on signal to the gate-off signal, the turn-off process of the low-side power semiconductor device 100L starts. . During the turn-off process, the collector-emitter voltage V _CE of the low-side power semiconductor device 100L rapidly rises. The sharp rise of the collector-emitter voltage V _CE discharges the gate-collector capacitor C _GC of the low-side power semiconductor device 100L. This generates a displacement signal I _dis in the form of a current proportional to the product of the rate of change of the gate-collector capacitor C _GC and the collector-emitter voltage V _CE (= capacitance of C _GC x dV _CE /dt ).

When there is no malfunction turn-on prevention circuit, the displacement signal I _dis may charge the gate-emitter capacitor C _GE of the low-side power semiconductor device 100L. For this reason, when the gate-emitter voltage V _GE of the low-side power semiconductor device 100L increases to more than the threshold voltage of the low-side power semiconductor device 100L, the low-side power semiconductor device 100L may malfunctionly turn on. .

According to the malfunction turn-on prevention circuit, the displacement signal I _dis drops the voltage V _node2 of the node 2 while flowing through the second signal path 145 . In detail, the voltage V _node2 becomes lower than the voltage V _node1 of the node 1 by I _dis x R _off + V _f . where V _f is the forward voltage drop of Doff. For example, if the threshold voltage of the self-turn-on transistor 130 is -3V and the voltage drop by the second signal path is greater than or equal to the absolute value of -3V (eg, -3.1V), the self-turn-on transistor 130 is ) can be turned on.

When the gate-source voltage V _GS of the self-turn-on transistor 130 becomes less than or equal to the threshold voltage of the self-turn-on transistor 130 due to the voltage drop by the second signal path, the self-turn-on transistor 130 is turned on. Due to this, the gate-emitter capacitor C _GE cannot be charged above the source-drain voltage V _SD of the turned-on self-turn-on transistor 130 , so that the erroneous turn-on of the low-side power semiconductor device 100L is prevented.

4 is a circuit diagram illustrating a state after the malfunction protection circuit is turned on according to an embodiment of the present invention.

When the self-turn-on transistor 130 is turned on, the gate terminal and the emitter terminal of the low-side power semiconductor device 100L are short-circuited. Due to this, the displacement signal I _dis branches at the node 1 into a first displacement signal I _dis1 and a second displacement signal I _dis2 .

The first displacement signal I _dis1 is applied to the second signal path, and the second displacement signal I _dis2 is applied to the source of the self-turn-on transistor 130 . Here, the resistance value of the resistor R _off and the forward voltage drop Vf of the resistor D _off may be determined such that the first displacement signal I _dis1 is maintained relatively larger than that of the second displacement signal I _dis2 .

The turn-on resistance R _ON of the self-turn-on transistor 130 may be determined such that the source-drain voltage V _SD by the second displacement signal I _dis2 is maintained to be less than the threshold voltage of the low-side power semiconductor device 100L.

Up to now, the power semiconductor device 110 has been illustrated as an example in the case of an insulated gate bipolar transistor (IGBT), but the technical concept of the present invention can be applied and expanded in the same or similar manner to various types of power semiconductor devices such as power MOSFETs. it is natural to have

Although the above has been described with reference to the embodiments of the present invention, those of ordinary skill in the art can variously modify the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. and may be changed.

100: power semiconductor device including self-turn-on structure
110: power semiconductor device that does not include a self-turn-on structure
120: malfunction turn-on prevention circuit 130: self-turn-on transistor

Claims (8)

a power semiconductor device having a gate terminal connected to the first node and formed on a semiconductor substrate;
a P-type self-turn-on transistor formed on the semiconductor substrate, a source connected to the first node, a gate connected to a second node, and a drain connected to a source terminal or an emitter terminal of the power semiconductor device; and
It is connected to the first node and the second node, transfers a gate-on signal from the second node to the gate terminal of the power semiconductor device, and receives a displacement signal generated when the power semiconductor device is turned off at the gate terminal Including a signal transmission device for transmitting to the second node,
The P-type self-turn-on transistor is
is turned off when the gate-on signal is applied,
When the displacement signal is applied, the power semiconductor device is turned on to short-circuit the gate terminal and the source terminal or the emitter terminal of the power semiconductor device. According to claim 1,
The signal transmission element,
a first resistor and a first diode connected in series to transfer the gate-on signal; and
A power semiconductor device having a built-in malfunction turn-on prevention circuit, comprising a second resistor and a second diode connected in series for transmitting the displacement signal. 3. The method of claim 2,
When the voltage of the second node is greater than the voltage of the first node by the gate-on signal, the P-type self-turn-on transistor is turned off,
When the voltage of the first node becomes greater than the threshold voltage of the P-type self-turn-on transistor by the displacement signal, the P-type self-turn-on transistor is turned on, semiconductor device. According to claim 1,
The P-type self-turn-on transistor is a MOSFET, a power semiconductor device having a built-in malfunction turn-on prevention circuit. 5. The method of claim 4,
The absolute value of the threshold voltage of the P-type self-turn-on transistor is smaller than the threshold voltage of the power semiconductor device, a power semiconductor device having a built-in malfunction turn-on prevention circuit. 5. The method of claim 4,
A source-drain breakdown voltage of the P-type self-turn-on transistor is greater than a gate guarantee voltage of the power semiconductor device, a power semiconductor device having a built-in malfunction turn-on prevention circuit. According to claim 1,
The power semiconductor device is a MOSFET transistor, a power semiconductor device having a built-in malfunction turn-on prevention circuit. According to claim 1,
The power semiconductor device is an insulated gate bipolar transistor, a power semiconductor device with a built-in malfunction turn-on prevention circuit.

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