KR102451950B1 - 융합된 단일 사이클 증가-비교-점프를 수행하기 위한 명령어 및 로직 - Google Patents
융합된 단일 사이클 증가-비교-점프를 수행하기 위한 명령어 및 로직 Download PDFInfo
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- KR102451950B1 KR102451950B1 KR1020177013959A KR20177013959A KR102451950B1 KR 102451950 B1 KR102451950 B1 KR 102451950B1 KR 1020177013959 A KR1020177013959 A KR 1020177013959A KR 20177013959 A KR20177013959 A KR 20177013959A KR 102451950 B1 KR102451950 B1 KR 102451950B1
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
- G06F9/45525—Optimisation or modification within the same instruction set architecture, e.g. HP Dynamo
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/582,053 US20160179542A1 (en) | 2014-12-23 | 2014-12-23 | Instruction and logic to perform a fused single cycle increment-compare-jump |
| US14/582,053 | 2014-12-23 | ||
| PCT/US2015/062098 WO2016105767A1 (en) | 2014-12-23 | 2015-11-23 | Instruction and logic to perform a fused single cycle increment-compare-jump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20170097633A KR20170097633A (ko) | 2017-08-28 |
| KR102451950B1 true KR102451950B1 (ko) | 2022-10-11 |
Family
ID=56129480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020177013959A Active KR102451950B1 (ko) | 2014-12-23 | 2015-11-23 | 융합된 단일 사이클 증가-비교-점프를 수행하기 위한 명령어 및 로직 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20160179542A1 (enExample) |
| EP (1) | EP3238046A4 (enExample) |
| JP (1) | JP6849274B2 (enExample) |
| KR (1) | KR102451950B1 (enExample) |
| CN (1) | CN107077321B (enExample) |
| TW (1) | TWI691897B (enExample) |
| WO (1) | WO2016105767A1 (enExample) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7958181B2 (en) * | 2006-09-21 | 2011-06-07 | Intel Corporation | Method and apparatus for performing logical compare operations |
| US10275217B2 (en) | 2017-03-14 | 2019-04-30 | Samsung Electronics Co., Ltd. | Memory load and arithmetic load unit (ALU) fusing |
| US10360034B2 (en) * | 2017-04-18 | 2019-07-23 | Samsung Electronics Co., Ltd. | System and method for maintaining data in a low-power structure |
| US11150908B2 (en) * | 2017-08-18 | 2021-10-19 | International Business Machines Corporation | Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence |
| US11256509B2 (en) | 2017-12-07 | 2022-02-22 | International Business Machines Corporation | Instruction fusion after register rename |
| US11157280B2 (en) * | 2017-12-07 | 2021-10-26 | International Business Machines Corporation | Dynamic fusion based on operand size |
| US11475951B2 (en) | 2017-12-24 | 2022-10-18 | Micron Technology, Inc. | Material implication operations in memory |
| US10424376B2 (en) | 2017-12-24 | 2019-09-24 | Micron Technology, Inc. | Material implication operations in memory |
| US11194578B2 (en) | 2018-05-23 | 2021-12-07 | International Business Machines Corporation | Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor |
| CN111209044B (zh) * | 2018-11-21 | 2022-11-25 | 展讯通信(上海)有限公司 | 指令压缩方法及装置 |
| US10996952B2 (en) * | 2018-12-10 | 2021-05-04 | SiFive, Inc. | Macro-op fusion |
| US10831496B2 (en) | 2019-02-28 | 2020-11-10 | International Business Machines Corporation | Method to execute successive dependent instructions from an instruction stream in a processor |
| KR20210012335A (ko) | 2019-07-24 | 2021-02-03 | 에스케이하이닉스 주식회사 | 반도체장치 |
| US11216278B2 (en) * | 2019-08-12 | 2022-01-04 | Advanced New Technologies Co., Ltd. | Multi-thread processing |
| US11144324B2 (en) * | 2019-09-27 | 2021-10-12 | Advanced Micro Devices, Inc. | Retire queue compression |
| US12254285B2 (en) | 2020-01-07 | 2025-03-18 | SK Hynix Inc. | Processing-in-memory (PIM) devices |
| US11537323B2 (en) | 2020-01-07 | 2022-12-27 | SK Hynix Inc. | Processing-in-memory (PIM) device |
| US12248762B2 (en) | 2020-01-07 | 2025-03-11 | SK Hynix Inc. | Processing-in-memory (PIM) devices |
| US11422803B2 (en) | 2020-01-07 | 2022-08-23 | SK Hynix Inc. | Processing-in-memory (PIM) device |
| US12405799B2 (en) * | 2020-11-19 | 2025-09-02 | Arm Limited | Register rename stage fusing of instructions |
| US12008369B1 (en) * | 2021-08-31 | 2024-06-11 | Apple Inc. | Load instruction fusion |
| TW202411838A (zh) * | 2022-07-12 | 2024-03-16 | 美商賽發馥股份有限公司 | 與破壞性指令融合 |
| US12288066B1 (en) | 2022-09-23 | 2025-04-29 | Apple Inc. | Operation fusion for instructions bridging execution unit types |
| US12217060B1 (en) | 2022-09-23 | 2025-02-04 | Apple Inc. | Instruction fusion |
| US12487829B2 (en) | 2023-02-03 | 2025-12-02 | SiFive, Inc. | Macro-op fusion for pipelined architectures |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020087955A1 (en) * | 2000-12-29 | 2002-07-04 | Ronny Ronen | System and Method for fusing instructions |
| US20060224863A1 (en) * | 2005-03-30 | 2006-10-05 | Lovett William O | Preparing instruction groups for a processor having multiple issue ports |
| US20100312991A1 (en) | 2008-05-08 | 2010-12-09 | Mips Technologies, Inc. | Microprocessor with Compact Instruction Set Architecture |
| US20110264897A1 (en) * | 2010-04-27 | 2011-10-27 | Via Technologies, Inc. | Microprocessor that fuses load-alu-store and jcc macroinstructions |
| US20140281397A1 (en) | 2013-03-15 | 2014-09-18 | Maxim Loktyukhin | Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1254661A (en) * | 1985-06-28 | 1989-05-23 | Allen J. Baum | Method and means for instruction combination for code compression |
| US5051940A (en) * | 1990-04-04 | 1991-09-24 | International Business Machines Corporation | Data dependency collapsing hardware apparatus |
| JPH09265400A (ja) * | 1996-03-28 | 1997-10-07 | Hitachi Ltd | コンパイル最適化方式 |
| US5717910A (en) * | 1996-03-29 | 1998-02-10 | Integrated Device Technology, Inc. | Operand compare/release apparatus and method for microinstrution sequences in a pipeline processor |
| JPH09288564A (ja) * | 1996-06-17 | 1997-11-04 | Takeshi Sakamura | データ処理装置 |
| US6857063B2 (en) * | 2001-02-09 | 2005-02-15 | Freescale Semiconductor, Inc. | Data processor and method of operation |
| US6931517B1 (en) * | 2001-10-23 | 2005-08-16 | Ip-First, Llc | Pop-compare micro instruction for repeat string operations |
| US7051190B2 (en) * | 2002-06-25 | 2006-05-23 | Intel Corporation | Intra-instruction fusion |
| US7451294B2 (en) * | 2003-07-30 | 2008-11-11 | Intel Corporation | Apparatus and method for two micro-operation flow using source override |
| GB2414308B (en) * | 2004-05-17 | 2007-08-15 | Advanced Risc Mach Ltd | Program instruction compression |
| US8082430B2 (en) * | 2005-08-09 | 2011-12-20 | Intel Corporation | Representing a plurality of instructions with a fewer number of micro-operations |
| US7797517B1 (en) * | 2005-11-18 | 2010-09-14 | Oracle America, Inc. | Trace optimization via fusing operations of a target architecture operation set |
| US7596681B2 (en) * | 2006-03-24 | 2009-09-29 | Cirrus Logic, Inc. | Processor and processing method for reusing arbitrary sections of program code |
| US7958181B2 (en) * | 2006-09-21 | 2011-06-07 | Intel Corporation | Method and apparatus for performing logical compare operations |
| US9690591B2 (en) * | 2008-10-30 | 2017-06-27 | Intel Corporation | System and method for fusing instructions queued during a time window defined by a delay counter |
| US8850164B2 (en) * | 2010-04-27 | 2014-09-30 | Via Technologies, Inc. | Microprocessor that fuses MOV/ALU/JCC instructions |
| CN102163139B (zh) * | 2010-04-27 | 2014-04-02 | 威盛电子股份有限公司 | 微处理器融合载入算术/逻辑运算及跳跃宏指令 |
| US9886277B2 (en) * | 2013-03-15 | 2018-02-06 | Intel Corporation | Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources |
-
2014
- 2014-12-23 US US14/582,053 patent/US20160179542A1/en not_active Abandoned
-
2015
- 2015-11-23 WO PCT/US2015/062098 patent/WO2016105767A1/en not_active Ceased
- 2015-11-23 CN CN201580063903.7A patent/CN107077321B/zh not_active Expired - Fee Related
- 2015-11-23 JP JP2017527588A patent/JP6849274B2/ja not_active Expired - Fee Related
- 2015-11-23 EP EP15873974.8A patent/EP3238046A4/en not_active Withdrawn
- 2015-11-23 TW TW104138808A patent/TWI691897B/zh not_active IP Right Cessation
- 2015-11-23 KR KR1020177013959A patent/KR102451950B1/ko active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020087955A1 (en) * | 2000-12-29 | 2002-07-04 | Ronny Ronen | System and Method for fusing instructions |
| US20060224863A1 (en) * | 2005-03-30 | 2006-10-05 | Lovett William O | Preparing instruction groups for a processor having multiple issue ports |
| US20100312991A1 (en) | 2008-05-08 | 2010-12-09 | Mips Technologies, Inc. | Microprocessor with Compact Instruction Set Architecture |
| US20110264897A1 (en) * | 2010-04-27 | 2011-10-27 | Via Technologies, Inc. | Microprocessor that fuses load-alu-store and jcc macroinstructions |
| US20140281397A1 (en) | 2013-03-15 | 2014-09-18 | Maxim Loktyukhin | Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources |
Also Published As
| Publication number | Publication date |
|---|---|
| US20160179542A1 (en) | 2016-06-23 |
| EP3238046A4 (en) | 2018-07-18 |
| CN107077321A (zh) | 2017-08-18 |
| WO2016105767A1 (en) | 2016-06-30 |
| JP6849274B2 (ja) | 2021-03-24 |
| KR20170097633A (ko) | 2017-08-28 |
| TW201643706A (zh) | 2016-12-16 |
| JP2018500657A (ja) | 2018-01-11 |
| CN107077321B (zh) | 2021-08-17 |
| TWI691897B (zh) | 2020-04-21 |
| EP3238046A1 (en) | 2017-11-01 |
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