KR102442809B1 - Lock-in amplifier, integrated circuit and portable measurement device including the same - Google Patents

Abstract

The lock-in amplifier includes a clock signal generating unit and a detecting unit. The clock signal generator generates a first demodulated clock signal and a second demodulated clock signal having a phase difference of 90 degrees and having the same demodulation frequency. The detection unit provides an offset voltage corresponding to an offset of an internal circuit in a first operation mode, based on an input signal, the first demodulated clock signal, and the second demodulated clock signal, and demodulates the input signal in a second operation mode A first output voltage and a second output voltage corresponding to the magnitude of the frequency component are provided. The lock-in amplifier can be implemented with a simplified configuration and a reduced size by eliminating the phase adjustment circuit and the feedback circuit for the conventional phase lock-in, and extracting the offset voltage representing the offset of the internal circuit of the demodulation frequency component of the input signal. You can provide the exact size.

Description

Lock-in amplifier, integrated circuit and portable measurement device including the same

The present invention relates to a semiconductor integrated circuit, and more particularly, to a lock-in amplifier, an integrated circuit including the same, and a portable measurement device.

For AC signals with very small amplitudes, amplification is required for measurement. Even if the small signal of alternating current is amplified, the noise level also increases. Therefore, noise filtering is usually accompanied with amplification. A band pass filter (BPF) may be used to detect a specific frequency component. In this case, since the noise also exists in the pass band, the minute signal is still buried in the noise. In addition, it is virtually impossible to design a bandpass filter with a sufficiently narrow passband.

SUMMARY OF THE INVENTION One object of the present invention to solve the above problems is to provide a lock-in amplifier capable of efficiently and accurately detecting the magnitude of a demodulation frequency component of a minute signal.

It is also an object of the present invention to provide an integrated circuit including the lock-in amplifier and a portable measuring device.

In order to achieve the above object, a lock-in amplifier according to embodiments of the present invention includes a clock signal generator and a detector. The clock signal generator generates a first demodulated clock signal and a second demodulated clock signal having a phase difference of 90 degrees and having the same demodulation frequency. The detection unit provides an offset voltage corresponding to an offset of an internal circuit in a first operation mode, based on an input signal, the first demodulated clock signal, and the second demodulated clock signal, and demodulates the input signal in a second operation mode A first output voltage and a second output voltage corresponding to the magnitude of the frequency component are provided.

In an embodiment, the detector may sequentially generate the offset voltage, the first output voltage, and the second output voltage for each operation mode using a single mixer.

In an embodiment, the magnitude of the demodulation frequency component of the input signal may be determined by the following equation.

Vo=[(VOX-VOS) ² +(VOY-VOS) ² ] ^1/2

where Vo is the output of the lock-in amplifier corresponding to the magnitude of the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage, and VOS is the offset voltage.

In an embodiment, the detector sequentially generates a first offset voltage and the first output voltage for each operation mode using a first mixer, and uses a second mixer to generate a second offset voltage and the second output voltage may occur sequentially.

In an embodiment, the magnitude of the demodulation frequency component of the input signal may be determined by the following equation.

Vo=[(VOX-VOSX) ² +(VOY-VOSY) ² ] ^1/2

where Vo is the output of the lock-in amplifier corresponding to the magnitude of the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage, VOSX is the first offset voltage, and VOSY is the second offset voltage.

In an embodiment, the detection unit comprises: an amplifying unit amplifying the input signal to output an amplified signal in the second operation mode; multiplying the amplified signal by the first demodulated clock signal in the second operation mode A mixer unit that generates a rectified signal and multiplies the amplified signal with the second demodulated clock signal to generate a second rectified signal, and filters the first rectified signal in the second operation mode to generate the first output voltage and a filter unit configured to generate the second output voltage by filtering the second rectified signal.

In an embodiment, the mixer unit comprises: a first input terminal for receiving the amplified signal, a second input terminal for sequentially receiving the first demodulated clock signal and the second demodulated clock signal in the second operation mode; and a mixer having an output terminal for sequentially outputting the first rectified signal and the second rectified signal in the second operation mode.

In an embodiment, the filter unit may include a low-pass filter connected to the output terminal of the mixer to sequentially generate the first output voltage and the second output voltage in the second operation mode.

In an embodiment, the lock-in amplifier may further include a clock selector that selects one of the first demodulated clock signal and the second demodulated clock signal and provides it to the second input terminal of the mixer.

In an embodiment, the mixer unit includes a first input terminal for receiving the amplified signal, a second input terminal for receiving the first demodulated clock signal, and a first output terminal for outputting the first rectified signal. a second mixer having a first mixer and a third input terminal receiving the amplified signal, a fourth input terminal receiving the second demodulated clock signal, and a second output terminal outputting the second rectified signal .

In one embodiment, the filter unit is connected to the first output terminal of the first mixer to generate a first offset voltage in the first operation mode and generate the first output voltage in the second operation mode a first low pass filter and a second low pass connected to the second output terminal of the second mixer to generate a second offset voltage in the first mode of operation and to generate the second output voltage in the second mode of operation Filters may be included.

In an embodiment, the detection unit may further include an input unit configured to block the input signal applied to the amplifier unit in the first operation mode in response to a mode signal.

In an embodiment, the filter unit may generate the offset voltage while the mode signal is activated and the input signal applied to the amplifier is blocked by the input unit.

In an embodiment, the clock signal generator may include a plurality of flip-flops that generate the first demodulated clock signal and the second demodulated clock signal based on a reference clock signal having a frequency that is an integer multiple of the demodulation frequency. can

In an embodiment, the clock signal generator receives a reference clock signal through a clock terminal, a data terminal is connected to an inverted output terminal, and generates a first clock signal through a non-inverted output terminal, and to the inverted output terminal a first flip-flop generating a second clock signal, receiving the first clock signal through a clock terminal, a data terminal coupled to an inverting output terminal, and a second generating the first demodulated clock signal through a non-inverting output terminal and a flip-flop and a third flip-flop receiving the second clock signal through a clock terminal, a data terminal connected to an inverting output terminal, and generating the second demodulated clock signal through a non-inverting output terminal.

In an embodiment, the frequency of the reference clock signal may be four times the demodulation frequency.

In an embodiment, the clock signal generator includes: a first flip-flop that receives a reference clock signal through a clock terminal, a data terminal is connected to an inverted output terminal, and generates the first demodulated clock signal through a non-inverted output terminal and a second flip-flop that receives an inverted signal of the reference clock signal through a clock terminal, a data terminal is connected to an inverted output terminal, and generates the second demodulated clock signal through a non-inverted output terminal.

In an embodiment, the frequency of the reference clock signal may be twice the demodulation frequency.

In order to achieve the above object, an integrated circuit according to embodiments of the present invention includes a clock signal generator, a detector, an analog-to-digital converter, and a controller. The clock signal generator generates a first demodulated clock signal and a second demodulated clock signal having a phase difference of 90 degrees and having the same demodulation frequency. The detection unit provides an offset voltage corresponding to an offset of an internal circuit in a first operation mode, based on an input signal, the first demodulated clock signal, and the second demodulated clock signal, and demodulates the input signal in a second operation mode A first output voltage and a second output voltage corresponding to the magnitude of the frequency component are provided. The analog-to-digital converter converts the offset voltage, the first output voltage, and the second output voltage into digital values, respectively. The controller controls the clock signal generator, the detector, and the analog-to-digital converter, and calculates the magnitude of the demodulation frequency component of the input signal based on the digital values.

In an embodiment, the detection unit sequentially generates the offset voltage, the first output voltage, and the second output voltage for each operation mode using a single mixer, and the control unit is configured by the following equation The magnitude of the demodulation frequency component of the input signal may be calculated.

Vo=[(VOX-VOS) ² +(VOY-VOS) ² ] ^1/2

where Vo is the output of the lock-in amplifier corresponding to the magnitude of the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage, and VOS is the offset voltage.

In an embodiment, the detector sequentially generates a first offset voltage and the first output voltage for each operation mode using a first mixer, and uses a second mixer to generate a second offset voltage and the second output voltage occurs sequentially,

The controller may calculate the magnitude of the demodulation frequency component of the input signal by the following equation.

Vo=[(VOX-VOSX) ² +(VOY-VOSY) ² ] ^1/2

where Vo is the output of the lock-in amplifier corresponding to the magnitude of the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage, VOSX is the first offset voltage, and VOSY is the second offset voltage.

In order to achieve the above object, a portable measuring device according to embodiments of the present invention senses a signal generated by a modulator generating a modulated signal based on a modulated clock signal, and a signal generated by a mutual reaction between the modulated signal and an object under test. A sensor for generating an input signal, a clock signal generator generating a first demodulated clock signal and a second demodulated clock signal having a phase difference of 90 degrees and having the same demodulation frequency, an input signal, the first demodulated clock signal and the second demodulated clock signal Based on the clock signal, providing an offset voltage corresponding to the offset of the internal circuit in a first operation mode and generating a first output voltage and a second output voltage corresponding to the magnitude of a demodulation frequency component of the input signal in a second operation mode A detection unit that provides, an analog-to-digital converter that converts the offset voltage, the first output voltage, and the second output voltage into digital values, respectively, and controls the clock signal generator, the detection unit, and the analog-to-digital converter, and controls the digital and a controller configured to calculate a magnitude of the demodulation frequency component of the input signal based on the values.

In an embodiment, the clock signal generator may include a plurality of flip-flops that generate the first demodulated clock signal and the second demodulated clock signal based on a reference clock signal having a frequency that is an integer multiple of the demodulation frequency. can

In an embodiment, at least one of the first demodulated clock signal and the second demodulated clock signal may be provided to the modulator as the modulated clock signal.

A lock-in amplifier according to embodiments of the present invention, an integrated circuit including the same, and a portable measurement device include two orthogonal components (In) using two demodulated clock signals having a phase difference of 90 degrees regardless of the phase of an input signal. - By detecting the phase component and quadrature component) and using it to calculate the magnitude of the demodulation frequency component of the input signal, the phase adjustment circuit and the feedback circuit for the conventional phase lock-in are eliminated, and can be implemented with a simplified configuration and reduced size. have. In addition, the lock-in amplifier according to embodiments of the present invention provides demodulated clock signals having a phase difference of 90 degrees using a plurality of flip-flops, so that the size and power consumption can be further reduced, and can be efficiently used in portable devices. have.

A lock-in amplifier, an integrated circuit including the same, and a portable measurement device according to embodiments of the present invention may extract an offset voltage representing an offset of an internal circuit of the lock-in amplifier to accurately provide the magnitude of a demodulation frequency component of an input signal .

A lock-in amplifier, an integrated circuit including the same, and a portable measurement device according to embodiments of the present invention sequentially generate a first output voltage and a second output voltage for each operation mode using a single signal channel including one mixer By doing so, it is possible to prevent mismatch between the conventional channels and accurately provide the magnitude of the demodulation frequency component of the input signal.

1 is a block diagram illustrating a lock-in amplifier according to embodiments of the present invention.
FIG. 2 is a block diagram illustrating an embodiment of a detection unit included in the lock-in amplifier of FIG. 1 .
3 is a circuit diagram illustrating an embodiment of an input unit included in the detection unit of FIG. 2 .
4 is a circuit diagram illustrating an embodiment of an amplifying unit included in the detection unit of FIG. 2 .
5 is a diagram illustrating an example of a common mode voltage generator.
6 is a diagram illustrating an embodiment of a mixer unit and a filter unit included in the detection unit of FIG. 2 .
7 is a circuit diagram illustrating an embodiment of a mixer included in the mixer unit of FIG. 6 .
8 is a timing diagram illustrating an operation of a non-overlapping clock signal generator included in the mixer of FIG. 7 .
9 is a timing diagram illustrating an operation of the lock-in detector including the mixer unit and the filter unit of FIG. 6 .
10 is a waveform diagram illustrating an example of a rectified signal output from a mixer.
11 is a diagram illustrating an embodiment of a mixer unit and a filter unit included in the detection unit of FIG. 2 .
12 is a timing diagram illustrating an operation of the lock-in detector including the mixer unit and the filter unit of FIG. 11 .
13 and 14 are diagrams illustrating embodiments of a clock signal generator included in the lock-in amplifier of FIG. 1 .
15 is a timing diagram illustrating an operation of the clock signal generator of FIGS. 13 and 14 .
16 is a diagram illustrating an embodiment of a clock signal generator included in the lock-in amplifier of FIG. 1 .
17 is a timing diagram illustrating an operation of the clock signal generator of FIG. 16 .
18 is a circuit diagram illustrating an embodiment of a flip-flop included in a clock signal generator.
19 is a block diagram illustrating an integrated circuit including a lock-in amplifier according to embodiments of the present invention.
20 is a flowchart illustrating a signal measuring method according to embodiments of the present invention.
21 is a block diagram illustrating a portable measurement device including a lock-in amplifier according to embodiments of the present invention.
22 is a block diagram illustrating a computing system including a measurement device according to an embodiment of the present invention.
23 is a block diagram illustrating an example of an interface used in the computing system of FIG. 22 .

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms. It should not be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, and is intended to indicate that one or more other features or numbers are present. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with the context of the related art, and unless explicitly defined in the present application, they are not to be interpreted in an ideal or excessively formal meaning. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 is a block diagram illustrating a lock-in amplifier according to embodiments of the present invention.

Referring to FIG. 1 , a lock-in amplifier 10 includes a detector (DET) 20 and a clock signal generator (CKGEN) 30 .

The clock signal generator 30 generates a first demodulated clock signal CKX and a second demodulated clock signal CKY having a phase difference of 90 degrees and having the same demodulation frequency. In an embodiment, the clock signal generator 30 may generate a first demodulated clock signal CKX and a second demodulated clock signal CKY using a plurality of flip-flops. Embodiments of the clock signal generator 30 will be described later with reference to FIGS. 13 to 18 .

The detector 20 generates an output signal SO based on the input signal SI, the first demodulated clock signal CKX, and the second demodulated clock signal CKY. The detector 20 may provide the offset voltage VOS, the first output voltage VOX, and the second output voltage VOY through the output signal SO. The detector 20 provides an offset voltage VOS corresponding to the offset of the internal circuit in the first operation mode OM1 and corresponds to the magnitude of the demodulation frequency component of the input signal SI in the second operation mode OM2. A first output voltage VOX and a second output voltage VOY may be provided.

In an embodiment, as will be described later with reference to FIGS. 6 and 9 , the detection unit 20 uses a single signal channel including one mixer to generate an offset voltage VOS, a first output voltage VOX, and a second output voltage VOX. Two output voltages VOY may be sequentially provided. In another embodiment, as will be described later with reference to FIGS. 11 and 12 , the detection unit 20 uses a first signal channel including a first mixer to obtain a first offset voltage VOSX and a first output voltage VOX. ) may be sequentially provided, and the second offset voltage VOSY and the second output voltage VOY may be sequentially provided using the second signal channel including the second mixer.

A conventional lock-in amplifier includes a sophisticated tunable phase shifting circuit and a feedback circuit for phase lock-in with the demodulation frequency component of the input signal SI, and these circuits are complicated by the complexity of hardware and the lock-in amplifier. increase the size. In addition, since the conventional lock-in amplifier requires trimming for each lock-in amplifier according to variations in the provision process, variations in operating conditions, and the like, test time and cost increase. The lock-in amplifier according to embodiments of the present invention detects two orthogonal components (in-phase component and quadrature component) using two demodulated clock signals having a phase difference of 90 degrees irrespective of the phase of the input signal. By calculating the magnitude of the demodulation frequency component of the input signal by using it, the phase adjustment circuit and the feedback circuit for the conventional phase lock-in can be eliminated and implemented with a simplified configuration and a reduced size. In addition, the lock-in amplifier according to embodiments of the present invention provides demodulated clock signals having a phase difference of 90 degrees using a plurality of flip-flops, so that the size and power consumption can be further reduced, and can be efficiently used in portable devices. have. Furthermore, the lock-in amplifier according to embodiments of the present invention can accurately provide the magnitude of the demodulation frequency component of the input signal by extracting the offset voltage representing the offset of the internal circuit.

FIG. 2 is a block diagram illustrating an embodiment of a detection unit included in the lock-in amplifier of FIG. 1 .

Referring to FIG. 2 , the detection unit 20 may include an input unit 100 , an amplifier (AMP) 200 , a mixer unit (MX) 300 , and a filter unit (FLT) 400 .

The input unit 100 may block the input signal SI applied to the amplifier 200 in the first operation mode OM1 in response to the mode signal MD. The input unit 100 is a switch that is opened when the mode signal MD is a first logic level (eg, a logic low level) and closed when it is a second logic level (eg, a logic high level) (SW) may be included. When the mode signal MD is at the first logic level, it may correspond to the first operation mode OM1 and may correspond to the second operation mode OM2 when it is at the second logic level. In the first operation mode OM1 , the input signal SI may be blocked and the detector 20 may provide the offset voltage VOS through the output signal SO. In the second operation mode OM2 , the input signal SI may be transmitted, and the detector 20 may provide the first output voltage VOX and the second output voltage VOY through the output signal S0 . In FIG. 2 , the input unit 100 is shown as a separate component and disposed at the front end of the amplifying unit 200 , but the input unit 100 may be included in the amplifying unit 200 .

The amplifier 200 amplifies the input signal SI in the second operation mode OM2 and outputs the amplified signal SA. The gain and configuration of the amplifier 200 may be variously implemented according to the lock-in amplifier 10 .

The mixer unit 300 multiplies the amplified signal SA by the first demodulated clock signal CKX in the second operation mode OM2 to generate a first rectified signal SRX and performs a second demodulation of the amplified signal SA. A second rectified signal SRY is generated by multiplying the clock signal CKY. The filter unit 400 may filter the first rectified signal SRX to generate a first output voltage VOX, and filter the second rectified signal SRY to generate a second output voltage VOY. In an embodiment, as will be described later with reference to FIGS. 6 and 9 , the mixer unit 300 uses a single mixer in the second operation mode OM2 for the first rectified signal SRX and the second rectified signal. SRY may be sequentially provided, and the filter unit 400 may sequentially provide the first output voltage VOX and the second output voltage VOY using one low-pass filter. In another embodiment, as will be described later with reference to FIGS. 11 and 12 , the mixer unit 300 uses two mixers in the second operation mode OM2 to obtain a first rectified signal SRX and a second rectified signal. SRY is provided, and the filter unit 400 may provide the first output voltage VOX and the second output voltage VOY using two low-pass filters, respectively.

3 is a circuit diagram illustrating an embodiment of an input unit included in the detection unit of FIG. 2 .

Referring to FIG. 3 , the input unit 100 includes a capacitor Cd and a transistor TN connected between a first node N1 to which an input signal SI is applied and a second node corresponding to the input of the amplifier 200 . ) may be included.

The capacitor Cd may function to transmit only the AC component of the input signal SI to the rear end and block the DC component. The transistor TN may function as a switch turned on in response to the mode signal MD. For example, the transistor TN may be implemented as an NMOS transistor. In this case, when the mode signal MD is at a logic low level, the transistor TN is turned off to indicate the first operation mode OM1 , and when the mode signal MD is at a logic high level, the transistor TN is turned off. It may be turned on to indicate the second operation mode OM2 .

4 is a circuit diagram illustrating an embodiment of an amplifier included in the detection unit of FIG. 2 , and FIG. 5 is a diagram illustrating an example of a common mode voltage generator.

Referring to FIG. 4 , the amplifier 200 may include one or more operational amplifiers 210 and 220 connected between the second node N2 and the third node N3 . The operational amplifiers 210 and 220 may be implemented as a low noise amplifier (LNA). Input resistors R1 and R3 may be respectively connected to negative terminals (−) of the operational amplifiers 210 and 220 , and a common mode voltage VCM may be applied to positive terminals (+). Each of the capacitors C1 and C2 and each of the feedback resistors R2 and R4 may be connected in parallel on the feedback path of the operational amplifiers 210 and 220 . A portion of the feedback resistor R4 may be implemented as a variable resistor, and the gain of the amplifier 200 may be adjusted by adjusting the resistance value of the variable resistor R4 . 4 illustrates an example in which the amplifying unit 200 is implemented in two stages, the configuration and the number of stages of the amplifying unit 200 may be variously changed.

Referring to FIG. 5 , the common mode voltage generator 230 may include division resistors Ru and Rd, a capacitor Cg, and an operational amplifier 232 . The operational amplifier 230 may be implemented as a low noise amplifier (LNA). The distribution resistors Ru and Rd may be connected in series between the power supply voltage VDD and the ground. A negative terminal (−) of the operational amplifier 232 may be connected to an output generating a common mode voltage VCM, and a positive terminal (+) may be connected to a node between the distribution resistors Ru and Rd. The capacitor Cg may be connected between the positive terminal (+) of the operational amplifier 232 and the ground.

The operational amplifier 232 may operate as a unity-gain amplifier and may provide a voltage divided by the division resistors Ru and Rd as a common mode voltage VCM. For example, resistance values of the distribution resistors Ru and Rd are the same, and in this case, the common mode voltage VCM may correspond to a half (VDD/2) of the power supply voltage VDD.

6 is a diagram illustrating an embodiment of a mixer unit and a filter unit included in the detection unit of FIG. 2 .

6 shows the structure of a single signal channel according to an embodiment of the present invention. Referring to FIG. 6 , the mixer unit 310 may include one mixer 320 and a clock selector (MUX) 330 , and the filter unit 410 includes one low pass filter (LPF). filter) may be included.

The mixer 320 includes a first input terminal for receiving the amplified signal SA provided from the amplifier 200 , and a first demodulated clock signal CKX and a second demodulated clock signal CKY in a second operation mode OM2 . ) and an output terminal sequentially outputting the first rectified signal SRX and the second rectified signal SRY in the second operation mode OM2. That is, the first rectified signal SRX and the second rectified signal SRY may correspond to one rectified signal SR provided for each operation mode through one output terminal.

The clock selector 330 selects one of the first demodulated clock signal CKX and the second demodulated clock signal CKY in response to the clock select signal SEL and selects it to the second input terminal of the mixer 320 . It may be provided as the clock signal CKS. Although the clock selector 330 is illustrated as being included in the mixer unit 310 in FIG. 6 , the clock selector 330 may be included in the clock signal generator 30 of FIG. 1 according to an exemplary embodiment.

The low-pass filter 410 is connected to the output terminal of the mixer 320 to generate the offset voltage VOS in the first operation mode OM1, and the first output voltage VOX and The second output voltage VOY is sequentially generated. That is, the low-pass filter 410 may sequentially provide the offset voltage VOS, the first output voltage VOX, and the second output voltage VOY for each operation mode through one output signal SO. As described above, in the first operation mode OM1 in which the input signal SI is blocked, the low-pass filter 410 generates the offset voltage VOS. For example, the low-pass filter 410 may include one or more RC filters. The operation of the lock-in amplifier adopting the structure of the single signal channel of FIG. 6 will be described later with reference to FIG. 9 .

7 is a circuit diagram illustrating an embodiment of a mixer included in the mixer unit of FIG. 6 , and FIG. 8 is a timing diagram illustrating an operation of a non-overlapping clock signal generator included in the mixer of FIG. 7 .

Referring to FIG. 7 , the mixer 320 may include a non-overlapping clock signal generator (NOCG) 322 , an operational amplifier 324 , resistors R1 and R2 , and switches SW1 and SW2 . . The first resistor R1 is connected to the negative terminal (-) of the operational amplifier 324 and the second resistor R2 is the output terminal of the operational amplifier 324 for generating the rectified signal SR and the negative terminal (-) It can be placed on the return path between The first switch SW1 may apply the amplified signal SA to the positive terminal (+) of the operational amplifier 324 in response to the first clock signal Q1 from the non-overlapping clock signal generator 322 . . The second switch SW2 may apply the common mode voltage VCM to the positive terminal (+) of the operational amplifier 324 in response to the second clock signal Q2 from the non-overlapping clock signal generator 322 . have. For example, the first resistor R1 and the second resistor R2 may have the same resistance value.

The non-overlapping clock signal generator 322 is a first clock signal Q1 and a second clock signal Q2 that are complementarily activated based on the selection clock signal CKS provided from the clock selection unit 330 of FIG. 6 . ) can occur. As shown in FIG. 8 , the non-overlapping clock signal generating unit 322 is configured after a predetermined delay time td after one of the first clock signal Q1 and the second clock signal Q2 is deactivated to a logic low level. The timing can be adjusted so that the other can be activated to a logic high level. That is, the non-overlapping clock signal generator 322 may adjust the timing so that the activation periods of the first clock signal Q1 and the second clock signal CK2 do not overlap each other. Using the non-overlapping first clock signal Q1 and the second clock signal Q2 as described above, the amplified signal SA and the common mode voltage VCM are simultaneously applied to the positive terminal (+) of the operational amplifier 324 . can be prevented from being applied.

9 is a timing diagram illustrating an operation of the lock-in detector including the mixer unit and the filter unit of FIG. 6 .

In FIG. 9 , time sections t1 to t2 correspond to the first operation mode OM1 , and time sections t2 to t4 correspond to the second operation mode OM2 .

1, 2, 6, and 9, the detector 20 uses one mixer 320 as described above for the offset voltage VOS, the first output voltage VOX, and the second output for each operation mode. The voltage VOY may be sequentially generated. The clock signal generator 30 generates a first demodulated clock signal CKX and a second demodulated clock signal CKY having a phase difference of 90 degrees and having the same demodulation frequency.

During the time period t1 to t2, the mode signal MD indicates the first operation mode OM1 as a logic low level, and the input unit 100 responds to the mode signal MD indicating the first operation mode OM1. Block (SI). The clock selector 330 selects the first demodulated clock signal CKX in response to the logic low level of the clock select signal SEL and provides it as the select clock signal CKS. For convenience, an example in which the first demodulated clock signal CKX is selected in the first operation mode OM1 is illustrated, but in the first operation mode OM1 , the second demodulated clock signal CKY is used as the selection clock signal CKS. It is free to provide In a state in which the input signal SI is blocked, the output signal SO provided from the low-pass filter 410 represents the offset voltage VOS of the internal circuit of the lock-in amplifier 10 .

During the time period t2 to t3, the mode signal MD indicates the second operation mode OM2 as a logic high level, and the input unit 100 responds to the mode signal MD indicating the second operation mode OM2. (SI) is transmitted to the amplification unit 200 . The clock selector 330 selects the first demodulated clock signal CKX in response to the logic low level of the clock select signal SEL and provides it as the select clock signal CKS. In this case, the output signal SO provided from the low-pass filter 410 represents the first output voltage VOX.

The demodulation frequency component of the input signal Si may be expressed as Vi*sin(wt), and the first demodulated clock signal CKX may be expressed as Vd*sin(wt+θ). In this case, the first rectified signal SRX generated from the mixer 320 during the time period t2 to t3 may be expressed as Equation (1).

In Equation 1, Ga represents the gain of the amplifier 200, θ represents the phase difference between the demodulation frequency component of the input signal Si and the first demodulated clock signal SKX, and w represents an angle corresponding to the demodulation frequency Indicates the angular frequency. The time-dependent component of the first rectified signal SRX is removed by the low-pass filter 410 , and as a result, the first output voltage VOX may be expressed as Equation (2).

During the time period t3 to t4, the mode signal MD indicates the second operation mode OM2 as a logic high level, and the input unit 100 responds to the mode signal MD indicating the second operation mode OM2. (SI) is transmitted to the amplification unit 200 . The clock selector 330 selects the second demodulated clock signal CKY in response to the logic high level of the clock select signal SEL and provides it as the select clock signal CKS. In this case, the output signal SO provided from the low-pass filter 410 represents the second output voltage VOY.

Since the second demodulated clock signal CKY has a phase difference of 90 degrees from the first demodulated clock signal CKX, it can be expressed as Vd*cos(wt+θ). In this case, the second rectified signal SRY generated from the mixer 320 during the time period t3 to t4 may be expressed as Equation (3).

The time-dependent component of the second rectified signal SRY is removed by the low-pass filter 410 , and as a result, the second output voltage VOY may be expressed as Equation (4).

The magnitude Vo of the demodulation frequency component of the input signal Si can be obtained from Equations 2 and 4, and the result is as Equation 5.

As described above, the lock-in amplifier according to embodiments of the present invention sequentially applies the first output voltage VOX and the second output voltage VOY for each operation mode using a single signal channel including one mixer 320 . , it is possible to prevent mismatch between the conventional channels and accurately provide the magnitude Vo of the demodulation frequency component of the input signal SI.

10 is a waveform diagram illustrating an example of a rectified signal output from a mixer.

Referring to FIG. 10 , in the first operation mode OM1 , the rectified signal SR substantially corresponds to a DC voltage, and its effective voltage corresponds to the offset voltage VOS. In the first operation mode OM1 , the selection clock signal CKS may be any of the first demodulated clock signal CKX and the second demodulated clock signal CKY.

In the second operation mode OM2 , the first demodulated clock signal CKX and the second demodulated clock signal CKY are sequentially selected as the selection clock signal CKS. When the first demodulated clock signal CKX is selected as the selection clock signal CKS, the rectified signal SR corresponds to the first rectified signal SRX, and the second demodulated clock signal CKY is selected as the selection clock signal CKS. CKS), the rectified signal SR corresponds to the second rectified signal SRY. Since the first demodulated clock signal CKX and the second demodulated clock signal CKY have a phase difference of 90 degrees from each other, the waveforms of the first rectified signal SRX and the second rectified signal SRY are different from each other. The effective voltage of the first rectified signal SR1 corresponds to the first output voltage VOX, and the effective voltage of the second rectified signal SR2 corresponds to the second output voltage VOY.

11 is a diagram illustrating an embodiment of a mixer unit and a filter unit included in the detection unit of FIG. 2 .

11 shows the structure of a double signal channel according to an embodiment of the present invention. Referring to FIG. 11 , the mixer unit 350 may include a first mixer 360 and a second mixer 370 , and the filter unit 450 includes a first low pass filter (LPF) ( 460) and a second low-pass filter 470 .

The first mixer 360 has a first input terminal for receiving the amplified signal SA, a second input terminal for receiving the first demodulated clock signal CKX, and a first output terminal for outputting the first rectified signal SRX. has The second mixer 370 includes a third input terminal receiving the amplified signal SA, a fourth input terminal receiving the second demodulated clock signal CKY, and a second output terminal outputting the second rectified signal SRY. has

The first low-pass filter 460 is connected to the first output terminal of the first mixer 360 to generate the first offset voltage VOSX in the first operation mode OM1 and in the second operation mode OM2. A first output voltage VOX is generated. That is, the first low-pass filter 460 may sequentially provide the first offset voltage VOSX and the first output voltage VOX for each operation mode through the first output signal SOX. The second low-pass filter 470 is connected to the second output terminal of the second mixer 370 to generate a second offset voltage VOSY in the first operation mode OM1 and in the second operation mode OM2. A second output voltage VOY is generated. That is, the second low-pass filter 470 may sequentially provide the second offset voltage VOSY and the second output voltage VOY for each operation mode through the second output signal SOY.

12 is a timing diagram illustrating an operation of the lock-in detector including the mixer unit and the filter unit of FIG. 11 .

In FIG. 12 , time sections t1 to t2 correspond to the first operation mode OM1 , and time sections t2 to t3 correspond to the second operation mode OM2 .

1, 2, 11 and 12 , the detector 20 sequentially generates a first offset voltage VOSX and a first output voltage VOX for each operation mode using the first mixer 360 as described above. , and the second offset voltage VOSY and the second output voltage VOY may be sequentially generated for each operation mode using the second mixer 370 . The clock signal generator 30 generates a first demodulated clock signal CKX and a second demodulated clock signal CKY having a phase difference of 90 degrees and having the same demodulation frequency.

During the time period t1 to t2, the mode signal MD indicates the first operation mode OM1 as a logic low level, and the input unit 100 responds to the mode signal MD indicating the first operation mode OM1. Block (SI). In a state in which the input signal SI is blocked, the first output signal SOX provided from the first low-pass filter 460 is generated by the amplifier 200 , the first mixer 360 and the first low-pass filter 460 . represents the first offset voltage VOSX of the first signal channel including In a state in which the input signal SI is blocked, the second output signal SOY provided from the second low-pass filter 470 is generated by the amplifier 200 , the second mixer 370 , and the second low-pass filter 470 . represents the second offset voltage VOSY of the second signal channel including

During the time period t2 to t3, the mode signal MD indicates the second operation mode OM2 as a logic high level, and the input unit 100 responds to the mode signal MD indicating the second operation mode OM2. (SI) is transmitted to the amplification unit 200 . In this case, the first output signal SOX provided from the first low-pass filter 460 represents the first output voltage VOX, and the second output signal SOY provided from the second low-pass filter 470 . denotes the second output voltage VOY.

As described above, the demodulation frequency component of the input signal Si may be expressed as Vi*sin(wt), and the first demodulated clock signal CKX may be expressed as Vd*sin(wt+θ). In this case, the first rectified signal SRX generated from the first mixer 360 during the time period t2 to t3 may be expressed as Equation (6).

In Equation 6, Ga represents the gain of the amplifier 200, θ represents the phase difference between the demodulation frequency component of the input signal Si and the first demodulated clock signal SKX, and w represents an angle corresponding to the demodulation frequency Indicates the angular frequency. The time-dependent component of the first rectified signal SRX is removed by the first low-pass filter 460 , and as a result, the first output voltage VOX may be expressed as Equation (7).

As described above, since the second demodulated clock signal CKY has a phase difference of 90 degrees from the first demodulated clock signal CKX, it can be expressed as Vd*cos(wt+θ). In this case, the second rectified signal SRY generated from the second mixer 370 during the time period t2 to t3 may be expressed as Equation (8).

The time-dependent component of the second rectified signal SRY is removed by the second low-pass filter 470, and as a result, the second output voltage VOY may be expressed as Equation 9.

The magnitude Vo of the demodulation frequency component of the input signal Si can be obtained from Equations 7 and 9, and the result is as Equation 10.

As described above, the lock-in amplifier according to embodiments of the present invention uses two demodulated clock signals CKX and CKY having a phase difference of 90 degrees regardless of the phase of the input signal, and uses two orthogonal components, that is, In - By detecting the phase component (VOX) and quadrature component (VOY) and using them to calculate the magnitude (Vo) of the demodulation frequency component of the input signal, the phase adjustment circuit and the feedback circuit for the conventional phase lock-in are eliminated and the configuration is simplified and reduced size. In addition, the lock-in amplifier according to the embodiments of the present invention extracts the offset voltages VOSX and VOSY indicating the offset of the internal circuit of the lock-in amplifier to accurately provide the magnitude Vo of the demodulation frequency component of the input signal SI. can do.

According to embodiments of the present invention, the clock signal generator 30 of FIG. 1 may include a first demodulated clock signal CKX and a second demodulated clock signal CKX based on a reference clock signal CKR having a frequency that is an integer multiple of a demodulation frequency. It may include a plurality of flip-flops generating the clock signal CKY. Hereinafter, with reference to FIGS. 13, 14 and 15, the first demodulated clock signal CKX and the second demodulated clock signal CKY are generated based on the reference clock signal CKR having a frequency four times the demodulation frequency. An embodiment of the clock signal generators 31 and 32 including three flip-flops will be described, and based on the reference clock signal CKR having a frequency twice the demodulation frequency with reference to FIGS. 16 and 17 . An embodiment of the clock signal generator 33 including two flip-flops generating the first demodulated clock signal CKX and the second demodulated clock signal CKY will be described.

13 and 14 are diagrams illustrating embodiments of a clock signal generator included in the lock-in amplifier of FIG. 1 , and FIG. 15 is a timing diagram illustrating an operation of the clock signal generator of FIGS. 13 and 14 .

Referring to FIG. 13 , the clock signal generator 31 includes a first flip-flop FF1 , a second flip-flop FF2 , and a third flip-flop FF3 .

The first flip-flop FF1 receives the reference clock signal CKR through the clock terminal CK, the data terminal D is connected to the inverted output terminal QB, and the first flip-flop FF1 receives the reference clock signal CKR through the non-inverted output terminal Q. A clock signal CKa is generated, and a second clock signal CKb is generated through the inverted output terminal QB.

The second flip-flop FF2 receives the first clock signal CKa through the clock terminal CK, the data terminal D is connected to the inverted output terminal QB, and the second flip-flop FF2 receives the first clock signal CKa through the non-inverted output terminal Q. 1 Generates a demodulated clock signal CKX.

The third flip-flop FF3 receives the second clock signal CKb through the clock terminal CK, the data terminal D is connected to the inverted output terminal QB, and the third flip-flop FF3 receives the second clock signal CKb through the non-inverted output terminal Q. 2 A demodulated clock signal CKY is generated.

In an embodiment, all of the first flip-flop FF1 , the second flip-flop FF2 , and the third flip-flop FF3 may be implemented as a rising edge triggered D-flip-flop. A rising edge triggered D-flip-flop will be described below with reference to FIG. 18 .

Since the clock signal generator 32 of FIG. 14 is similar to the clock signal generator 31 of FIG. 13 , the overlapping description will be omitted. However, in the clock signal generator 31 of FIG. 13 , the data terminal D of the third flip-flop FF3 is connected to the inverted output terminal QB of the third flip-flop FF3, but the clock signal of FIG. In the generator 32 , the data terminal D of the third flip-flop FF3 is connected to the non-inverting output terminal Q of the second flip-flop FF2. Referring to FIGS. 13, 14 and 15 , , the first flip-flop FF1 generates a first clock signal CKa and a second clock signal CKb that toggle in synchronization with a rising edge of the reference clock signal CKR. The first clock signal CKa and the second clock signal CKb correspond to inverted signals. The second flip-flop FF2 generates a first demodulated clock signal CKX that toggles in synchronization with a rising edge of the first clock signal CKa. The third flip-flop FF3 generates a second demodulated clock signal CKY that toggles in synchronization with a rising edge of the second clock signal CKb.

As a result, the first demodulated clock signal CKX and the second demodulated clock signal CKY may have a phase difference of 90 degrees, and the frequency of the reference clock signal CKR may correspond to four times the demodulation frequency.

16 is a diagram illustrating an embodiment of a clock signal generator included in the lock-in amplifier of FIG. 1 , and FIG. 17 is a timing diagram illustrating an operation of the clock signal generator of FIG. 16 .

Referring to FIG. 16 , the clock signal generator 33 includes a first flip-flop FFa and a second flip-flop FFb.

The first flip-flop FFa receives the reference clock signal CKR through the clock terminal CK, the data terminal D is connected to the inverted output terminal QB, and the first flip-flop FFa receives the reference clock signal CKR through the non-inverted output terminal Q. A demodulated clock signal CKY is generated.

The second flip-flop FFb receives the inverted signal of the reference clock signal CKR through the clock terminal CK, the data terminal D is connected to the inverted output terminal QB, and the non-inverted output terminal Q to generate the second demodulated clock signal CKY.

In an embodiment, the first flip-flop FFa may be implemented as a rising-edge triggered D-flip-flop, and the second flip-flop FFb may be implemented as a falling-edge triggered D-flip-flop. A rising edge triggered D-flip-flop and a falling edge triggered D-flip-flop will be described below with reference to FIG. 18 .

16 and 17 , the first flip-flop FFa generates a first demodulated clock signal CKX that toggles in synchronization with the rising edge of the reference clock signal CKR. The second flip-flop FFb generates a second demodulated clock signal CKY that toggles in synchronization with the falling edge of the reference clock signal CKR.

As a result, the first demodulated clock signal CKX and the second demodulated clock signal CKY may have a phase difference of 90 degrees, and the frequency of the reference clock signal CKR may correspond to twice the demodulation frequency.

18 is a circuit diagram illustrating an embodiment of a flip-flop included in a clock signal generator.

Referring to FIG. 18 , the D-flip-flop 50 includes a first inverter 111 , a second inverter 112 , a first switch 113 , a third inverter 114 , a fourth inverter 115 , and a 2 switches 116 and a fifth inverter 117 .

The output of the first inverter 111 is connected to the input of the second inverter 112 and has a latch structure in which the output of the second inverter 112 is connected to the input of the first inverter 111 . In addition, the output of the third inverter 114 is connected to the input of the fourth inverter 115 and the output of the fourth inverter 115 is connected to the input of the third inverter 114 has a latch structure.

In the examples of FIGS. 13, 14 and 16 , the output of the fifth inverter 117 corresponds to the inverting output terminal QB and the output of the fourth inverter 115 corresponds to the non-inverting output terminal Q. The first switch 113 is connected between the data terminal D and the input of the second inverter 112 , and the control terminal CK of the first switch 113 corresponds to a clock terminal. A clock signal CLK is applied to the control terminal CK of the first switch 113 and the second switch 116 .

18 shows an example in which the first switch 113 is a PMOS type and the second switch 116 is an NMOS type. In this case, the D-flip-flop 50 corresponds to a rising-edge triggered D-flip-flop.

When the clock signal CLK applied to the control terminal CK is logic low, the output of the D-flip-flop 50 of FIG. 18 is in a memory for the previous data value, i.e., in a storage state and the data terminal D Even if the logic state changes, the output state of the flip-flop does not change. That is, at this time, the data terminal D is transmitted as an inverted signal by the second inverter 112 to the output node N1 of the second inverter 112 , but since the second switch 116 is in the off state, the flip-flop It is not transmitted to the output terminals (Q, QB) of When the clock signal CLK transitions to logic high, that is, at the rising edge of the clock signal CLK, the moment the first switch 113 is turned off, the value stored in the output node N1 of the second inverter 112 becomes the second 1 is latched and maintained through the inverter 111 and the second inverter 112, is transferred through the second switch 116, is inverted again by the fourth inverter 115, and the clock signal ( CLK) a data value triggered on a rising edge, and the inverted data value is transferred to the inverted output terminal QB. Afterwards, when the clock signal CLK falls and becomes a logic low, the second switch 116 is turned off, and the previous output value is transferred to the output terminal Q, QB), and at this time, the new data value is inverted and transmitted to the output node N1 of the second inverter 112 by the turn-on of the first switch 113 and the second inverter 112 .

A flip-flop whose logic state changes in synchronization with the edge of a signal applied to the control terminal CK as described above is called an edge-triggered type, and the D-flip-flop of FIG. 18 is a rising-edge-triggered D-flip. corresponds to the flop. The rising-edge triggered D-flip-flop performs a toggling operation in which the storage state is reversed from a logic high to a logic low or from a logic low to a logic high every rising edge of the clock signal CLK.

Meanwhile, a falling-edge triggered D-flip-flop may be implemented by using the first switch 113 as an NMOS type and the second switch 116 as a PMOS type. Also, instead of changing the types of the first switch 113 and the second switch 116 , a falling-edge triggered D-flip-flop may be implemented by applying an inverted signal of the original signal to the control terminal CK.

As described above, the first demodulated clock signal CKX and the second demodulated clock signal CKY having a phase difference of 90 degrees may be generated using flip-flops performing the toggling operation.

19 is a block diagram illustrating an integrated circuit including a lock-in amplifier according to embodiments of the present invention.

Referring to FIG. 19 , the integrated circuit 50 may include a lock-in amplifier (LIA) 10 , an analog-to-digital converter (ADC) 60 , and a control unit (CTRL) 70 .

The integrated circuit 50 of FIG. 19 may be a semiconductor integrated circuit simultaneously formed using one semiconductor die. The integrated circuit 50 may be packaged as one chip.

The lock-in amplifier 10 receives an input signal SI and generates an output signal SO. The output signal SO may be a voltage signal having a voltage level according to an operation mode. As described with reference to FIGS. 1 to 18 , the lock-in amplifier 10 includes a clock signal generator and a detector. The clock signal generator generates a first demodulated clock signal and a second demodulated clock signal having a phase difference of 90 degrees and having the same demodulation frequency. The detection unit provides an offset voltage corresponding to an offset of an internal circuit in a first operation mode, based on an input signal SI, the first demodulated clock signal, and the second demodulated clock signal, and in a second operation mode, the input A first output voltage and a second output voltage corresponding to the magnitude of the demodulation frequency component of the signal are provided.

The analog-to-digital converter 60 converts the offset voltage, the first output voltage, and the second output voltage into digital values, respectively. The analog-to-digital converter 60 may sample the output of the lock-in amplifier 10 at an appropriate time according to the control of the controller 70 . As shown in the timing diagrams of FIGS. 9 and 12 , a certain time is required for the first output voltage VOX and the second output voltage VOY to be stabilized to a substantial DC voltage according to the time constant of the low-pass filter. can The controller 70 may determine the timing at which the analog-to-digital converter 60 samples the output of the lock-in amplifier 10 in consideration of the stabilization time. After stabilization, the analog-to-digital converter 60 samples N times for a period of time after stabilization, adds all the outputs, and divides by N to obtain an average filtering can be performed.

The controller 70 controls the lock-in amplifier 10 and the analog-to-digital converter 60 and calculates the magnitude of the demodulation frequency component of the input signal SI based on the digital values. To this end, the control unit 70 may include a microprocessor, a built-in memory, and the like. For example, the above-described mode signal MD and clock selection signal SEL may be provided from the controller 70 . In one embodiment, the lock-in amplifier 10 may have a single signal channel structure as described above with reference to FIGS. 6 and 9, and in this case, the control unit 70 controls the input signal SI by Equation 5. It is possible to calculate the magnitude (Vo) of the demodulation frequency component of . In another embodiment, the lock-in amplifier 10 may have a structure of a double signal channel as described above with reference to FIGS. 11 and 12. In this case, the control unit 70 controls the input signal SI by Equation (10). It is possible to calculate the magnitude (Vo) of the demodulation frequency component of .

As described above, the lock-in amplifier and the integrated circuit including the same according to embodiments of the present invention include two orthogonal two demodulated clock signals having the same demodulation frequency and having a phase difference of 90 degrees regardless of the phase of the input signal. By detecting the components (In-Phase component and Quadrature component) and using them to calculate the magnitude of the demodulation frequency component of the input signal, the phase adjustment circuit and the feedback circuit for the conventional phase lock-in are eliminated, and the configuration is simplified and the size is reduced. can be implemented as In addition, the lock-in amplifier and the integrated circuit including the same according to embodiments of the present invention can extract the offset voltage representing the offset of the internal circuit of the lock-in amplifier to accurately provide the magnitude of the demodulation frequency component of the input signal.

20 is a flowchart illustrating a signal measuring method according to embodiments of the present invention.

1, 2, 19 and 20, the integrated circuit 50 measures the offset voltage VOS using the included lock-in amplifier 10 (step S100). As described above, the offset voltage VOS may correspond to the voltage level of the output signal SO output when the input signal SI applied to the lock-in amplifier 10 is blocked. Also, the integrated circuit 50 measures the first output voltage VOX and the second output voltage VOY using the lock-in amplifier 10 (steps S200 and S300 ). As described above, the first output voltage VOX corresponds to the voltage level of the output signal SO when the first demodulated clock signal CKX and the input signal SI are mixed or multiplied, and the second output voltage (VOY) corresponds to the voltage level of the output signal SO when the input signal SI is mixed or multiplied with the second demodulated clock signal CKY having a phase difference of 90 degrees from the first demodulated clock signal CKX. can

The analog-to-digital converter 60 converts the measured analog DC voltages into digital values, respectively. The controller 70 of the integrated circuit 50 calculates the magnitude Vo of the demodulation frequency component of the input signal SI based on the digital values (step S400). The calculation of the magnitude Vo of the demodulation frequency component is the same as described with reference to Equations 1 to 10.

Although it is illustrated that the offset voltage VOS, the first output voltage VOX, and the second output voltage VOY are sequentially measured in FIG. 20 , the measuring order of the voltages may be variously changed. According to an embodiment, when the structure of the double signal channel is adopted, the first output voltage VOX and the second output voltage VOY may be simultaneously measured.

21 is a block diagram illustrating a portable measurement device including a lock-in amplifier according to embodiments of the present invention.

Referring to FIG. 21 , the portable measuring device 900 may include a modulator (MOD) 910 , a sensor (SEN) 920 , and an integrated circuit chip 50 . 21 , an object to be inspected (OBJ) 90 is shown together for convenience.

The modulator 910 generates a modulated signal SM1 based on the modulated clock signal. The sensor 920 senses a signal SM2 generated by a mutual reaction between the modulated signal SM1 and the subject 90 to generate an input signal SI. In one embodiment, the modulator 910 may be implemented as a laser diode and the sensor 920 may be implemented as a photodiode. In this case, the signal SM2 input to the sensor 920 may include a transmitted wave, a reflected wave, a refracted wave, a scattered wave, etc. of the modulated signal SM1 by the subject 90 .

The sensor 920 may provide a voltage signal or a current signal as the input signal SI. When the input signal SI is a current signal, the integrated circuit chip 50 may include a current-to-voltage converter for converting the input signal SI into a voltage signal and providing it to the lock-in amplifier 10 .

The integrated circuit chip 50 may include a lock-in amplifier (LIA) 10 , an analog-to-digital converter (ADC) 60 , and a control unit (CTRL) 70 as described with reference to FIG. 19 . As described with reference to FIGS. 1 to 18 , the lock-in amplifier 10 includes a clock signal generator and a detector. The clock signal generator generates a first demodulated clock signal and a second demodulated clock signal having a phase difference of 90 degrees and having the same demodulation frequency. The detection unit provides an offset voltage corresponding to an offset of an internal circuit in a first operation mode, based on an input signal, the first demodulated clock signal, and the second demodulated clock signal, and demodulates the input signal in a second operation mode A first output voltage and a second output voltage corresponding to the magnitude of the frequency component are provided. The analog-to-digital converter 60 converts the offset voltage, the first output voltage, and the second output voltage into digital values, respectively. The controller 70 controls the lock-in amplifier 10 and the analog-to-digital converter 60 and calculates the magnitude of the demodulation frequency component of the input signal SI based on the digital values.

The portable measuring device 900 may be any measuring device requiring a small size and low power consumption. For example, the portable measuring device 900 may be various signal measuring devices such as a blood glucose meter, a blood pressure monitor, and an electronic nose.

As described above, the lock-in amplifier, the integrated circuit and the portable measuring device including the same according to the embodiments of the present invention, use two demodulated clock signals having a phase difference of 90 degrees regardless of the phase of the input signal, using two orthogonal two components. The phase adjustment circuit and the feedback circuit for the conventional phase lock-in are eliminated by detecting the in-phase components and quadrature components and using them to calculate the magnitude of the demodulation frequency component of the input signal, and with a simplified configuration and reduced size. can be implemented. In addition, the lock-in amplifier, the integrated circuit including the same, and the portable measurement device according to the embodiments of the present invention extract the offset voltage representing the offset of the internal circuit of the lock-in amplifier to accurately provide the magnitude of the demodulation frequency component of the input signal. have.

22 is a block diagram illustrating a computing system including a measurement device according to an embodiment of the present invention.

Referring to FIG. 22 , the computing system 1000 includes a processor 1010 , a memory device 1020 , a storage device 1030 , an input/output device 1040 , a power supply 1050 , and a signal measuring device (MSRM) 900 . may include. Meanwhile, although not shown in FIG. 22 , the computing system 1000 may further include ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc., or communicating with other electronic devices. .

The processor 1010 may perform certain calculations or tasks. According to an embodiment, the processor 1010 may be a micro-processor or a central processing unit (CPU). The processor 1010 includes a memory device 1020 , a storage device 1030 , a photographing device 900 , and an input/output device 1040 through an address bus, a control bus, and a data bus. can communicate with Depending on the embodiment, the processor 1010 may also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus. The memory device 1020 may store data necessary for the operation of the computing system 1000 . For example, the memory device 1020 may be implemented as DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM. have. The storage device 1030 may include a solid state drive, a hard disk drive, a CD-ROM, and the like. The input/output device 1040 may include input means such as a keyboard, keypad, and mouse, and output means such as a printer and a display. The power supply 1050 may supply an operating voltage required for the operation of the electronic device 1000 .

The signal measuring apparatus 900 may include a lock-in amplifier according to embodiments of the present invention as described with reference to FIGS. 1 to 18 . The lock-in amplifier and the signal measuring device 900 including the same include two orthogonal components (in-phase component and quadrature component) using two demodulated clock signals having a phase difference of 90 degrees regardless of the phase of the input signal. By detecting and using this to calculate the magnitude of the demodulation frequency component of the input signal, the phase adjustment circuit and the feedback circuit for the conventional phase lock-in can be eliminated and implemented with a simplified configuration and reduced size. In addition, the lock-in amplifier and the signal measuring device 900 including the same can accurately provide the magnitude of the demodulation frequency component of the input signal by extracting the offset voltage indicating the offset of the internal circuit of the lock-in amplifier.

The computing system 1000 may be implemented in various types of packages. For example, at least some components of the computing system 1000 may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic Dual In-Line Package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline( SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer- It may be mounted using packages such as Level Processed Stack Package (WSP).

Meanwhile, the computing system 1000 should be interpreted as any computing system including the lock-in amplifier according to embodiments of the present invention. For example, the computing system 1000 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, and the like.

23 is a block diagram illustrating an example of an interface used in the computing system of FIG. 22 .

Referring to FIG. 23 , the computing system 1100 may be implemented as a data processing device capable of using or supporting the MIPI interface, and may include an application processor 1110 , an image sensor 1140 , and a display 1150 . have. The CSI host 1112 of the application processor 1110 may perform serial communication with the CSI device 1141 of the image sensor 1140 through a camera serial interface (CSI). In an embodiment, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the application processor 1110 may perform serial communication with the DSI device 1151 of the display 1150 through a Display Serial Interface (DSI).

In an embodiment, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). Furthermore, the computing system 1100 may further include a radio frequency (RF) chip 1160 capable of communicating with the application processor 1110 . The PHY 1113 of the computing system 1100 and the PHY 1161 of the RF chip 1160 may perform data transmission/reception according to Mobile Industry Processor Interface (MIPI) DigRF. In addition, the application processor 1110 may further include a DigRF MASTER 1114 for controlling data transmission/reception according to the MIPI DigRF of the PHY 1161 .

Meanwhile, the computing system 1100 may include a Global Positioning System (GPS) 1120 , a storage 1170 , a microphone 1180 , a Dynamic Random Access Memory (DRAM) 1185 and a speaker 1190 . can The computing system 1100 may also include a signal measurement device (MSRM) 900 including a lock-in amplifier according to embodiments of the present invention. In addition, the computing system 1100 uses an Ultra WideBand (UWB) 1210 , a Wireless Local Area Network (WLAN) 1220 and a Worldwide Interoperability for Microwave Access (WIMAX) 1230 , etc. communication can be performed. However, the structure and interface of the computing system 1100 are examples and are not limited thereto.

As described above, the lock-in amplifier, the integrated circuit, and the portable measurement device including the lock-in amplifier according to the embodiments of the present invention use two demodulated clock signals having a phase difference of 90 degrees regardless of the phase of the input signal to be orthogonal to each other. By detecting two components (in-phase component and quadrature component) and using them to calculate the magnitude of the demodulation frequency component of the input signal, the phase adjustment circuit and feedback circuit for the conventional phase lock-in are eliminated, and the simplified configuration and reduced size can be implemented. In addition, the lock-in amplifier according to embodiments of the present invention provides demodulated clock signals having a phase difference of 90 degrees using a plurality of flip-flops, so that the size and power consumption can be further reduced, and can be efficiently used in portable devices. have.

In addition, the lock-in amplifier, the integrated circuit and the portable measuring device including the same according to the embodiments of the present invention extract the offset voltage representing the offset of the internal circuit of the lock-in amplifier to accurately provide the magnitude of the demodulation frequency component of the input signal. can

In addition, the lock-in amplifier, the integrated circuit including the same, and the portable measurement device according to the embodiments of the present invention sequentially apply the first output voltage and the second output voltage for each operation mode using a single signal channel including one mixer. , it is possible to prevent mismatch between the conventional channels and accurately provide the magnitude of the demodulation frequency component of the input signal.

Embodiments of the present invention may be usefully used in a signal measuring apparatus requiring a small size and low power consumption and a system including the same. In particular, embodiments of the present invention are applied to a signal measuring device such as a blood glucose meter, a blood pressure monitor, an electronic nose, and the like, and a portable electronic device such as a cellular phone, a smart phone, and a wearable device including the same. It can be applied more usefully.

Although the present invention has been described with reference to preferred embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the following claims. you will understand that you can

10: lock-in amplifier
20: detection unit
30: clock signal generator
100: input unit
200: amplification unit
300: mixer unit
400: filter unit

Claims (20)

a clock signal generator which has a phase difference of 90 degrees and generates a first demodulated clock signal and a second demodulated clock signal having the same demodulation frequency; and
Based on an input signal, the first demodulated clock signal and the second demodulated clock signal, an offset voltage corresponding to an offset of an internal circuit is provided in a first operation mode, and a demodulation frequency component of the input signal in a second operation mode is provided. A detector for providing a first output voltage and a second output voltage corresponding to the magnitude,
The detector may include at least one mixer to sequentially generate the offset voltage, the first output voltage, and the second output voltage for each operation mode. delete The method of claim 1,
The lock-in amplifier, characterized in that the magnitude of the demodulation frequency component of the input signal is determined by the following equation.
Vo=[(VOX-VOS) ² +(VOY-VOS) ² ] ^1/2
where Vo is the output of the lock-in amplifier corresponding to the magnitude of the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage, and VOS is the offset voltage. The method of claim 1,
The detection unit sequentially generates a first offset voltage and the first output voltage for each operation mode using a first mixer and sequentially generates a second offset voltage and the second output voltage using a second mixer Features a lock-in amplifier. 5. The method of claim 4,
The lock-in amplifier, characterized in that the magnitude of the demodulation frequency component of the input signal is determined by the following equation.
Vo=[(VOX-VOSX) ² +(VOY-VOSY) ² ] ^1/2
where Vo is the output of the lock-in amplifier corresponding to the magnitude of the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage, VOSX is the first offset voltage, and VOSY is the second offset voltage. According to claim 1, wherein the detection unit,
an amplifying unit amplifying the input signal in the second operation mode and outputting an amplified signal;
a mixer unit for generating a first rectified signal by multiplying the amplified signal with the first demodulated clock signal in the second operation mode and generating a second rectified signal by multiplying the amplified signal with the second demodulated clock signal; and
and a filter unit configured to generate the first output voltage by filtering the first rectified signal in the second operation mode and to generate the second output voltage by filtering the second rectified signal. The method of claim 6, wherein the mixer unit,
A first input terminal for receiving the amplified signal, a second input terminal for sequentially receiving the first demodulated clock signal and the second demodulated clock signal in the second operation mode, and the first rectification in the second operation mode A lock-in amplifier comprising a mixer having an output terminal for sequentially outputting a signal and the second rectified signal. The method of claim 7, wherein the filter unit,
and a low pass filter coupled to the output terminal of the mixer for sequentially generating the first output voltage and the second output voltage in the second mode of operation. 8. The method of claim 7,
and a clock selector which selects one of the first demodulated clock signal and the second demodulated clock signal and provides it to the second input terminal of the mixer. The method of claim 6, wherein the mixer unit,
a first mixer having a first input terminal for receiving the amplified signal, a second input terminal for receiving the first demodulated clock signal, and a first output terminal for outputting the first rectified signal; and
and a second mixer having a third input terminal for receiving the amplified signal, a fourth input terminal for receiving the second demodulated clock signal, and a second output terminal for outputting the second rectified signal. amplifier. The method of claim 10, wherein the filter unit,
a first low-pass filter coupled to the first output terminal of the first mixer to generate a first offset voltage in the first mode of operation and to generate the first output voltage in the second mode of operation; and
and a second low pass filter coupled to the second output terminal of the second mixer to generate a second offset voltage in the first mode of operation and to generate the second output voltage in the second mode of operation. A lock-in amplifier with The method of claim 6, wherein the detection unit,
The lock-in amplifier further comprising an input unit for blocking the input signal applied to the amplifier unit in the first operation mode in response to a mode signal. 13. The method of claim 12,
and the filter unit generates the offset voltage while the mode signal is activated and the input signal applied to the amplifier is blocked by the input unit. The method of claim 1, wherein the clock signal generator comprises:
and a plurality of flip-flops for generating the first demodulated clock signal and the second demodulated clock signal based on a reference clock signal having a frequency that is an integer multiple of the demodulation frequency. The method of claim 1, wherein the clock signal generator comprises:
a first flip-flop receiving a reference clock signal at a clock terminal, a data terminal coupled to an inverting output terminal, generating a first clock signal at a non-inverting output terminal, and generating a second clock signal at the inverting output terminal;
a second flip-flop receiving the first clock signal at a clock terminal, a data terminal coupled to an inverting output terminal, and generating the first demodulated clock signal at a non-inverting output terminal; and
a third flip-flop receiving the second clock signal at a clock terminal, a data terminal coupled to an inverting output terminal, and generating the second demodulated clock signal at a non-inverting output terminal;
and the frequency of the reference clock signal is four times the demodulation frequency. The method of claim 1, wherein the clock signal generator comprises:
a first flip-flop receiving a reference clock signal at a clock terminal, a data terminal coupled to an inverting output terminal, and generating the first demodulated clock signal at a non-inverting output terminal; and
a second flip-flop receiving an inverted signal of the reference clock signal at a clock terminal, a data terminal coupled to an inverting output terminal, and generating the second demodulated clock signal at a non-inverting output terminal;
and the frequency of the reference clock signal is twice the demodulation frequency. a clock signal generator which has a phase difference of 90 degrees and generates a first demodulated clock signal and a second demodulated clock signal having the same demodulation frequency;
Based on an input signal, the first demodulated clock signal and the second demodulated clock signal, an offset voltage corresponding to an offset of an internal circuit is provided in a first operation mode, and a demodulation frequency component of the input signal in a second operation mode is provided. a detection unit providing a first output voltage and a second output voltage corresponding to the magnitude;
an analog-to-digital converter converting the offset voltage, the second output voltage, and the second output voltage into digital values, respectively; and
a control unit for controlling the clock signal generating unit, the detecting unit, and the analog-to-digital converter, and calculating the magnitude of the demodulation frequency component of the input signal based on the digital values;
The detector may be configured to sequentially generate the offset voltage, the first output voltage, and the second output voltage for each operation mode using at least one mixer. a modulator for generating a modulated signal based on the modulated clock signal;
a sensor for generating an input signal by sensing a signal generated by a mutual reaction between the modulated signal and the subject;
a clock signal generator which has a phase difference of 90 degrees and generates a first demodulated clock signal and a second demodulated clock signal having the same demodulation frequency;
Based on the input signal, the first demodulated clock signal and the second demodulated clock signal, an offset voltage corresponding to an offset of an internal circuit is provided in a first operation mode, and a demodulation frequency component of the input signal in a second operation mode a detection unit providing a first output voltage and a second output voltage corresponding to the magnitude of ;
an analog-to-digital converter converting the offset voltage, the first output voltage, and the second output voltage into digital values, respectively; and
and a controller controlling the clock signal generator, the detector, and the analog-to-digital converter, and calculating the magnitude of the demodulation frequency component of the input signal based on the digital values. The method of claim 18, wherein the clock signal generator comprises:
and a plurality of flip-flops for generating the first demodulated clock signal and the second demodulated clock signal based on a reference clock signal having a frequency that is an integer multiple of the demodulation frequency. 19. The method of claim 18,
and at least one of the first demodulated clock signal and the second demodulated clock signal is provided to the modulator as the modulated clock signal.

Images