KR102435216B1 - Display device - Google Patents

Abstract

The present invention relates to a display device. A display device according to an embodiment of the present invention provides a display panel for displaying an image, a gate driver supplying a gate signal to a gate line of the display panel, and a gate control signal for generating the gate signal to the gate driver and a level shifter unit, and a timing controller supplying a serial data sequence for generation of the gate control signal to the level shifter unit. According to the present invention, by reducing the number of signal lines and input/output pins required for transmission of a control signal, the complexity of circuit design can be reduced and the size of a substrate or chip can be reduced.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode Various display devices such as an organic light emitting diode (OLED) are being used.

Some of the above-described display devices, for example, a liquid crystal display device or an organic light emitting diode display device, include a display panel including a plurality of sub-pixels arranged in a matrix form, a driver for driving the display panel, and a timing controller for controlling the driver. Here, the driver includes a gate driver that supplies a gate signal (or scan signal) to the display panel and a data driver that supplies a data signal to the display panel.

The timing controller generates a control signal for controlling the operation timing of the gate driver based on the timing signals and driving timing information stored in the memory. The control signal generated by the timing controller is transmitted to the level shifter, and the level shifter generates a gate control signal based on the control signal supplied from the timing controller and supplies it to the gate driver. In addition, the gate driver generates a gate signal based on the gate control signal supplied from the level shifter and applies it to the display panel.

For signal transmission between the timing controller and the level shifter, signal lines and input/output pins corresponding to the number of control signals generated by the timing controller should be provided in the timing controller and the level shifter. However, as the number of signal lines connected to the timing controller and the level shifter and corresponding input/output pins increases, the circuit design becomes more complex and the size of the substrate or chip increases.

An object of the present invention is to provide a display device capable of reducing the size of a substrate or chip while reducing the complexity of circuit design by reducing the number of signal lines and input/output pins required for transmission of a control signal.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned may be understood by the following description, and will be more clearly understood by the examples of the present invention. It will also be readily apparent that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the appended claims.

A display device according to an embodiment of the present invention provides a display panel for displaying an image, a gate driver supplying a gate signal to a gate line of the display panel, and a gate control signal for generating the gate signal to the gate driver and a level shifter unit, and a timing controller supplying a serial data sequence for generation of the gate control signal to the level shifter unit.

In an embodiment of the present invention, the timing controller generates the serial data sequence by serializing a plurality of control signals input in parallel.

In addition, in an embodiment of the present invention, the timing controller includes a control signal generator that generates a plurality of control signals, a first sampler that samples the plurality of control signals input in parallel, and a sampled control signal using the sampled control signal. and a serializer for generating a serial data sequence.

Also in one embodiment of the present invention, the serial data sequence includes a sequence start field, a control signal field, and a sequence end field.

Also, in an embodiment of the present invention, the level shifter generates the gate control signal by parallelizing the serial data sequence.

Also, in an embodiment of the present invention, the level shifter unit includes a second sampling unit for sampling the serial data sequence, a parallelization unit for parallelizing the sampled control signal, and a gate generating the gate control signal using the parallelized control signal. and a control signal generator.

Also, in an embodiment of the present invention, the timing controller generates the serial data sequence based on a clock signal, and the level shifter generates the gate control signal from the serial data sequence based on the clock signal.

According to the present invention, by reducing the number of signal lines and input/output pins required for transmission of a control signal, the complexity of circuit design can be reduced and the size of a substrate or chip can be reduced.

1 is a block diagram showing the configuration of a display device.
2 and 3 are block diagrams showing the configuration of a timing controller and a level shifter according to the prior art.
4 is a block diagram illustrating a configuration of a timing controller according to an embodiment of the present invention.
5 is a block diagram illustrating a configuration of a level shifter unit according to an embodiment of the present invention.
6 is a waveform diagram of a control signal generated inside a timing controller according to an embodiment of the present invention.
7 and 8 are diagrams for explaining a process in which the timing controller samples the control signal shown in FIG. 6 according to an embodiment of the present invention.
9 to 11 are diagrams for explaining a process of a level shifter generating a parallelized control signal using a serial data sequence provided from a timing controller according to an embodiment of the present invention.

The above-described objects, features and advantages will be described below in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention pertains will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

1 is a block diagram showing the configuration of a display device.

1 , the display device includes an image supply unit 110 , a timing controller 120 , a level shifter 135 , a gate driver 130 , a data driver 140 , and a display panel 150 . .

The image supply unit 110 image-processes the data signal and outputs the processed data signal together with a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The image supply unit 110 transmits a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, a data signal, etc. to the timing controller 120 through a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface. ) is supplied to

The timing controller 120 receives the data signal DATA from the image supply unit 110 along with a driving signal including a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 120 outputs a data timing control signal DDC for controlling the operation timing of the data driver 140 and a control signal for controlling the operation timing of the gate driver 130 based on the driving signal.

The timing controller 120 outputs the data signal DATA together with the data timing control signal DDC and the clock signal through a communication interface or the like, and controls operation timings of the gate driver 130 and the data driver 140 . The timing controller 120 generates control signals, such as a start signal, a clock signal, and a driving signal, and supplies them to the level shifter 135 .

The level shifter 135 generates a gate control signal using a control signal supplied from the timing controller 120 . The level shifter 135 supplies the generated gate control signal to the gate driver 130 .

The gate driver 130 outputs a gate signal (or a scan signal) in response to the gate control signal supplied from the level shifter 135 . The gate driver 130 shifts and outputs a gate signal having a gate high signal and a gate low signal using the gate control signal, and supplies it to each sub-pixel SP constituting the display panel 150 .

The level shifter 135 may be implemented in the form of an integrated circuit (IC), and the gate driver 130 may be disposed on one or both non-display areas of the display panel 150 in a gate-in-panel manner. can

2 and 3 are block diagrams showing the configuration of a timing controller and a level shifter according to the related art.

First, referring to FIG. 2 , the timing controller 120 according to the related art outputs a plurality of control signals through a plurality of control signal output pins T_OUT01 to T_OUT13. For reference, although an embodiment in which the timing controller 120 outputs 13 control signals is illustrated in FIG. 2 , the number of control signals output by the timing controller 120 may vary.

As described above, the plurality of control signals output by the timing controller 120 are supplied to the level shifter 135 . The level shifter unit 135 is a power voltage for receiving the control signal input pins IN01 to IN13 for receiving a plurality of control signals supplied from the timing control unit 120 and a power voltage supplied from a power supply unit (not shown). It has input pins (VGH, VGL).

The level shifter 135 includes a control circuit 202 and a gate control signal generator 204 . The control circuit unit 202 adjusts each of the control signals input through the control signal input pins IN01 to IN10 to three levels by using the three reference voltage level signals input through the control signal input pins IN11 to IN13. A plurality of driving voltage signals having

The gate control signal generator 204 gates a plurality of driving voltage signals output from the control circuit unit 202 by using the power voltage supplied from the power supply unit (not shown) through the power voltage input pins VGH and VGL. converted to a control signal. Accordingly, the gate control signal generator 204 outputs a plurality of gate control signals having a voltage swing width from the gate low voltage VGL to the gate high voltage VGL through the gate control signal output pins OUT01 to OUT10 . do.

However, according to the conventional configuration as shown in FIG. 2 , each control signal output pin is provided to the timing controller 120 and the level shifter 135 according to the number of a plurality of control signals supplied from the timing controller 120 to the level shifter 135 . (T_OUT01 to T_OUT13) and control signal input pins (IN01 to IN13) must be provided. In addition, signal lines for connecting corresponding pins should be connected to the control signal output pins T_OUT01 to T_OUT13 and the control signal input pins IN01 to IN13.

As a result, according to the conventional configuration as shown in FIG. 2 , the number of input or output pins and signal lines to be provided in the timing controller 120 or the level shifter 135 becomes excessively large. Such an increase in the number of input or output pins and signal lines makes the design of a chip or a substrate for implementing the timing controller 120 and the level shifter 135 very complicated. In addition, due to an increase in the number of input or output pins and signal lines, the overall size of the panel increases.

In order to solve this problem, a timing controller and a level shifter having the configuration as shown in FIG. 3 may be used.

Referring to FIG. 3 , the timing controller 120 according to the related art performs an on clock signal and an off clock signal through an on clock signal output pin ONCLK, an off clock signal output pin OFFCLK, and a start signal output pin VST_I, respectively. Signal and start signal are output. Also, the timing controller 120 outputs a plurality of driving voltage signals having three levels through three control signal output pins T_OUT01 to T_OUT03.

The level shifter unit 135 includes an on-clock signal input pin ONCLK for receiving an on-clock signal, an off-clock signal, a start signal, and a plurality of driving voltage signals having three levels supplied from the timing controller 120; An off clock signal input pin (OFFCLK), a start signal input pin (VST_I), and three control signal input pins (IN01 to IN03) are provided. Also, the level shifter 135 includes power voltage input pins VGH and VGL for receiving a power voltage supplied from a power supply unit (not shown).

The control circuit unit 302 included in the level shifter unit 135 generates a plurality of gate clock signals using the on and off clock signals supplied from the timing control unit 120 and a plurality of driving voltage signals having three levels. create

In addition, the gate control signal generator 304 included in the level shifter 135 uses a plurality of gate clock signals supplied from the control circuit unit 302 and a power supply voltage supplied from a power supply unit (not shown) to obtain a gate low voltage. A plurality of gate control signals having a voltage swing width from (VGL) to a gate high voltage (VGL) are generated, and each generated gate control signal is output through the gate control signal output pins OUT01 to OUT05. Also, the gate control signal generator 304 outputs a start signal for generating the gate signal through the start signal output pin VST_O.

The conventional timing controller and level shifter having the configuration as shown in FIG. 3 generates a plurality of gate control signals using the on-clock signal and the off-clock signal, so compared to the timing controller and the level shifter as shown in FIG. It requires a small number of input and output pins and signal lines.

However, even according to the conventional configuration as shown in FIG. 3 , at least six input and output pins should be provided in the timing controller 120 and the level shifter 135 , respectively. Therefore, when a plurality of level shifters 135 are used according to the size or internal configuration of a panel used in a display device, it is difficult to avoid a problem in that the circuit design is still complicated and the panel size increases.

In addition, when the timing controller and the level shifter having the configuration shown in FIG. 3 are used, the circuit can be implemented with a smaller number of input and output pins compared to the configuration of FIG. 2, but can be generated as an on-clock signal and an off-clock signal. Since the waveform or type of the output signal is simple, it is difficult to generate a signal having various output waveforms.

The present invention is to solve the above problems that occur when using the timing controller and the level shifter according to the conventional configuration, and reduces the number of input and output pins and signal lines to reduce the complexity of circuit design and the size of the panel while reducing the number of input and output pins. A new timing control unit and a level shifter unit capable of generating a signal having an output waveform are provided.

Hereinafter, the configuration and functions of the timing controller and the level shifter included in the display device according to the present invention will be described in detail with reference to FIGS. 4 to 11 .

4 is a block diagram illustrating a configuration of a timing controller according to an embodiment of the present invention.

Referring to FIG. 4 , the timing controller 120 according to an embodiment of the present invention includes a control signal generator 402 , a first sampling unit 404 , and a serialization unit 406 .

The control signal generator 402 generates a plurality of control signals for generating the gate signal of the gate driver 130 . 4 , the control signal generator 402 generates and outputs 16 control signals CS01 to CS16. According to an embodiment, the plurality of control signals may be generated outside the timing controller 120 and input into the timing controller 120 .

Hereinafter, the configuration of the present invention will be described through an embodiment in which the control signal generating unit 402 generates 16 control signals CS01 to CS16, but the number of control signals generated by the control signal generating unit 402 is implemented It may vary depending on the example.

In addition, the control signal generator 402 outputs a clock signal CLK used for sampling and serializing the plurality of generated control signals.

The first sampling unit 404 receives a plurality of control signals CS01 to CS16 and a clock signal CLK from the control signal generation unit 402 . As shown in FIG. 4 , the first sampling unit 404 samples the plurality of control signals CS01 to CS16 input in parallel according to the clock signal CLK and outputs the plurality of sampled control signals SS01 to SS16.

The serializer 406 generates a serial data sequence SDS by using the plurality of sampled control signals SS01 to SS16 supplied from the first sampling unit 404 . In the serial data sequence SDS, each of the plurality of sampled control signals SS01 to SS16 is serialized and arranged as one data sequence.

The serial data sequence SDS and the clock signal CLK generated by the serializer 406 are leveled through the serial data sequence output pin S_OUT and the clock signal output pin CLK_OUT provided in the timing controller 120 , respectively. It is supplied to the shifter part.

5 is a block diagram illustrating a configuration of a level shifter unit according to an embodiment of the present invention.

Referring to FIG. 5 , the level shifter unit 135 according to an embodiment of the present invention includes a serial data sequence input pin S_IN for receiving a serial data sequence SDS supplied from the timing controller 120 and a clock signal. A clock signal input pin CLK for receiving (CLK) is provided.

In addition, the level shifter unit 135 according to an embodiment of the present invention includes a second sampling unit 502 , a parallelization unit 504 , and a gate control signal generation unit 506 .

The second sampling unit 502 generates sampled control signals DS01 to DS16 by sampling the serial data sequence SDS input through the serial data sequence input pin S_IN. The parallelization unit 504 generates parallelized control signals PS01 to PS16 by parallelizing the control signals DS01 to DS16 sampled by the second sampling unit 502 .

The gate control signal generator 506 uses the control signals PS01 to PS16 paralleled by the parallelization unit 504 and the power voltage supplied from the power supply unit (not shown) from the gate low voltage VGL to the gate high voltage. A plurality of gate control signals FS01 to FS16 having a voltage swing width up to VGL are generated. Each of the gate control signals FS01 to FS16 generated by the gate control signal generator 506 is output through the gate control signal output pins OUT01 to OUT16 and is supplied to the gate driver 130 .

As such, in the present invention, by serializing a plurality of control signals CS01 to CS16 input in parallel and generating one data sequence, an output pin provided in the timing controller 120 and an input pin provided in the level shifter 135 are generated. , and the number of signal lines connected to each pin can be significantly reduced compared to the prior art. As described above, by reducing the number of output pins provided in the timing control unit 120 , input pins provided in the level shifter unit 135 , and signal lines connected to each pin, the complexity of circuit design is reduced and the panel size is also reduced. .

In addition, according to the present invention, the plurality of control signals CS01 to CS16 are sampled as they are, included in the serial data sequence, and transmitted to the level shifter 135 . Accordingly, there is no limitation in the waveform and type of the control signal generated by the timing controller 120 and transmitted to the level shifter 135 . As a result, according to the present invention, there is an advantage in that it is possible to supply signals having more various waveforms than in the prior art of generating a gate control signal through an on-clock signal and an off-clock signal.

Hereinafter, a signal supply process and a gate control signal generation process by the timing controller and the level shifter according to the present invention will be described with reference to FIGS. 4 to 11 .

6 is a waveform diagram of a control signal generated inside a timing controller according to an embodiment of the present invention.

FIG. 6 shows waveforms according to time of each of the 16 control signals CS01 to CS16 generated by the control signal generator 402 . As shown in FIG. 6 , each of the 16 control signals CS01 to CS16 has a high state or a low state.

The first sampling unit 404 receives a plurality of control signals CS01 to CS16 and a clock signal CLK that are continuously generated as shown in FIG. 6 by the control signal generation unit 402 . The first sampling unit 404 samples each of the plurality of control signals CS01 to CS16 according to a predetermined sampling period. The sampling period of the first sampling unit 404 may be determined according to the period of the clock signal CLK.

7 and 8 are diagrams for explaining a process in which the timing controller samples the control signal shown in FIG. 6 according to an embodiment of the present invention. Hereinafter, the configuration of the present invention will be described through an embodiment in which the first sampling unit 404 samples the control signals CS01 to CS16 at two consecutive time points, namely, the time points 602 and 604, respectively.

First, the first sampling unit 404 samples the control signals CS01 to CS16 input at the time point 602 according to the cycle of the clock signal CLK. In FIG. 6 , the state of each of the control signals CS01 to CS16 is as follows when viewed at a time point 602 .

CS01: HIGH

CS02: HIGH

CS03: HIGH

CS04: HIGH

CS05: HIGH

CS06: HIGH

CS07: HIGH

CS08: LOW

CS09: HIGH

CS10: HIGH

CS11: HIGH

CS12: LOW

CS13: HIGH

CS14: HIGH

CS15: HIGH

CS16: HIGH

The first sampling unit 404 converts the state of each of the control signals CS01 to CS16 sampled as above into a digital value. That is, if the state of the control signal is HIGH, the first sampling unit 404 converts it to 1, and if the state of the control signal is LOW, it converts it to 0. Accordingly, the control signal sampled at the time point 602 is converted into 16-bit sampled control signals SS01 to SS16, that is, '1111 1110 1110 1111', as shown in FIG. 7 . The first sampling unit 404 transfers each of the control signals SS01 to SS16 sampled in this way to the serialization unit 406 .

Next, the first sampling unit samples each of the control signals CS01 to CS16 input at the time point 604 according to the cycle of the clock signal CLK. In FIG. 6 , the state of each of the control signals CS01 to CS16 is as follows when viewed with reference to the time point 604 .

CS01: HIGH

CS02: LOW

CS03: HIGH

CS04: HIGH

CS05: HIGH

CS06: LOW

CS07: HIGH

CS08: LOW

CS09: HIGH

CS10: HIGH

CS11: HIGH

CS12: LOW

CS13: HIGH

CS14: LOW

CS15: HIGH

CS16: LOW

The first sampling unit 404 converts the state of each of the control signals CS01 to CS16 sampled as above into a digital value. That is, the first sampling unit 404 converts the control signal to 1 when the state of the control signal is HIGH, and converts it to 0 when the state of the control signal is LOW. Accordingly, the control signal sampled at the time point 604 is converted into 16-bit sampled control signals SS01 to SS16, that is, '1011 1010 1110 1010', as shown in FIG. 8 . The first sampling unit 404 transfers each of the control signals SS01 to SS16 sampled in this way to the serialization unit 406 .

Next, the serialization unit 406 generates a serial data sequence SDS by using the sampled control signals SS01 to SS16 supplied from the first sampling unit 404 . As shown in [Table 1] below, the serial data sequence (SDS) may include a sequence start field, a control signal field, and a sequence end field.

Referring to [Table 1], the sequence start field is a field for indicating that one serial data sequence (SDS) starts, and always has a predetermined value. For example, as shown in [Table 1], the serializer 406 records the sequence start field of the new serial data sequence SDS as '1111'. In the present embodiment, it is described that the sequence start field is composed of 4 bits and the field value is '1111'. However, the number of bits and the field value of the sequence start field may vary depending on the embodiment.

Next, the previously sampled control signals SS01 to SS16 supplied from the first sampling unit 404 are recorded in the control signal field. That is, as described above, the control signal '1111 1110 1110 1111' or '1011 1010 1110 1010' sampled at the time point 602 is recorded in the control signal field as it is. In the present embodiment, the number of bits of the control signal field is set to 16, but the number of bits of the control signal field may vary according to the number of control signals generated by the control signal generator 402 .

The sequence end field is a field for indicating that one serial data sequence (SDS) is ended, and always has a predetermined value. For example, as shown in [Table 1], the serializer 406 records the sequence end field of the new serial data sequence SDS as '0000'. In the present embodiment, it is described that the sequence end field consists of 4 bits and the field value is '0000'. However, the number of bits and the field value of the sequence end field may vary depending on the embodiment.

The serializer 406 generates a serial data sequence SDS having the above configuration for each time point 602 , 604 . In this embodiment, each serial data sequence (SDS) composed of a total of 24 bits is continuously generated. The serial data sequence SDS generated as described above is sequentially output through the serial data sequence output pin S_OUT provided in the timing controller 120 .

As described above, the serial data sequence SDS output through the serial data sequence output pin S_OUT is inputted through the serial data sequence output pin S_IN provided in the level shifter 135 to the second sampling unit 502 . is transmitted

The second sampling unit 502 generates sampled control signals DS01 to DS16 by sampling each serial data sequence SDS sequentially input. The parallelization unit 504 generates parallelized control signals PS01 to PS16 by using the control signals DS01 to DS16 sampled by the second sampling unit 502 .

9 to 11 are diagrams for explaining a process of a level shifter generating a parallelized control signal using a serial data sequence provided from a timing controller according to an embodiment of the present invention.

First, referring to FIG. 9 , the second sampling unit 502 receives the serial data sequence generated by the timing controller 120 at the time point 602 , that is, '1111 1111 1110 1110 1111 0000' and the clock signal CLK. get input The second sampling unit 502 starts sampling the input serial data sequence according to the clock signal CLK. At this time, the second sampling unit 502 samples and outputs '1111 1110 1110 1111', which is a value excluding the sequence start field value, that is, '1111' and the sequence end field value, that is, '0000'.

Since the embodiment of FIG. 9 assumes that there is no sampled data in the previous section of the section in which the sampling of the serial data sequence '1111 1111 1110 1110 1111 0000' is performed, the sampled data and the parallelized control signals PS01 to PS16 ) are all shown as non-existent.

When sampling for the serial data sequence '1111 1111 1110 1110 1111 0000' is finished, the second sampling unit 502 provides a sampled control signal, that is, '1111 1110 1110 1111' to the parallelization unit 504, and then Sampling is performed on the serial data sequence, that is, '1111 1011 1010 1110 1010 0000', which is the serial data sequence generated at the time point 604 .

As shown in FIG. 10 , data '1111 1110 1110 1111' sampled by the second sampling unit 502 is provided to the parallelization unit 504, and the parallelization unit 504 is parallelized based on the data. '1111 1110 1110 1111', which is the control signals PS01 to PS16, is generated and provided to the gate control signal generator 506 . The gate control signal generator 506 receives the parallelized control signals PS01 to PS16 provided from the parallelization unit 504 '1111 1110 1110 1111' and the power supply voltage input pins (VGH, VGL) from the power supply unit (not shown). A gate control signal is generated using the power supply voltage supplied through the

Meanwhile, in the section shown in FIG. 10 , the second sampling unit 502 performs sampling on '1111 1011 1010 1110 1010 0000', which is the serial data sequence generated at the time point 604 , and performs sampling on the sequence start field value of '1111'. and '1011 1010 1110 1010', which is a field value excluding '0000', which is a sequence end field value, is sampled. 11 illustrates the sampled data '1011 1010 1110 1010'.

The parallelization unit 504 generates '1011 1010 1110 1010' which are parallelized control signals PS01 to PS16 based on the sampled data '1011 1010 1110 1010' provided from the second sampling unit 502 . The parallelization unit 504 supplies the generated parallelized control signals PS01 to PS16 to the gate control signal generation unit 506 . The gate control signal generator 506 receives '1011 1010 1110 1010' which is the parallelized control signals PS01 to PS16 provided from the parallelization unit 504 and the power voltage input pins (VGH, VGL) from the power supply unit (not shown). A gate control signal is generated using the power supply voltage supplied through the

For those of ordinary skill in the art to which the present invention pertains, various substitutions, modifications and changes are possible within the scope of the present invention without departing from the technical spirit of the present invention. is not limited by

Claims (7)

a display panel for displaying an image;
a gate driver supplying a gate signal to a gate line of the display panel;
a level shifter supplying a gate control signal for generating the gate signal to the gate driver;
a timing controller for supplying a serial data sequence for generating the gate control signal to the level shifter;
The timing control
a control signal generator generating a plurality of control signals;
a first sampling unit receiving the plurality of control signals and a clock signal input in parallel, and sampling the plurality of control signals according to a cycle of the clock signal; and
a serializer configured to generate the serial data sequence by including a sequence start field value and a sequence end field value in the sampled control signal;
the level shifter
a second sampling unit receiving the clock signal and the serial data sequence, and sampling the plurality of control signals excluding the sequence start field value and the sequence end field value from the serial data sequence according to the clock signal;
a parallelizer for parallelizing the sampled control signal; and
and a gate control signal generator configured to generate the gate control signal by using the parallelized control signal.
display device.
According to claim 1,
The timing control
Generating the serial data sequence by serializing a plurality of control signals input in parallel
display device.
delete According to claim 1,
The serial data sequence is
sequence start field, control signal field, sequence end field
display device.
According to claim 1,
The level shifter
parallelizing the serial data sequence to generate the gate control signal
display device.
delete According to claim 1,
the timing controller generates the serial data sequence based on the clock signal;
The level shifter generates the gate control signal from the serial data sequence based on the clock signal.
display device.

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