KR102433782B1 - 명령 패킷들을 위한 패리티 - Google Patents

명령 패킷들을 위한 패리티 Download PDF

Info

Publication number
KR102433782B1
KR102433782B1 KR1020187037143A KR20187037143A KR102433782B1 KR 102433782 B1 KR102433782 B1 KR 102433782B1 KR 1020187037143 A KR1020187037143 A KR 1020187037143A KR 20187037143 A KR20187037143 A KR 20187037143A KR 102433782 B1 KR102433782 B1 KR 102433782B1
Authority
KR
South Korea
Prior art keywords
parity
packet
command packet
instruction
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020187037143A
Other languages
English (en)
Korean (ko)
Other versions
KR20190021247A (ko
Inventor
에리히 제임스 플론드케
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20190021247A publication Critical patent/KR20190021247A/ko
Application granted granted Critical
Publication of KR102433782B1 publication Critical patent/KR102433782B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Detection And Correction Of Errors (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
KR1020187037143A 2016-06-24 2017-06-02 명령 패킷들을 위한 패리티 Active KR102433782B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/192,981 2016-06-24
US15/192,981 US10108487B2 (en) 2016-06-24 2016-06-24 Parity for instruction packets
PCT/US2017/035713 WO2017222784A1 (en) 2016-06-24 2017-06-02 Parity for instruction packets

Publications (2)

Publication Number Publication Date
KR20190021247A KR20190021247A (ko) 2019-03-05
KR102433782B1 true KR102433782B1 (ko) 2022-08-17

Family

ID=59067918

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020187037143A Active KR102433782B1 (ko) 2016-06-24 2017-06-02 명령 패킷들을 위한 패리티

Country Status (7)

Country Link
US (1) US10108487B2 (enExample)
EP (1) EP3475823B1 (enExample)
JP (1) JP6943890B2 (enExample)
KR (1) KR102433782B1 (enExample)
CN (1) CN109313594B (enExample)
SG (1) SG11201810111UA (enExample)
WO (1) WO2017222784A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10606587B2 (en) * 2016-08-24 2020-03-31 Micron Technology, Inc. Apparatus and methods related to microcode instructions indicating instruction types
CN115081429B (zh) * 2022-07-07 2024-10-22 北京微纳星空科技股份有限公司 一种指令校验方法、装置、设备和存储介质
US12399766B2 (en) 2023-01-12 2025-08-26 Nxp Usa, Inc. Central processing unit system and method with improved self-checking
US12613768B2 (en) * 2023-12-27 2026-04-28 Nxp Usa, Inc. System and method of checking integrity of an instruction decoder of a processing system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238168A (ja) * 2008-03-28 2009-10-15 Mitsubishi Electric Corp マイクロプロセッサ
US20110307961A1 (en) * 2009-03-02 2011-12-15 Nxp B.V. Software protection
US20130036294A1 (en) 2011-08-05 2013-02-07 Cisco Technology, Inc. System and method for instruction sets with run-time consistency check

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005405A (en) 1975-05-07 1977-01-25 Data General Corporation Error detection and correction in data processing systems
US6041430A (en) * 1997-11-03 2000-03-21 Sun Microsystems, Inc. Error detection and correction code for data and check code fields
US7013454B2 (en) 1999-02-22 2006-03-14 Sun Microsystems, Inc. Thread suspension system and method using trapping instructions
US6738892B1 (en) 1999-10-20 2004-05-18 Transmeta Corporation Use of enable bits to control execution of selected instructions
GB2362733B (en) * 2000-05-25 2002-02-27 Siroyan Ltd Processors having compressed instructions.
US6934903B1 (en) * 2001-12-17 2005-08-23 Advanced Micro Devices, Inc. Using microcode to correct ECC errors in a processor
US7240277B2 (en) 2003-09-26 2007-07-03 Texas Instruments Incorporated Memory error detection reporting
US7370230B1 (en) 2004-01-08 2008-05-06 Maxtor Corporation Methods and structure for error correction in a processor pipeline
US7302619B1 (en) * 2004-07-06 2007-11-27 Mindspeed Technologies, Inc. Error correction in a cache memory
TW200604934A (en) * 2004-07-16 2006-02-01 Benq Corp Firmware management system and method thereof
US7447948B2 (en) * 2005-11-21 2008-11-04 Intel Corporation ECC coding for high speed implementation
US20080256419A1 (en) 2007-04-13 2008-10-16 Microchip Technology Incorporated Configurable Split Storage of Error Detecting and Correcting Codes
US8135927B2 (en) * 2007-09-28 2012-03-13 International Business Machines Corporation Structure for cache function overloading
US8201067B2 (en) * 2008-02-25 2012-06-12 International Business Machines Corporation Processor error checking for instruction data
US8281111B2 (en) * 2008-09-23 2012-10-02 Qualcomm Incorporated System and method to execute a linear feedback-shift instruction
US8904115B2 (en) 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US8839069B2 (en) * 2011-04-08 2014-09-16 Micron Technology, Inc. Encoding and decoding techniques using low-density parity check codes
US20140089755A1 (en) * 2012-09-27 2014-03-27 Shveta KANTAMSETTI Reliability enhancements for high speed memory - parity protection on command/address and ecc protection on data
US20140244932A1 (en) * 2013-02-27 2014-08-28 Advanced Micro Devices, Inc. Method and apparatus for caching and indexing victim pre-decode information
CN103279329B (zh) * 2013-05-08 2015-07-29 中国人民解放军国防科学技术大学 支持同步edac校验的高效取指流水线
CN103645964B (zh) * 2013-11-22 2017-05-10 中国电子科技集团公司第三十二研究所 嵌入式处理器的高速缓存容错机制

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238168A (ja) * 2008-03-28 2009-10-15 Mitsubishi Electric Corp マイクロプロセッサ
US20110307961A1 (en) * 2009-03-02 2011-12-15 Nxp B.V. Software protection
US20130036294A1 (en) 2011-08-05 2013-02-07 Cisco Technology, Inc. System and method for instruction sets with run-time consistency check

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
An Architectural framework for support heterogeneous instructions set architectures, Silberman et al. IEEE, 1993.6.

Also Published As

Publication number Publication date
US20170371739A1 (en) 2017-12-28
WO2017222784A1 (en) 2017-12-28
EP3475823B1 (en) 2022-04-20
CN109313594B (zh) 2022-06-17
JP2019519858A (ja) 2019-07-11
CN109313594A (zh) 2019-02-05
BR112018076279A8 (pt) 2023-01-31
US10108487B2 (en) 2018-10-23
BR112018076279A2 (pt) 2019-03-26
EP3475823A1 (en) 2019-05-01
KR20190021247A (ko) 2019-03-05
SG11201810111UA (en) 2019-01-30
JP6943890B2 (ja) 2021-10-06

Similar Documents

Publication Publication Date Title
KR102242872B1 (ko) 비휘발성 메모리 내의 복구 알고리즘
KR20160033722A (ko) 비휘발성 메모리에서의 오류 정정
EP3475823B1 (en) Parity for instruction packets
US10162635B2 (en) Confidence-driven selective predication of processor instructions
TW202227971A (zh) 處理器、用以保護處理器的裝置、以及用以保護處理器的方法
US8281111B2 (en) System and method to execute a linear feedback-shift instruction
US20170046158A1 (en) Determining prefetch instructions based on instruction encoding
KR20140073553A (ko) Ｆｉｆｏ 로드 명령
US20190004805A1 (en) Multi-tagged branch prediction table
US9104403B2 (en) Data processing system having selective redundancy and method therefor
US20190004806A1 (en) Branch prediction for fixed direction branch instructions
KR20180039077A (ko) 전력 효율적 페치 적응
WO2013036950A1 (en) Instruction packet including multiple instructions having a common destination
US9389854B2 (en) Add-compare-select instruction
JP6189866B2 (ja) プロセッサモードを切り替えるための、呼び出される関数のアドレスの最下位ビットの使用
EP3198400B1 (en) Dependency-prediction of instructions
JP2019519858A5 (enExample)
CN102822794B (zh) 处理阶层式极长指令包的系统和方法
US20130283023A1 (en) Bimodal Compare Predictor Encoded In Each Compare Instruction
US10114685B2 (en) System and method for error detection of executed program code employing compressed instruction signatures
HK1261188A1 (en) Parity for instruction packets
HK1261188B (en) Parity for instruction packets
CN117348936A (zh) 处理器、取指方法和计算机系统
BR112018076279B1 (pt) Paridade para pacotes de instrução

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 5