JP6943890B2 - 命令パケットのためのパリティ - Google Patents

命令パケットのためのパリティ Download PDF

Info

Publication number
JP6943890B2
JP6943890B2 JP2018566476A JP2018566476A JP6943890B2 JP 6943890 B2 JP6943890 B2 JP 6943890B2 JP 2018566476 A JP2018566476 A JP 2018566476A JP 2018566476 A JP2018566476 A JP 2018566476A JP 6943890 B2 JP6943890 B2 JP 6943890B2
Authority
JP
Japan
Prior art keywords
parity
instruction
packet
instruction packet
assembler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018566476A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019519858A5 (enExample
JP2019519858A (ja
Inventor
エリック・ジェームズ・プロンドケ
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2019519858A publication Critical patent/JP2019519858A/ja
Publication of JP2019519858A5 publication Critical patent/JP2019519858A5/ja
Application granted granted Critical
Publication of JP6943890B2 publication Critical patent/JP6943890B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
  • Error Detection And Correction (AREA)
JP2018566476A 2016-06-24 2017-06-02 命令パケットのためのパリティ Active JP6943890B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/192,981 2016-06-24
US15/192,981 US10108487B2 (en) 2016-06-24 2016-06-24 Parity for instruction packets
PCT/US2017/035713 WO2017222784A1 (en) 2016-06-24 2017-06-02 Parity for instruction packets

Publications (3)

Publication Number Publication Date
JP2019519858A JP2019519858A (ja) 2019-07-11
JP2019519858A5 JP2019519858A5 (enExample) 2020-06-25
JP6943890B2 true JP6943890B2 (ja) 2021-10-06

Family

ID=59067918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018566476A Active JP6943890B2 (ja) 2016-06-24 2017-06-02 命令パケットのためのパリティ

Country Status (7)

Country Link
US (1) US10108487B2 (enExample)
EP (1) EP3475823B1 (enExample)
JP (1) JP6943890B2 (enExample)
KR (1) KR102433782B1 (enExample)
CN (1) CN109313594B (enExample)
SG (1) SG11201810111UA (enExample)
WO (1) WO2017222784A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10606587B2 (en) 2016-08-24 2020-03-31 Micron Technology, Inc. Apparatus and methods related to microcode instructions indicating instruction types
CN115081429B (zh) * 2022-07-07 2024-10-22 北京微纳星空科技股份有限公司 一种指令校验方法、装置、设备和存储介质
US12399766B2 (en) * 2023-01-12 2025-08-26 Nxp Usa, Inc. Central processing unit system and method with improved self-checking
US20250217230A1 (en) * 2023-12-27 2025-07-03 Nxp Usa, Inc. System and method of checking integrity of an instruction decoder of a processing system

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005405A (en) 1975-05-07 1977-01-25 Data General Corporation Error detection and correction in data processing systems
US6041430A (en) * 1997-11-03 2000-03-21 Sun Microsystems, Inc. Error detection and correction code for data and check code fields
US7013454B2 (en) 1999-02-22 2006-03-14 Sun Microsystems, Inc. Thread suspension system and method using trapping instructions
US6738892B1 (en) 1999-10-20 2004-05-18 Transmeta Corporation Use of enable bits to control execution of selected instructions
GB2362733B (en) * 2000-05-25 2002-02-27 Siroyan Ltd Processors having compressed instructions.
US6934903B1 (en) * 2001-12-17 2005-08-23 Advanced Micro Devices, Inc. Using microcode to correct ECC errors in a processor
US7240277B2 (en) 2003-09-26 2007-07-03 Texas Instruments Incorporated Memory error detection reporting
US7370230B1 (en) 2004-01-08 2008-05-06 Maxtor Corporation Methods and structure for error correction in a processor pipeline
US7302619B1 (en) * 2004-07-06 2007-11-27 Mindspeed Technologies, Inc. Error correction in a cache memory
TW200604934A (en) * 2004-07-16 2006-02-01 Benq Corp Firmware management system and method thereof
US7447948B2 (en) * 2005-11-21 2008-11-04 Intel Corporation ECC coding for high speed implementation
US20080256419A1 (en) 2007-04-13 2008-10-16 Microchip Technology Incorporated Configurable Split Storage of Error Detecting and Correcting Codes
US8135927B2 (en) * 2007-09-28 2012-03-13 International Business Machines Corporation Structure for cache function overloading
US8201067B2 (en) * 2008-02-25 2012-06-12 International Business Machines Corporation Processor error checking for instruction data
JP2009238168A (ja) * 2008-03-28 2009-10-15 Mitsubishi Electric Corp マイクロプロセッサ
US8281111B2 (en) * 2008-09-23 2012-10-02 Qualcomm Incorporated System and method to execute a linear feedback-shift instruction
CN102341806B (zh) * 2009-03-02 2014-09-24 Nxp股份有限公司 软件保护
US8904115B2 (en) 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US8839069B2 (en) * 2011-04-08 2014-09-16 Micron Technology, Inc. Encoding and decoding techniques using low-density parity check codes
US9176739B2 (en) * 2011-08-05 2015-11-03 Cisco Technology, Inc. System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions
US20140089755A1 (en) * 2012-09-27 2014-03-27 Shveta KANTAMSETTI Reliability enhancements for high speed memory - parity protection on command/address and ecc protection on data
US20140244932A1 (en) * 2013-02-27 2014-08-28 Advanced Micro Devices, Inc. Method and apparatus for caching and indexing victim pre-decode information
CN103279329B (zh) * 2013-05-08 2015-07-29 中国人民解放军国防科学技术大学 支持同步edac校验的高效取指流水线
CN103645964B (zh) * 2013-11-22 2017-05-10 中国电子科技集团公司第三十二研究所 嵌入式处理器的高速缓存容错机制

Also Published As

Publication number Publication date
CN109313594A (zh) 2019-02-05
KR20190021247A (ko) 2019-03-05
CN109313594B (zh) 2022-06-17
BR112018076279A2 (pt) 2019-03-26
KR102433782B1 (ko) 2022-08-17
SG11201810111UA (en) 2019-01-30
US20170371739A1 (en) 2017-12-28
BR112018076279A8 (pt) 2023-01-31
EP3475823A1 (en) 2019-05-01
JP2019519858A (ja) 2019-07-11
US10108487B2 (en) 2018-10-23
WO2017222784A1 (en) 2017-12-28
EP3475823B1 (en) 2022-04-20

Similar Documents

Publication Publication Date Title
KR101767018B1 (ko) 비휘발성 메모리에서의 오류 정정
US9652321B2 (en) Recovery algorithm in non-volatile memory
JP6943890B2 (ja) 命令パケットのためのパリティ
US20170192843A1 (en) Error counters on a memory device
JP2009181163A (ja) マイクロプロセッサならびにビット・ベクタのエンコーディング方法およびビット・ベクタの生成方法
CN107851023A (zh) 基于指令编码确定预提取指令
US20190004805A1 (en) Multi-tagged branch prediction table
CN110741345A (zh) 对固定方向分支指令的分支预测
JP6189866B2 (ja) プロセッサモードを切り替えるための、呼び出される関数のアドレスの最下位ビットの使用
CN101911011B (zh) 确定表内的元素的地址的系统和方法
JP2011257966A (ja) キャッシュ装置及び情報処理装置
JP2019519858A5 (enExample)
EP3198400B1 (en) Dependency-prediction of instructions
CN102822794B (zh) 处理阶层式极长指令包的系统和方法
US8069376B2 (en) On-line testing for decode logic
HK1261188A1 (en) Parity for instruction packets
HK1261188B (en) Parity for instruction packets
JP5843804B2 (ja) 演算装置およびエラー処理方法
BR112018076279B1 (pt) Paridade para pacotes de instrução
JP2010140132A (ja) メモリシステム及びメモリコントローラ
TW202418068A (zh) 處理器及自處理器偵測軟錯誤的方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181226

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200511

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200511

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210414

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210426

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210720

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210810

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210909

R150 Certificate of patent or registration of utility model

Ref document number: 6943890

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250