KR102430795B1 - Display device and method for driving the same - Google Patents

Abstract

An embodiment of the present invention relates to a display device capable of rapidly discharging a power supply voltage when a display panel is turned off, thereby reducing a time for turning off a display panel, thereby preventing a screen transient phenomenon. The display device according to an exemplary embodiment of the present invention may connect a discharge unit including a discharge circuit and a discharge control circuit to a power voltage line to discharge the power voltage to a ground voltage when the display panel is turned off. The discharge control circuit controls the discharge circuit to discharge the power supply voltage to the ground voltage only when the display panel is turned off. A driving signal may be generated using a difference voltage between the gamma voltage input to the discharge control circuit and the reference voltage. Further, it is possible to supply a driving signal from the discharge control circuit to the discharge circuit only when the power supply voltage is reduced.

Description

Display device and driving method thereof

Embodiments of the present invention relate to a display device and a driving method thereof.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display, a plasma display panel, and an organic light emitting display device Various flat panel display devices such as light emitting display devices are being used.

The display device includes a display panel and a circuit board. The display panel includes data lines, gate lines, and pixels connected to the data lines and gate lines.

The circuit board may be a source printed circuit board (PCB). Flexible films may be attached to the circuit board. A power line disposed on the circuit board supplies a power voltage of 24V when the display panel is turned on. A gamma line disposed on the circuit board supplies a gamma voltage of 12V when the display panel is turned on. When the display panel is turned off, the power supply voltage is first discharged to 0V, and then the gamma voltage is discharged to 0V.

There is no separate discharge path in the power line. When the display panel is turned off, the power voltage is discharged through the display panel. The discharge rate varies depending on the state of the display panel when the display panel is turned off. In particular, when the display panel has a black or dark screen and low gray, the discharge rate is slow. Accordingly, when the power supply voltage is slowly converted to 0V due to an increase in the time to turn off the display panel, the gamma voltage is converted to 0V before the power voltage is converted to 0V, and light is emitted momentarily before the display panel is turned off. There is also a problem that the phenomenon occurs with the screen.

SUMMARY OF THE INVENTION An aspect of the present invention is to provide a display device capable of rapidly discharging a power supply voltage when a display panel is turned off to prevent a screen transient from occurring, and a method of driving the same.

According to an embodiment of the present invention, when the display panel on which the power line is disposed, the power supply supplying the power voltage of the first logic level to the display panel, and the display panel are switched from the turn-on state to the turn-off state, the power supply voltage is converted to a ground voltage. A discharge unit for discharging to

An embodiment of the present invention includes a discharge unit for discharging a power supply voltage to a ground voltage when the display panel is switched from a turn-on state to a turn-off state. Accordingly, when the display panel is switched to the turn-off state, the power supply voltage can be rapidly discharged to the ground voltage. Accordingly, it is possible to prevent a screen transient phenomenon in which the image of the display panel is temporarily brightened and then turned off because the power voltage is not discharged.

1 is a block diagram of a display device according to an exemplary embodiment;
2 is a circuit diagram illustrating a display panel, a source drive IC, a flexible film, a timing control circuit, a power supply unit, a discharge unit, a circuit board, and a power line of a display device according to an embodiment of the present invention;
FIG. 3 is an exemplary view showing an example of the pixel of FIG. 1;
4 is a block diagram illustrating a power supply unit and a discharge unit according to an embodiment of the present invention.
FIG. 5 is a circuit diagram showing the discharge unit of FIG. 4 in detail;
6 is a circuit diagram illustrating the op-amp of FIG. 5 in detail.
7 is a waveform diagram illustrating a power supply voltage, a gamma voltage, and a reference voltage according to an embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than the range in which the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a display device according to an exemplary embodiment. Referring to FIG. 1 , a display device according to an exemplary embodiment of the present invention includes a display panel 10 , a gate driver 20 , a data driver 30 , a timing control circuit 40 , a power supply unit 50 , and a discharge unit. (60) is provided.

The display device according to the embodiment of the present invention may include any display device that supplies data voltages to the pixels P through line sequential scanning in which gate signals are sequentially supplied to the gate lines G1 to Gn. For example, a display device according to an embodiment of the present invention includes a liquid crystal display, an organic light emitting display, a field emission display, and an electrophoresis display. display) can be implemented as any one of them. Hereinafter, a case in which the display device according to an embodiment of the present invention is an organic light emitting display device will be mainly described.

The display panel 10 includes an upper substrate and a lower substrate. Data lines D1 to Dm, m is a positive integer equal to or greater than 2), gate lines G1 to Gn, n is a positive integer greater than or equal to 2), and pixels P are provided on the lower substrate. The pixels P may be provided on the display area PA of the lower substrate. The pixel P may be connected to any one of the data lines D1 to Dm and to any one of the gate lines G1 to Gn. Accordingly, the pixel P receives the data voltage of the data line when the gate signal is supplied to the gate line, and emits light with a predetermined brightness according to the supplied data voltage.

When the display device is implemented as an organic light emitting diode display, each of the pixels P includes an organic light emitting diode OLED, a scan transistor ST, a driving transistor DT, and a storage capacitor Cst as shown in FIG. 3 . can do. The scan transistor ST supplies the data voltage of the j-th data line Dj to the gate electrode of the driving transistor DT in response to the gate signal of the k-th gate line Gk. The driving transistor DT controls a driving current flowing from the high potential voltage line VDDL to the organic light emitting diode OLED according to a data voltage supplied to its gate electrode. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL, and emits light with a predetermined brightness according to the driving current. The storage capacitor Cst may be provided between the gate electrode and the source electrode of the driving transistor DT to maintain a constant voltage difference between the gate electrode and the source electrode of the driving transistor DT.

The display panel 10 receives the power supply voltage ELVDD from the discharge unit 60 and the power reference voltage ELVSS from the power supply unit 50 . The power supply voltage ELVDD is a supply voltage for driving the display panel, and maintains the first logic level L1 when the display panel 10 is turned on. For example, in a large organic light emitting diode display, the first logic level L1 may be 24V. When the display panel 10 is turned off, the power supply voltage ELVDD maintains the ground voltage GND. Accordingly, when the display panel 10 is switched from the turn-on state to the turn-off state, the power supply voltage ELVDD is discharged from the first logic level L1 to the ground voltage GND. The power reference voltage ELVSS is a supply voltage for driving the display panel 10 , and may be controlled by the power supply unit 50 .

The gate driver 20 receives the gate control signal GCS from the timing control circuit 40 , generates gate signals according to the gate control signal GCS and supplies them to the gate lines G1 to Gn.

The data driver 30 receives digital video data DATA and a data control signal DCS from the timing control circuit 40 , and receives gamma voltages GMA from the power supply 50 . The data driver 30 converts the digital video data DATA into analog data voltages according to the data control signal DCS and the gamma voltages GMA and supplies the data voltages to the data lines D1 to Dm. The gamma voltages GMA control the size of each of the data voltages to be supplied to the data lines. The gamma voltages GMA may have a third logic level L3 smaller than the first logic level L1 .

The timing control circuit 40 receives digital video data DATA and a timing signal from an external system board (not shown), and inputs a gate high voltage VGH and a gate low voltage VGL from the power supply 50 . receive The timing control circuit 40 includes a gate control signal GCS and a data driver 30 for controlling the operation timing of the gate driver 20 based on the timing signal, the gate high voltage VGH, and the gate low voltage VGL. ) to generate a data control signal DCS for controlling the operation timing. The timing control circuit 40 supplies the gate control signal GCS to the gate driver 20 , and supplies digital video data DATA and a source control signal DCS to the data driver 30 .

The power supply unit 50 generates a power supply voltage ELVDD, a power reference voltage ELVSS, a gate high voltage VGH, a gate low voltage VGL, and a gamma voltage GMA. The power supply unit 50 supplies the power voltage ELVDD to the discharge unit 60 . The power supply unit 50 supplies the power reference voltage ELVSS to the display panel 10 . The power supply unit 50 supplies the gate high voltage and the gate low voltage VGH and VGL to the timing control circuit 40 . The power supply unit 50 supplies the gamma voltages GMA to the data driver 30 .

The discharge unit 60 receives the power supply voltage ELVDD of the first logic level L1 from the power supply unit 50 . The discharge unit 60 outputs the power supply voltage ELVDD of the first logic level L1 to the power line ELVDDL when the display panel 10 is turned on. The discharge unit 60 discharges the power supply voltage ELVDD to the ground voltage GND when the display panel 10 is switched from the turn-on state to the turn-off state. Accordingly, when the display panel 10 is switched to the turn-off state, the power supply voltage ELVDD may be rapidly discharged to the ground voltage GND. Accordingly, it is possible to prevent a screen transient phenomenon in which the image of the display panel 10 is temporarily brightened and then turned off because the power voltage ELVDD is not discharged.

2 illustrates a display panel 10 , a source drive IC 31 , a flexible film 32 , a timing control circuit 40 , a power supply unit 50 , and a discharge unit 60 of a display device according to an exemplary embodiment of the present invention. ), the circuit board 70, and a circuit diagram showing the power line ELVDDL. In FIG. 2 , gate lines G1 to Gn, data lines D1 to Dm, and pixels P are omitted for convenience of description.

The data driver 30 may include a plurality of source drive integrated circuits (hereinafter referred to as “ICs”) 31 . Each of the source drive ICs 31 may be mounted on the flexible film 32 .

The circuit board 70 may be connected to the display panel 10 through the flexible films 32 . The circuit board 70 may mount the timing control circuit 40 , the power supply unit 50 , and the discharge unit 60 . The circuit board 70 may be a source printed circuit board (PCB). Alternatively, the circuit board 70 may be a flexible printed circuit board (FPCB).

The power line ELVDDL connects the display panel 10 , the power supply unit 50 , and the discharge unit 60 . A plurality of power lines ELVDDL may be provided on the display panel 10 and the circuit board 70 , and the power lines ELVDDL and the circuit board provided on the display panel 10 through the flexible films 32 . A power supply line ELVDDL provided on 70 may be connected. The power line ELVDDL is generated by the power supply unit 50 and supplies the power voltage ELVDD via the discharge unit 60 to the display panel 10 . The power line ELVDDL supplies the power supply voltage ELVDD of the first logic level L1 when the display panel 10 is turned on.

4 is a block diagram illustrating a power supply unit 50 and a discharge unit 60 according to an embodiment of the present invention. The discharge unit 60 includes a discharge control circuit 200 and a discharge circuit 210 .

The power supply unit 50 supplies the power voltage ELVDD to the discharge control circuit 200 and the discharge circuit 210 , and supplies the input voltage and the reference voltage REF to the discharge control circuit 200 . When the display panel 10 is turned on, the reference voltage REF may have the same logic level as the input voltage. The input voltage may be any one of gamma voltages GMA supplied to the data driver 30 to generate data voltages. In this case, the reference voltage REF may have the same third logic level L3 as the gamma voltage GMA. Accordingly, the reference voltage REF can be supplied from the power supply unit 50 without adding a separate circuit or a level shifter to the power supply unit 50 that generates the gamma voltage GMA.

The discharge control circuit 200 receives the power supply voltage ELVDD, the gamma voltage GMA, and the reference voltage REF from the power supply unit 50 . The discharge control circuit 200 generates a driving signal Vout using the gamma voltage GMA and the reference voltage REF. The discharge control circuit 200 outputs the driving signal Vout when the power supply voltage ELVDD is lower than the second logic level L2 which is lower than the first logic level L1 . Accordingly, the driving signal Vout may be output to the discharge circuit 210 only when the display panel 10 is switched from the turn-on state to the turn-off state.

The discharge circuit 210 receives the driving signal Vout from the discharge control circuit 200 . When the driving signal Vout is input, the discharge circuit 210 connects the power line ELVDDL to the ground to discharge the power voltage ELVDD to the ground voltage GND. Accordingly, when the display panel is switched from the turn-on state to the turn-off state, the power supply voltage ELVDD can be rapidly discharged to the ground voltage GND.

5 is a circuit diagram illustrating the discharge unit 60 in detail. The discharge unit 60 includes a discharge control circuit 200 and a discharge circuit 210 .

The discharge circuit 210 may include a first switching unit S1 and a first resistor R1.

The first switching unit S1 is connected to the discharge control circuit 200 . The first switching unit S1 is turned on when receiving the driving signal Vout from the discharge control circuit 200 . The first switching unit S1 may be implemented using an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, the MOSFET may be turned on by receiving the driving signal Vout through the gate of the MOSFET. Accordingly, only when the driving signal Vout is input, the power supply line ELVDDL is connected to the ground to discharge the power supply voltage ELVDD.

The first resistor R1 is disposed between the power line ELVDDL and the first switching unit S1 . The first resistor R1 may control a rate at which the power supply voltage ELVDD is discharged when the power line ELVDDL is connected to the ground when the first switching unit S1 is turned on. To this end, the first resistor R1 may be a variable resistor.

The discharge control circuit 200 includes a second switching unit S2 and an operational amplifier 201 .

The second switching unit S2 is connected to the power line ELVDDL through the inverter line INVL including the inverter INV. The second switching unit S2 is turned on when the power supply voltage ELVDD is lower than the second logic level L2. The second switching unit S2 may be implemented using an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, the inverted power supply voltage INV_ELVDD may be input to the gate of the MOSFET. Accordingly, when the display panel 10 is switched from turn-on to turn-off, as the power supply voltage ELVDD decreases, the inverted power supply voltage INV_ELVDD rises, so that the MOSFET may be turned on.

The operational amplifier 201 receives a reference voltage REF and a gamma voltage GMA, and outputs a driving signal Vout according to a difference voltage between the reference voltage REF and the gamma voltage GMA. The operational amplifier 201 has a positive input, a negative input, and an output.

A reference voltage REF is input to the positive input part, and the positive input part and the operational amplifier 201 are connected by a reference line REFL. A gamma voltage GMA is input to the negative input unit, and the negative input unit and the op-amp 201 are connected by a gamma line GMAL. The driving signal Vout is output to the output unit, and the output unit is connected to the driving line DL.

As shown in FIG. 5 , when separate feedback resistors are not connected to the operational amplifier 201 , the reference voltage REF and the gamma voltage GMA input to the operational amplifier 201 and the driving output from the operational amplifier 201 . The relationship between the signal Vout is as shown in Equation (1).

In Equation 1, Gain means the voltage gain of the operational amplifier 201 itself. That is, the driving signal Vout is generated with a magnitude obtained by multiplying the voltage difference between the reference voltage REF and the gamma voltage GMA by the voltage gain of the op-amp itself. When the display panel 10 is in the turned-on state, the difference voltage between the reference voltage REF and the gamma voltage GMA is not generated, and thus the driving signal Vout is not generated. When the display panel 10 is switched from the turn-on state to the turn-off state, both the gamma voltage GMA and the reference voltage REF are discharged to the ground voltage GND. However, the timing at which the reference voltage REF starts to be discharged to the ground voltage GND is later than the gamma voltage GMA. Accordingly, a difference voltage between the reference voltage REF and the gamma voltage GMA may be generated, and a driving signal Vout may be generated. As the gamma voltage GMA decreases, the voltage level of the driving signal Vout increases. Accordingly, when the display panel 10, which is when the gamma voltage GMA is low, displays a low gray level, that is, a dark image, a driving signal Vout having a large voltage is applied to the first switching unit S1 to supply power. The voltage ELVDD can be rapidly discharged.

Alternatively, the operational amplifier 201 may be designed as an inverting amplifier having a feedback function by further including second and third resistors R2 and R3 as shown in FIG. 6 . An ideal operational amplifier 201 has a very large voltage gain and input resistance. Accordingly, there is no current flowing into the positive and negative inputs of the operational amplifier 201, and the voltages of the positive and negative inputs are the same. In the circuit of FIG. 6 , the relationship between the reference voltage REF and the gamma voltage GMA input to the operational amplifier 201 and the driving signal Vout output from the operational amplifier 201 is expressed by Equation (2).

When the display panel 10 is in the turned-on state, the difference voltage between the reference voltage REF and the gamma voltage GMA does not occur, so that the driving signal Vout having the same voltage as the reference voltage REF is generated. do. When the display panel 10 is switched from the turn-on state to the turn-off state, both the gamma voltage GMA and the reference voltage REF are discharged to the ground voltage GND. However, the timing at which the reference voltage REF starts to be discharged to the ground voltage GND is later than the gamma voltage GMA. Accordingly, a difference voltage between the reference voltage REF and the gamma voltage GMA is generated, and the magnitude of the driving signal Vout increases. As the gamma voltage GMA decreases, the voltage level of the driving signal Vout increases. Accordingly, when the display panel 10, which is when the gamma voltage GMA is low, displays a low gray level, that is, a dark image, a driving signal Vout having a large voltage is applied to the first switching unit S1 to supply power. The voltage ELVDD can be rapidly discharged.

Even when the driving signal Vout is generated, when the power voltage ELVDD is the first logic level L1 because the display panel 10 is turned on, the second switching unit S2 is turned off. The signal Vout is not output to the driving line DS. When the power supply voltage ELVDD is lower than the second logic level L2 lower than the first logic level L1 , the second switching unit S2 is turned on. When the second switching unit S2 is turned on, the driving signal Vout may be input to the first switching unit S1 through the driving line DL. Accordingly, the driving signal Vout may be supplied to the discharge circuit 210 only when the display panel 10 is switched from the turn-on state to the turn-off state.

7 is a waveform diagram illustrating a power supply voltage, a gamma voltage, and a reference voltage according to an embodiment of the present invention.

When the display panel 10 is switched from the turn-on state to the turn-off state, the power supply voltage ELVDD, the gamma voltage GMA, and the reference voltage REF all start to decrease. At this time, the discharge start timing T1 (hereinafter referred to as “first timing T1) of the power supply voltage ELVDD is greater than the discharge start timing T2 (hereinafter referred to as “second timing T2”) of the input voltage. fast. In particular, as shown in FIG. 7 , the gamma voltage GMA starts to be discharged when the power supply voltage ELVDD becomes lower than the second logic level L2 which is lower than the first logic level L1 . Accordingly, the power supply voltage ELVDD decreases faster than the input voltage, and the power supply voltage ELVDD is not discharged even after the input voltage is discharged, so that the display panel 10 temporarily brightens and turns off the screen transient phenomenon. can be prevented

The second timing T2 is later than the discharge start timing T3 of the reference voltage REF (hereinafter referred to as a “third timing T3 ). Accordingly, a differential voltage may be generated between the reference voltage REF and the input voltage, and the driving signal Vout may be generated between the second timing T2 and the third timing T3 .

The power supply voltage ELVDD starts to decrease at the first logic level L1. When the power supply voltage ELVDD becomes smaller than the second logic level L2 which is smaller than the first logic level L1 , the second switching unit S2 is turned on by the inverted power supply voltage INV_ELVDD to generate driving A signal Vout may be output. While the driving signal Vout is being output, the first switching unit S1 is turned on. Accordingly, the power supply voltage may be more rapidly discharged to the ground voltage GND through the discharge circuit 210 connecting the power line ELVDDL to the ground.

Hereinafter, a method of driving a display device according to an exemplary embodiment of the present invention will be described.

First, when the power supply voltage ELVDD is lower than the second logic level L2 which is lower than the first logic level L1 , the second switching unit S2 built in the discharge control circuit 200 is turned on. . The second switching unit S2 is connected to the power line ELVDDL through the inverter line INVL including the inverter INV. The second switching unit S2 is turned on when the power supply voltage ELVDD is lower than the second logic level L2. The second switching unit S2 may be implemented using an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, the inverted power supply voltage INV_ELVDD may be input to the gate of the MOSFET. Accordingly, when the display panel 10 is switched from turn-on to turn-off, as the power supply voltage ELVDD decreases, the inverted power supply voltage INV_ELVDD rises, so that the MOSFET may be turned on.

Second, the operational amplifier 201 built in the discharge control circuit 200 receives the reference voltage REF and the gamma voltage GMA, and according to the difference voltage between the reference voltage REF and the gamma voltage GMA, A driving signal Vout is output. The operational amplifier 201 has a positive input, a negative input, and an output. A reference voltage REF is input to the positive input part, and the positive input part and the operational amplifier 201 are connected by a reference line REFL. A gamma voltage GMA is input to the negative input unit, and the negative input unit and the op-amp 201 are connected by a gamma line GMAL. The driving signal Vout is output to the output unit, and the output unit is connected to the driving line DL.

When the display panel 10 is switched from the turn-on state to the turn-off state, both the gamma voltage GMA and the reference voltage REF are discharged to the ground voltage GND. However, the timing at which the reference voltage REF starts to be discharged to the ground voltage GND is later than the gamma voltage GMA. Accordingly, a difference voltage between the reference voltage REF and the gamma voltage GMA is generated, and the magnitude of the driving signal Vout increases. As the gamma voltage GMA decreases, the voltage level of the driving signal Vout increases. Accordingly, when the display panel 10, which is when the gamma voltage GMA is low, displays a low gray level, that is, a dark image, a driving signal Vout having a large voltage is applied to the first switching unit S1 to supply power. The voltage ELVDD can be rapidly discharged.

The discharge circuit 210 receives the driving signal Vout from the discharge control circuit 200 . The discharging circuit 210 may include a first switching unit S1 . The first switching unit S1 is connected to the discharge control circuit 200 . The first switching unit S1 is turned on when receiving the driving signal Vout from the discharge control circuit 200 . The first switching unit S1 may be implemented using an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, the MOSFET may be turned on by receiving the driving signal Vout through the gate of the MOSFET.

An embodiment of the present invention includes a discharge unit for discharging a power supply voltage to a ground voltage when the display panel is switched from a turn-on state to a turn-off state. Accordingly, when the display panel is switched to the turn-off state, the power supply voltage can be rapidly discharged to the ground voltage. Accordingly, it is possible to prevent a screen transient phenomenon in which the image of the display panel is temporarily brightened and then turned off because the power voltage is not discharged.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: gate driver
30: data driver 31: source drive IC
32: flexible film 40: timing control circuit
50: power supply unit 60: discharge unit
70: circuit board 200: discharge control circuit
201: operational amplifier 210: discharge circuit
DL: drive line ELVDDL: power line
GMAL: Gamma line REFL: Reference line
INV: Inverter INVL: Inverter Line
PA: display areas R1, R2, R3: first to third resistors
S1, S2: first and second switching units

Claims (10)

a display panel 10 on which a power line ELVDDL is disposed;
a power supply unit 50 for supplying a power supply voltage ELVDD of a first logic level L1 to the power line ELVDDL; and
and a discharge unit 60 for discharging the power supply voltage ELVDD to a ground voltage GND when the display panel 10 is switched from a turn-on state to a turn-off state;
The discharge unit 60,
When the power supply voltage ELVDD is lower than a second logic level L2 lower than the first logic level L1, the discharge control circuit 200 outputs a driving signal Vout according to the reference voltage REF and the input voltage. ); and
and a discharge circuit (210) connecting the power line (ELVDDL) to a ground when the driving signal (Vout) is input. delete According to claim 1, wherein the discharge circuit 210,
and a first switching unit (S1) for switching a connection between the power line (ELVDDL) and a ground according to the driving signal (Vout) from the discharge control circuit (200). According to claim 1, wherein the discharge control circuit 200,
an operational amplifier 201 that receives the reference voltage REF and the input voltage and outputs the driving signal Vout according to a difference voltage between the reference voltage REF and the input voltage;
a second switching unit (S2) connected between the operational amplifier (201) and the discharging circuit (210) and switching the supply of the driving signal (Vout) according to a voltage input to a control terminal; and
and an inverter (INV) connected between the power line (ELVDDL) and the control terminal of the second switching unit (S2) to invert the power supply voltage (ELVDD) of the power line (ELVDDL). The method of claim 1,
Further comprising a data driver 30 for supplying data voltages to the display panel 10,
The input voltage is any one of gamma voltages (GMA) supplied to the data driver 30 to generate the data voltages. The method of claim 1,
When the display panel 10 is switched from a turn-on state to a turn-off state,
A discharge start timing T1 of the power supply voltage ELVDD is earlier than a discharge start timing T2 of the input voltage.
7. The method of claim 6,
When the display panel 10 is switched from a turn-on state to a turn-off state,
The discharge start timing T2 of the input voltage is earlier than the discharge start timing T3 of the reference voltage REF. turning on the discharge control circuit 200 when the power supply voltage ELVDD is lower than a second logic level L2 lower than the first logic level L1;
When the operational amplifier 201 receives the reference voltage REF and the gamma voltage GMA and the discharge control circuit 200 is turned on, the difference voltage between the reference voltage REF and the gamma voltage GMA outputting a driving signal Vout according to and
and discharging the power supply voltage ELVDD to the ground voltage GND by the discharging circuit 210 connecting the power line ELVDDL to the ground when the driving signal Vout is input. The method of claim 8, wherein turning on the discharge control circuit (200) comprises:
receiving the inverted power supply voltage INV_ELVDD by the second switching unit S2 built in the discharge control circuit 200 through the inverter line INVL including the inverter INV; and
and turning on the second switching unit (S2) when the inverted power voltage (INV_ELVDD) rises. The method of claim 8, wherein the outputting of the driving signal (Vout) comprises:
starting to discharge the gamma voltage GMA to the ground voltage GND;
starting to discharge the reference voltage REF to the ground voltage GND later than the gamma voltage GMA;
generating a difference voltage between a reference voltage REF and a gamma voltage GMA according to a difference in discharge start timing; and
and generating a driving signal (Vout) by using the differential voltage.

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