KR102417987B1 - An integrated circuit, an electronic device comprising thereof, and an operating method thereof - Google Patents

Abstract

An integrated circuit is disclosed. The integrated circuit includes: a plurality of DTCs, receiving a first reference signal and a first divided signal, and a second reference signal based on the first reference signal, the first divided signal, and a plurality of control codes and a DTC block for outputting a second divided signal; a TDC for comparing the phases of the second reference signal and the second divided signal, and outputting a comparison signal; a digital loop filter for filtering the comparison signal; an oscillator for generating an output signal based on the filtered comparison signal; a delta-sigma modulator for outputting the first signal and the quantization noise signal based on the first frequency-divided ratio signal and the second frequency-divided ratio signal; a divider for dividing a frequency of the output signal based on the first signal and outputting the first divided signal; and a probability modulator generating the plurality of control codes based on the quantization noise signal, wherein a probability density function of the plurality of control codes may be time-invariant.

Description

AN INTEGRATED CIRCUIT, AN ELECTRONIC DEVICE COMPRISING THEREOF, AND AN OPERATING METHOD THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, an electronic device including the same, and a method of operating the same, and more particularly to a fractional-N digital phase locked loop circuit.

A phase locked loop may generate a signal fixed to a target frequency based on a signal having a reference frequency. The phase-locked loop may generate a signal having frequencies required by various electronic devices such as a communication system or a processor. In order to more finely adjust the frequency of the generated signal, the fractional-N phase-locked loop may further include a delta-sigma modulator for adjusting the division ratio of the generated signal in fractional units.

As the loop bandwidth of the fractional phase-locked loop decreases, less noise of an oscillator included in the fractional phase-locked loop can be filtered, instead of more quantization noise being removed. In order to generate a signal accurately fixed to a target frequency, the fractional-N phase-locked loop may further include a digital-time converter for removing high-frequency quantization noise generated from the delta-sigma modulator.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated circuit for preventing the occurrence of fractional spurs due to the nonlinearity of the nonlinearity of a digital-time converter, an electronic device including the same, and an operating method thereof.

An integrated circuit according to an embodiment of the present invention includes: a plurality of digital-to-time converters (DTCs), receiving a first reference signal and a first frequency-divided signal, and the first reference signal, the first a DTC block for outputting a second reference signal and a second divided signal based on the divided signal and the plurality of control codes; a time-to-digital converter (TDC) for comparing the phases of the second reference signal and the second divided signal and outputting a comparison signal; a digital loop filter for filtering the comparison signal; an oscillator for generating an output signal based on the filtered comparison signal; a delta-sigma modulator for outputting the first signal and the quantization noise signal based on the first frequency-divided ratio signal and the second frequency-divided ratio signal; a divider for dividing a frequency of the output signal based on the first signal and outputting the first divided signal; and a probability modulator generating the plurality of control codes based on the quantization noise signal, wherein a probability density function of the plurality of control codes may be time-invariant.

An electronic device according to an embodiment of the present invention includes: a processor; and a communication device for receiving data from the outside under the control of the processor, wherein the communication device includes: a delta-sigma outputting a first signal and a quantized noise signal based on the first frequency-divided ratio signal and the second frequency-divided ratio signal modulator; a probability modulator generating a plurality of control codes based on the quantization noise signal; a plurality of digital-to-time converters (DTCs), configured to receive a first reference signal and a first divided signal, and based on the first reference signal, the first divided signal, and the plurality of control codes a DTC block for outputting a second reference signal and a second divided signal; a time-to-digital converter (TDC) for comparing the phases of the second reference signal and the second divided signal and outputting a comparison signal; a digital loop filter for filtering the comparison signal; an oscillator for generating an output signal based on the filtered comparison signal; and a circuit block receiving the first signal and the output signal, and generating the divided signal from the output signal in response to the first signal, wherein a probability density function of the plurality of control codes is time-invariant. can

A method according to an embodiment of the present invention includes: generating a plurality of control codes based on a first signal associated with quantization noise of a delta-sigma modulator; delaying a reference signal and a frequency-divided signal respectively in the time domain based on the plurality of control codes; and generating an output signal based on the delayed reference signal and the delayed divided signal, wherein probability density functions of the plurality of control codes may be time-invariant.

An integrated circuit according to an embodiment of the present invention may include a time-invariant probability modulator and a plurality of digital-time converters. The time-invariant probability modulator may generate a plurality of control codes for controlling the plurality of digital-time converters, each probability density function being time-invariant, based on the quantization noise of the delta-sigma modulator. Accordingly, spur due to non-linearity of digital-time converters can be reduced.

1 is an exemplary block diagram of an integrated circuit according to an embodiment of the present invention.
2A is an exemplary block diagram of a digital-to-time converter, a time-to-digital converter, and a time-invariant probability modulator according to an embodiment of the present invention.
2B is an exemplary block diagram of a digital-to-time converter, a time-to-digital converter, and a time-invariant probability modulator according to another embodiment of the present invention.
2C is an exemplary block diagram of a digital-to-time converter, a time-to-digital converter, and a time-invariant probability modulator according to another embodiment of the present invention.
3 is an exemplary flowchart of a method of operation of the integrated circuit of FIG. 1 ;
4 is an exemplary block diagram of the time-invariant probability modulator of FIG. 1 ;
5 is an exemplary block diagram of an integrated circuit according to another embodiment of the present invention.
6 is an exemplary block diagram of the digital-to-time converter, time-to-digital converter, time-invariant stochastic modulator, and digital-to-time converter gain controller of FIG. 5 ;
7 is an exemplary block diagram of an electronic device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In order to facilitate the overall understanding in describing the present invention, similar reference numerals are used for similar components in the drawings, and duplicate descriptions of similar components are omitted.

1 is an exemplary block diagram of an integrated circuit according to an embodiment of the present invention. Referring to FIG. 1 , an integrated circuit 1000 includes a digital-time converter (DTC) block 1100 , a time-digital converter 1200 (Time-Digital Converter; TDC), and a digital loop filter 1300 ; Digital Loop Filter (DLF), Digital-Controlled Oscillator (DCO), Divider 1500, Delta-Sigma Modulator 1600, and Time-Invariant Probability Modulator 100; TIPM) may be included. In an embodiment, the integrated circuit 1000 may be referred to as a digital phase locked loop (PLL) or a fractional-N PLL.

The DTC block 1100 may include a plurality of DTCs. The DTC block 1100 may receive the reference signal SREF and the division signal SDIV. The reference signal SREF may be received from a voltage generator circuit (not shown) included in the integrated circuit 1000 or a device external to the integrated circuit 1000 . The DTC block 1100 may receive a plurality of control codes DCW from the TIPM 100 . The DTC block 1100 may delay the reference signal SREF and the divided signal SDIV based on the received control codes DCW. For example, the DTC block 1100 may generate analog signals by delaying each of the reference signal SREF and the divided signal SDIV for a predetermined time in the time domain in response to the control codes DCW. The lengths of the time that the reference signal SREF and the divided signal SDIV are delayed may be based on the control codes DCW. The DTC block 1100 may transmit the delayed reference signal SREF and the delayed division signal SDIV to the TDC 1200 . In an embodiment, the DTC block 1100 may include the same number of digital-time converters as the number of control codes DCW provided from the TIPM 100 .

The TDC 1200 may receive the delayed reference signal SREFD and the delayed division signal SDIVD from the DTC block 1100 . The TDC 1200 may compare the phases of the delayed reference signal SREFD and the delayed divided signal SDIVD. Based on the comparison result, the TDC 1200 may output the comparison signal DTDC to the digital loop filter 1300 . In an embodiment, the comparison signal DTDC may be a digital signal. In an embodiment, the integrated circuit 1000 may include a phase comparator or a subsampler instead of the TDC 1200 .

The digital loop filter 1300 may receive the comparison signal DTDC from the TDC 1200 . The digital loop filter 1300 may filter the comparison signal DTDC. According to an embodiment, the digital loop filter 1300 may include a first path and a second path. The first path may filter the phase noise of the comparison signal DTDC. The second path may filter the offset in the frequency domain of the comparison signal TDC flowing from the TDC 1200 to the DCO 1400 through the digital loop filter 1300 .

In an embodiment, the integrated circuit 1000 may further include a loop gain controller (not shown). The digital loop filter 1300 may operate under the control of a loop gain controller. For example, the gain of the DCO 1400 may change due to a change in Process, Voltage, Temperature (PVT) of the integrated circuit 1000 . In order to compensate for the changed gain of the DCO 1400 , the loop gain controller may control the operation of the digital loop filter 1300 . The loop gain controller may adjust a degree to which the comparison signal DTDC is filtered based on various algorithms such as a least mean square (LMS) algorithm. For example, the loop gain controller may control the digital loop filter to minimize the autocorrelation coefficient of the comparison signal DTDC.

The DCO 1400 may output the output signal SOUT based on the signal filtered by the digital loop filter 1300 . For example, the frequency of the output signal SOUT may be adjusted by a signal filtered by the digital loop filter 1300 . In one embodiment, the DCO 1400 may be implemented as an LC oscillator or a Ring oscillator.

In an embodiment, as the phase noise is filtered by the first path of the digital loop filter 1300 described above, the low noise characteristic of the output signal SOUT of the DCO 1400 may be satisfied. As the frequency offset is filtered by the second path of the digital loop filter 1300 , the frequency of the output signal SOUT of the DCO 1400 may be adjusted to the target frequency.

The divider 1500 may receive an output signal SOUT from the DCO 1400 . The divider 1500 may receive a divider control code DVC based on a fractional signal FRAC and an integer signal DINT. The divider 1500 may divide the frequency of the output signal SOUT based on the divider control code DVC. The divider 1500 may output the division signal SDIV to the DTC block 1100 . As a result, the output signal SOUT generated through the DTC block 1100 , the TDC 1200 , the digital loop filter 1300 , and the DCO 1400 based on the reference signal SREF is again the DTC block 1100 . may be fed back based on the fractional signal FRAC and the integer signal DINT. As the feedback is repeated, the frequency of the output signal SOUT may be adjusted to target frequencies corresponding to the fractional signal FRAC and the integer signal DINT. Hereinafter, the DTC block 1100 , the TDC 1200 , the digital loop filter 1300 , the DCO 1400 , and the divider 1500 may be referred to as a feedback loop.

According to an embodiment, the divider 1500 may be implemented as a multi-modulus divider (MMD), but is not limited thereto.

In another embodiment, the integrated circuit 1000 may include a phase selector instead of the divider 1500 . In this case, the integrated circuit 1000 may be referred to as a subsampling PLL circuit. An MMD or phase selector may be referred to as a circuit block.

The delta-sigma modulator 1600 may generate a divider control code (DVC) for controlling the divider 1500 . The delta-sigma modulator 1600 may include a core circuit 1601 and an adder 1602 .

The core circuit 1601 may receive the fractional signal FRAC from an external device of the integrated circuit 1000 . The fractional signal FRAC may be a signal related to a frequency to be obtained through the divider 1500 . For example, the fractional signal FRAC may be a signal corresponding to a fractional part of the division ratio of the divider 1500 . The core circuit 1601 may generate a signal DDSM based on the fractional signal FRAC. The signal DDSM may be output to the adder 1602 .

The adder 1602 may perform an addition operation on the signal DDSM and the integer signal DINT. The integer signal DINT may be a signal related to a frequency to be obtained through the divider 1500 . For example, the integer signal DINT may be a signal corresponding to an integer part of the division ratio of the divider 1500 . The adder 1602 may output the divider control code DVC to the divider 1500 as a result of the addition operation.

In an embodiment, the delta-sigma modulator 1600 may be implemented as any one of modulators having various orders, such as Multi-stAge noise Shaping (MASH)1, MASH1-1, and MASH1-1-1. It is not limited.

The delta-sigma modulator 1600 may generate the quantization noise signal DAQ by accumulating the signal DDSM. For example, the delta-sigma modulator 1600 may include an accumulator capable of accumulating a difference between the fractional signal FRAC and the signal DDSM. Unlike shown, the accumulator may be external to the delta-sigma modulator 1600 . Based on the accumulated difference, a quantization noise signal DAQ may be generated. The quantization noise signal DAQ may be associated with noise generated as the delta-sigma modulator 1600 generates the signal DDSM. The delta-sigma modulator 1600 may output the quantization noise signal DAQ to the TIPM 100 .

The TIPM 100 may receive the quantization noise signal DAQ from the delta-sigma modulator 1600 . The TIPM 100 may generate a plurality of control codes DCW based on the quantization noise signal DAQ. The TIPM 100 may output the generated control codes DCW to the DTC block 1100 .

According to an embodiment, probability density functions of the control codes DCW generated by the TIPM 100 may have a time-invariant characteristic. For example, for arbitrary times t1 and t2, the probability density function of any control code DCWa may satisfy the following expression.

At the same time, the linear combination of the control codes DCW may correspond to the quantization noise signal DAQ.

In some embodiments, the DTC block 1100 may be non-linear. By generating the control codes DCW based on the quantization noise signal DAQ, the TIPM 100 prevents the generation of a fractional spur caused by the nonlinearity of the DTC block 1100 . can stop The relationship between the control codes DCW generated by the TIPM 100 and the nonlinearity of the DTC block 1100 will be specifically described later.

2A, 2B, and 2C are exemplary block diagrams of a digital-to-time converter, a time-to-digital converter, and a time-invariant stochastic modulator in accordance with some embodiments of the present invention. Examples in which the control codes DCW generated from the TIPM 100 are output to the DTC block 1100 will be described in more detail with reference to FIGS. 1, 2A, 2B, and 2C .

In the embodiment shown in FIG. 2A , the DTC block 1100a may include a first DTC 1110a and a second DTC 1120a. The first DTC 1110a and the second DTC 1120a may be implemented as digital-time converters.

The first DTC 1110a may receive the reference signal SREF. The first DTC 1110a may receive the control code DCWD from the TIPM 100a. The first DTC 1110a may output the delayed reference signal SREFD to the TDC 1200a based on the reference signal SREF and the control code DCWR.

The second DTC 1120a may receive the divided signal SDIV. The second DTC 1120a may receive the control code DCWD from the TIPM 100a. The second DTC 1120a may output the delayed division signal SDIVD to the TDC 1200a based on the division signal SDIV and the control code DCWD.

As a result, in the embodiment shown in FIG. 2A , the TIPM 100a may generate two control codes DCWR and DCWD. Each of the control codes DWCR and DWCD may be input to the corresponding DTC of the DTC block 1100a. The first DTC 1110a and the second DTC 1120a may operate based on corresponding control codes.

In the embodiment shown in FIG. 2B , the DTC block 1100b may include a third DTC 1121b and a fourth DTC 1122b. In contrast to the first DTC 1110a and the second DTC 1120a of FIG. 2A may be disposed in parallel, the third DTC 1121b and the fourth DTC 1122b of FIG. 2B may be disposed in series . Also, in contrast to the first DTC 1110a of FIG. 2A generating the delayed reference signal SREFD based on the reference signal SREF, in the embodiment shown in FIG. 2B , the reference signal SREF is in the time domain may not be delayed. In this case, the reference signal SREF may be provided to the TDC 1200b through the DTC block 1100b.

The third DTC 1121b may receive the divided signal SDIV. The third DTC 1121b may receive the control code DCWD1 from the TIPM 100b. The third DTC 1121b may generate an analog signal based on the divided signal SDIV and the control code DCWD1. The third DTC 1121b may transmit the generated analog signal to the fourth DTC 1122b.

The fourth DTC 1122b may receive an analog signal generated by the third DTC 1121b. The fourth DTC 1122b may receive the control code DCWD2 from the TIPM 100b. The fourth DTC 1122b may generate the delayed division signal SDIVD based on the analog signal and the control code DCWD2 generated by the third DTC 1121b.

As a result, in the embodiment shown in FIG. 2B , the TIPM 100a may generate two control codes DCWD1 and DCWD2. The control codes DWCD1 and DWCD2 may be input to the corresponding DTC of the DTC block 1100b, respectively. The third DTC 1121b and the fourth DTC 1122b may operate based on the corresponding control codes.

In the embodiment shown in FIG. 2C , the DTC block 1100b may include a first DTC group 1110c and a second DTC group 1120c. The first DTC group 1110c and the second DTC group 1120c may include a plurality of series-connected DTCs.

The first DTC group 1110c may include n DTCs, and n may be an integer greater than 1. Each of the DTCs of the first DTC group 1110c may receive a corresponding control code from the TIPM 100c. The delay time of each DTC can be adjusted by a corresponding control code.

The second DTC group 1120c may include m DTCs, and m may be an integer greater than 1. Each of the DTCs of the second DTC group 1120c may receive a corresponding control code from the TIPM 100c. The delay time of each DTC can be adjusted by a corresponding control code.

As a result, in the embodiment shown in FIG. 2C , the TIPM 100a may generate n+m control codes DCWR1 to DCWRn and DCWD1 to DCWDn. Control codes DCWR1 to DCWRn and DCWD1 to DCWDn may be respectively input to corresponding DTCs.

2A, 2B, and 2C, it has been described that the TIPM 100 can generate a variable number of control codes. However, the number of control codes that the TIPM 100 can generate and the number of DTCs that the DTC block 1100 can include are not limited to the illustrated embodiment.

3 is an exemplary flowchart of a method of operation of the integrated circuit of FIG. 1 ; 1 and 3 , the integrated circuit 1000 may perform steps S100 to S300 .

In operation S100 , the integrated circuit 1000 may generate control codes for controlling the digital-time converter based on the quantization noise of the delta-sigma modulator. For example, the TIPM 100 of the integrated circuit 1000 may generate the control codes DCW based on the quantization noise signal DAQ. The probability density function of the control codes DCW may be time-invariant. Also, the sum of the linear combination of the control codes DCW may correspond to the quantization noise signal DAQ.

In operation S200 , the integrated circuit 1000 may delay the divided signal SDIV and/or the reference signal SREF in the time domain based on control codes. For example, the DTC block 1100 of the integrated circuit 1000 may delay the division signal SDIV and/or the reference signal SREF by a predetermined time in the time domain based on the control codes DCW, thereby delaying division. A signal SDIVD and/or a delayed reference signal SREF may be generated.

In operation S300 , the integrated circuit 1000 may generate the output signal SOUT based on the delayed division signal SDIVD and/or the delayed reference signal SREF. For example, the TDC 1200 of the integrated circuit may output the comparison signal DTDC based on the delayed division signal SDIVD and the delayed reference signal SREF. The digital loop filter 1300 may filter the comparison signal DTDC and transmit the filtered signal to the DCO 1400 . The DCO 1400 may generate the output signal SOUT based on the filtered signal.

As steps S100 to S300 are performed, the quantization noise signal DAQ generated from the delta-sigma modulator 1600 may be reflected to the feedback loop of the integrated circuit 1000 through the TIPM 100 . As the bandwidth of the feedback loop of the integrated circuit 1000 is smaller, the quantization noise signal DAQ having a high frequency band may be further filtered by the feedback loop. However, in this case, the noise of the DCO 1400 may not be sufficiently filtered. As a result, the integrated circuit 1000 may not satisfy low-jitter characteristics. Conversely, the larger the bandwidth of the feedback loop, the more the noise of the DCO 1400 is filtered, but the quantization noise signal DAQ may not be sufficiently filtered. That is, when determining the bandwidth of the feedback loop, filtering of the quantization noise signal DAQ and filtering of the noise of the DCO 1400 may be in a trade-off with each other. The unfiltered (or residual) quantization noise signal DAQ may cause degradation of the phase noise characteristic of the integrated circuit 1000 in the high frequency offset frequency band. Accordingly, the performance of the integrated circuit 1000 may deteriorate.

In order to sufficiently cancel the quantization noise signal DAQ, the DTC block 1100 may operate in response to control codes DCW associated with the quantization noise signal DAQ. According to an embodiment, the DTC block 1100 may determine the delay time linearly based on the control codes DCW. The DTC block 1100 may delay the reference signal SREF and the divided signal SDIV in the time domain by a determined delay time, respectively. The DTC block 1100 may provide the delayed reference signal SREFD and the delayed division signal SDIVD to the TDC 1200 . The delayed reference signal SREFD and the delayed divided signal SDIVD may be signals from which the quantization noise signal DAQ is sufficiently canceled.

In some embodiments, the DTC block 1100 may determine the delay time non-linearly. As described above, the TIPM 100 may generate control codes DCW having a time-invariant probability density function. Since the time-invariant property of the probability density functions of the control codes DCW is maintained even if distorted by the nonlinearity of the DTC block 1100, the probability density function of the delay time determined by the DTC block 1100 may also be time-invariant. Therefore, the delay time determined by the DTC block 1100 may not have a fractional spur.

The TIPM 100 of the integrated circuit 1000 may compensate for the nonlinearity of the DTC block 1100 by generating time-invariant control codes DCW based on the quantization noise signal DAQ. Due to this, despite the nonlinearity of the DTC block 1100 , a signal having a fractional spur may not flow into the TDC 1200 . Since a signal having a fractional spur does not flow into the feedback loop, a fractional spur of the output signal SOUT may not occur. Due to this, the performance of the integrated circuit 1000 may be improved.

In some embodiments, DCO 1400 may be implemented as a ring oscillator instead of an LC oscillator. Compared to LC oscillators, ring oscillators can have higher noise characteristics at the cost of occupying less area. The TIPM 100 may provide the control codes DCW in which the probability density function is modulated to a feedback loop of the integrated circuit 1000 . Since the probability density functions of the control codes DCW are time-invariant, even if distorted by the nonlinearity of the DTC block 1100, fractional spur may not occur. Accordingly, even if the bandwidth of the feedback loop is further increased (ie, the integrated circuit 1000 is referred to as a wideband PLL), the low noise characteristic can be satisfied while the low fractional spur characteristic can be achieved. As a result, due to the TIPM 100 , the integrated circuit 1000 may occupy a smaller area while improving performance.

4 is an exemplary block diagram of the time-invariant probability modulator of FIG. 1 ; 1 and 4, the TIPM 100 includes adders A1 to A4, multipliers M1 and M2, a Uniform Random Number Generator (URNG), a comparator (CMP), and a multiplexer ( MUX) may be included.

In the embodiment shown in FIG. 4 , the TIPM 100 generates control codes DCWR and DWCD that compensate for the quantization noise signal DAQ generated by the delta-sigma modulator 1600 implemented in MASH 11. can In this case, due to the characteristics of MASH 11, the probability density function of the quantization noise signal DAQ may be expressed as a triangular function distributed between the intervals [-1, 1]. The control codes DCWR and DWCD generated by the TIPM 100 may be respectively input to the first DTC 1110a and the second DTC 1120a of the DTC block 1100a of FIG. 2A .

The uniform random number generator (URNG) may generate a random number according to a uniform distribution. For example, the uniform random number generator (URNG) may generate random numbers evenly distributed between the intervals [0, 1]. The uniform random number generator URNG may provide the generated random number to the multipliers M1 and M2.

The adder A1 may perform an addition operation on the integer 1 and the negative number of the quantization noise signal DAQ. The multiplier M1 may perform a multiplication operation on the result of the operation of the adder A1 and the random number output from the uniform random number generator URNG. The adder A2 may perform an addition operation on the integer 1 and the negative number of the operation result of the multiplier M1 . The operation result of the adder A2 may be input to the multiplexer MUX.

The adder A2 may perform an addition operation on the integer 1 and the quantization noise signal DAQ. The multiplier M2 may perform a multiplication operation on the operation result of the adder A2 and the random number output from the uniform random number generator URNG. The operation result of the multiplier M2 may be input to the multiplexer MUX.

The comparator CMP may determine the sign of the quantization noise signal DAQ. For example, the comparator CMP may compare whether the quantization noise signal DAQ is greater than or equal to zero. The comparator CMP may transmit a selection signal SEL based on the comparison result to the multiplexer MUX. When the quantization noise signal DAQ is greater than or equal to 0, the selection signal SEL may correspond to the input '1' of the multiplexer MUX. Otherwise, the selection signal SEL may correspond to the input '0' of the multiplexer MUX.

The multiplexer MUX may output either the operation result of the adder A2 or the operation result of the multiplier M2 as the control code DCWD in response to the selection signal SEL. The control code DCWD output from the multiplexer MUX may be transmitted to the adder A4 and the second DTC 1120a of the DTC block 1100a.

The adder A4 may perform an addition operation on the negative numbers of the control code DCWD and the quantization noise signal DAQ. The adder A4 may output a control code DCWR based on the operation result. The control code DCWR output from the adder A4 may be transmitted to the first DTC 1110a of the DTC block 1100a.

The control codes DCWD and DCWR generated by the TIPM 100 may be expressed as follows.

Rearranging the results of Equations 2 and 3, the control codes DCWD and DCWR can be expressed more simply as follows.

Referring to Equations 4 and 5, it can be seen that the control codes DCWD and DCWR generated by the TIPM 100 follow a uniform distribution regardless of the quantization noise signal DAQ. Accordingly, the probability density function of the control code DWCD and the probability density function of the control code DWCR may be time-invariant. Also, referring to Equation 3, the difference between the control code DWCD and the control code DWCR may correspond to the quantization noise signal DAQ. In other words, the control codes DWCD, DWCR may be generated such that their linear combination corresponds to the quantization noise signal DAQ.

In response to the quantization noise signal DAQ output from the delta-sigma modulator 1600 implemented in MASH11 with reference to FIGS. 1, 2A, and 4, two control codes (DWCD, DWCR) are uniformly randomized. How to use it to create it has been described. However, this is only an example, and the present disclosure is not limited thereto.

5 is an exemplary block diagram of an integrated circuit according to another embodiment of the present invention. 1 and 5, the difference between the integrated circuit 1000 of FIG. 1 and the integrated circuit 2000 of FIG. 5 will be described.

The integrated circuit 2000 of FIG. 5 includes a DTC block 2100 , a TDC 2200 , a digital loop filter 2300 , a DCO 2400 , a divider 2500 , a delta-sigma modulator 2600 , and a TIPM 200 . , and a DTC gain controller 2700 . TDC 2200 , digital loop filter 2300 , DCO 2400 , divider 2500 , delta-sigma modulator 2600 , and TIPM 200 are each TDC 1200 of integrated circuit 1000 of FIG. 1 . , digital loop filter 1300 , DCO 1400 , divider 1500 , delta-sigma modulator 1600 , and TIPM 100 may be implemented and operated in a similar manner.

Compared to the integrated circuit 1000 of FIG. 1 , the integrated circuit 2000 of FIG. 5 may further include a DTC gain controller 2700 . The DTC gain controller 2700 may receive control codes DCW from the TIPM 200 . The DTC gain controller 2700 may adjust the control codes DCW. The DTC gain controller 2700 may transmit the adjusted control codes DCWG to the DTC block 2100 . The DTC block 2100 may operate based on coordinated control codes DCWG.

The DTC gain controller 2700 may control the gain of the DTC block 2100 by providing the adjusted control codes DCWG to the DTC block 2100 . For example, in order to completely block the quantization noise signal DAQ, the DTC gain controller 2700 controls the period of the output signal SOUT output from the DCO 2400 and the control codes ( DCWG) can be adjusted to be equal to the ratio between the control codes DCWG. In an embodiment, the DTC gain controller 2700 may adjust the gain of the DTC block 2100 using various algorithms such as an LMS algorithm. For example, the DTC gain controller 2700 controls the gain of the DTC block 2100 until the cross-correlation coefficient between the comparison signal DTDC and the control codes DCWG output from the TDC 2200 approaches zero. can be adjusted. Accordingly, the performance of the integrated circuit 2000 may be improved.

6 is an exemplary block diagram of the digital-to-time converter, time-to-digital converter, time-invariant stochastic modulator, and digital-to-time converter gain controller of FIG. 5 ; 2A, 5 and 6 , the DTC gain controller 2700 may include multipliers MG1 to MG4 , accumulators ACC1 and ACC2 , and an inverter INV. The DTC block 2100 may be implemented in a similar manner to the DTC block 1100a of FIG. 2A , and may operate in a similar manner.

The multiplier MG1 may receive the comparison signal DTDC from the TDC 2200 . The multiplier MG1 may receive the control code DCWR from the TIPM 200 . The multiplier MG1 may perform a multiplication operation on the comparison signal DTDC and the control code DCWR. The inverter INV may invert a signal corresponding to the operation result of the multiplier MG1 . The accumulator ACC1 may accumulate the signal inverted by the inverter INV. The multiplier MG2 may perform a multiplication operation on the signal accumulated by the accumulator ACC1 and the control code DCWR. The multiplier MG2 may output the result of the multiplication operation as the adjusted control code DCWGR to the converter 2110 of the DTC block 2100 .

The multiplier MG3 may receive the comparison signal DTDC from the TDC 2200 . The multiplier MG3 may receive the control code DCWD from the TIPM 200 . The multiplier MG3 may perform a multiplication operation on the comparison signal DTDC and the control code DCWD. The accumulator ACC2 may accumulate the operation result of the multiplier MG3 . The multiplier MG4 may perform a multiplication operation on the signal accumulated by the accumulator ACC2 and the control code DCWD. The multiplier MG4 may output the result of the multiplication operation to the converter 2120 of the DTC block 2100 as the adjusted control code DCWGD.

Through a multiplier MG1, an inverter INV, an accumulator ACC1, and a multiplier MG2, the adjusted control code DCWGR associated with the cross-correlation coefficient between the control code DCWR and the comparison signal DTDC is DTC It may be provided as block 2100 . Through multiplier MG3, accumulator ACC2, and multiplier MG4, the adjusted control code DCWGD associated with the cross-correlation coefficient between the control code DCWD and the comparison signal DTDC is sent to the DTC block 2100. can be provided. Accordingly, unlike the DTC block 1100 of FIG. 1 , the gain of the DTC block 2100 may be adjusted.

7 is an exemplary block diagram of an electronic device according to an embodiment of the present invention. Referring to FIG. 7 , the electronic device 3000 may include a processor 3100 , a working memory 3200 , a storage device 3300 , a communication device 3400 , and an interface circuit 3500 .

The processor 3100 may function as a central processing unit of the electronic device 3000 . The processor 3100 may include one or more core(s) capable of performing various operations. The core(s) may be implemented as a central processing unit (CPU), a digital signal processing unit (DSP), or a graphics processing unit (GPU).

The working memory 3200 may store data and program codes to be processed or to be processed by the processor 3100 . The working memory 3200 may function as a main memory device of the electronic device 3000 . The working memory 3200 may be implemented as dynamic random access memory (DRAM) or static random access memory (SRAM). The working memory 3200 may also be referred to as a buffer memory or a cache memory.

The storage device 3300 may function as an auxiliary storage device of the electronic device 3000 . The storage device 3300 may include a nonvolatile memory device such as a read-only memory (ROM) or a solid state drive (SSD). Data stored in the storage device 3300 may be transmitted to the processor 3100 via a bus.

The communication device 3400 may communicate with an external device of the electronic device 3000 wirelessly or by wire. The communication device 3400 may receive data for the operation of the electronic device 3000 from an external device. The communication device 3400 may transmit data generated by the processor 3100 to an external device.

The communication device 3400 may include the integrated circuit 1000 of FIG. 1 or the integrated circuit 2000 of FIG. 5 . Based on the output signal SOUT output from the integrated circuit 1000/2000, the communication device 3400 may generate signals having various frequencies and may modulate or demodulate the generated signals. For example, the output signal SOUT may have a frequency included in an ultra-high frequency band, such as a millimeter wave band, and simultaneously satisfy a low noise characteristic. Accordingly, the performance of the communication device 3400 may be improved.

The interface circuit 3500 may include various input/output devices for communicating with an external device. For example, the interface circuit 3500 may include at least one of various output devices such as a monitor, a printer, or a lamp. The interface circuit 3500 may include at least one of various input devices such as a keyboard, a touchpad, a mouse, and a microphone.

In the above-described embodiments, components according to embodiments of the present invention have been referred to by using blocks. Blocks include various hardware devices such as IC (Integrated Circuit), ASIC (Application Specific IC), FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), etc., firmware running on the hardware devices, software such as applications, Alternatively, the hardware device and software may be implemented in a combined form. In addition, the blocks may include circuits composed of semiconductor elements in the IC or circuits registered as IP (Intellectual Property).

The above are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the claims described below as well as the claims and equivalents of the present invention.

1000, 2000: integrated circuit
100: time invariant probability modulator (TIPM)

Claims (20)

a plurality of DTCs, receiving a first reference signal and a first divided signal, and based on the first reference signal, the first divided signal, and a plurality of control codes, a second reference signal and a second division DTC block outputting a signal;
a TDC for comparing the phases of the second reference signal and the second divided signal, and outputting a comparison signal;
a digital loop filter for filtering the comparison signal;
an oscillator for generating an output signal based on the filtered comparison signal;
a delta-sigma modulator for outputting the first signal and the quantization noise signal based on the first frequency-divided ratio signal and the second frequency-divided ratio signal;
a divider for dividing a frequency of the output signal based on the first signal and outputting the first divided signal; and
a probability modulator generating the plurality of control codes based on the quantization noise signal;
wherein the probability density function of the plurality of control codes is time-invariant. The method of claim 1,
wherein the linear combination of the plurality of control codes corresponds to the quantized noise signal. The method of claim 1,
wherein the probability density functions of each of the plurality of control codes are time-invariant. The method of claim 1,
The DTC block includes a first DTC and a second DTC,
the first DTC delays the first reference signal for a first delay time in the time domain in response to a first one of the plurality of control codes, and
and the second DTC delays the first divided signal for a second delay time in the time domain in response to a second control code among the plurality of control codes. The method of claim 1,
The DTC block includes a first DTC and a second DTC connected in series,
the first DTC delays the first divided signal for a first delay time in the time domain in response to a first one of the plurality of control codes, and outputs a first intermediate signal, and
and the second DTC delays the first intermediate signal for a second delay time in the time domain in response to a second one of the plurality of control codes. The method of claim 1,
The probability modulator comprises a uniform random number generator, and
The random modulator generates the plurality of control codes based on the uniform random number generated by the uniform random number generator. The method of claim 1,
The plurality of control codes includes a first control code and a second control code,
The probability density function of the first control code and the probability density function of the second control code follow a uniform distribution, and
The difference between the first control code and the second control code corresponds to the quantization noise signal. The method of claim 1,
a DTC gain controller modulating the plurality of control codes and providing the modulated plurality of control codes to the DTC block;
wherein the DTC block operates based on the modulated plurality of control codes. processor; and
A communication device for receiving data from the outside under the control of the processor, the communication device comprising:
a delta-sigma modulator for outputting the first signal and the quantization noise signal based on the first frequency-divided ratio signal and the second frequency-divided ratio signal;
a probability modulator generating a plurality of control codes based on the quantization noise signal;
a plurality of DTCs, receiving a first reference signal and a first divided signal, and based on the first reference signal, the first divided signal, and the plurality of control codes, a second reference signal and a second DTC block for outputting a divided signal;
a TDC for comparing the phases of the second reference signal and the second divided signal, and outputting a comparison signal;
a digital loop filter for filtering the comparison signal;
an oscillator for generating an output signal based on the filtered comparison signal; and
a circuit block receiving the first signal and the output signal and generating the divided signal from the output signal in response to the first signal;
and a probability density function of the plurality of control codes is time-invariant. 10. The method of claim 9,
The probability density functions of each of the plurality of control codes are time-invariant, and
The linear combination of the plurality of control codes corresponds to the quantization noise signal. 10. The method of claim 9,
The plurality of control codes includes a first control code and a second control code,
The probability density function of the first control code and the probability density function of the second control code follow a uniform distribution, and
The difference between the first control code and the second control code corresponds to the quantization noise signal. 10. The method of claim 9,
wherein the circuit block includes either an MMD or a phase selector. 10. The method of claim 9,
a DTC gain controller modulating the plurality of control codes and providing the modulated plurality of control codes to the DTC block;
The DTC block operates based on the plurality of modulated control codes. 10. The method of claim 9,
The probability modulator comprises a uniform random number generator, and
The probability modulator generates the plurality of control codes based on the uniform random number generated by the uniform random number generator. generating a plurality of control codes based on a first signal associated with quantization noise of a delta-sigma modulator;
delaying a reference signal and a frequency-divided signal respectively in the time domain based on the plurality of control codes; and
generating an output signal based on the delayed reference signal and the delayed divided signal;
wherein the probability density functions of the plurality of control codes are time-invariant. 16. The method of claim 15,
The probability density functions of each of the plurality of control codes are time-invariant, and
wherein the linear combination of the plurality of control codes corresponds to the quantization noise signal. 16. The method of claim 15,
The plurality of control codes includes a first control code and a second control code, and generating the plurality of control codes comprises:
generating a first intermediate code and a second intermediate code based on the first signal and a uniform distribution function;
determining one of the first intermediate code and the second intermediate code as the second control code based on a sign of the first signal; and
and generating the first control code that is the difference of the second control code and the first signal. 18. The method of claim 17,
Delaying each of the reference signal and the divided signal in a time domain based on the plurality of control codes includes:
delaying the reference signal by a first delay time in a time domain based on the first control code; and
Based on the second control code, the method further comprising the step of delaying the divided signal by a second delay time in the time domain. 18. The method of claim 17,
generating the output signal further comprises comparing a phase of the delayed reference signal and a phase of the delayed divided signal; and
Delaying each of the reference signal and the divided signal in a time domain based on the plurality of control codes includes:
modulating the first control code and the second control code based on a comparison signal corresponding to a result of comparing the phase of the delayed reference signal and the phase of the delayed divided signal;
delaying the reference signal by a first delay time in a time domain based on the modulated first control code; and
Based on the modulated second control code, the method further comprising the step of delaying the divided signal by a second delay time in the time domain 20. The method of claim 19,
The step of modulating the first control code and the second control code based on a result of comparing the phase of the delayed reference signal and the phase of the delayed divided signal may include:
calculating a first value that is a product of the comparison signal and the first control code;
inverting the first value;
accumulating the inverted first value to generate a second value;
calculating a product of the second value and the first control code;
calculating a third value that is a product of the comparison signal and the second control code;
accumulating the third value to generate a fourth value; and
The method further comprising calculating a product of the fourth value and the second control code.

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