KR102416885B1 - Apparatus and Driving Method of Timing Controller and Display Device using the same - Google Patents

Abstract

According to the present invention, a DE signal is generated and output from the period during which the data voltage should be supplied to the last horizontal line of the frame in which the no-signal mode is started, that is, until the data voltage supply is finished in the frame in which the no-signal mode is started, and then sufficient vertical blanking is performed. To a timing controller capable of preventing an operation algorithm of a display device from being abnormally performed by driving it using an internal DE after securing a section, a driving method therefor, and a display device using the same, the timing controller according to the present invention , a delay DE is generated using the last input DE input in the no-signal mode, and the delay DE is output for a period corresponding to the time when data voltages are to be supplied to all horizontal lines of the frame in which the no-signal mode is started. Next, a sufficient vertical blank section is secured, and thereafter, internal data synchronized with the internal DE is output.

Description

Timing controller, driving method thereof, and display device using same

The present invention relates to a timing controller and a driving method thereof, and in particular, in a no-signal mode, by generating a delay DE using an input DE input immediately before and maintaining the supply of the delay DE until a vertical blank section of one frame is reached. The present invention relates to a timing controller, a method for driving the same, and a display device using the same, which allow the operation timing of various control signals output from the timing controller to be normally maintained even in a mode.

An active matrix display device (hereinafter, referred to as a 'display device') includes a display panel that displays an image through a pixel matrix, a panel driving circuit that drives the display panel, and a gate line and data line provided in the display panel to drive the display panel. and a timing controller that aligns image data input from the outside and supplies the aligned image data to the gate and data driver to control operation timing of the display panel.

The timing controller generates timing control signals for controlling operation timings of the gate driver and the data driver based on timing signals inputted together with the input image data. An operation mode such as a normal mode and a no signal mode may be set in the timing controller.

In the normal mode, the timing controller generates various control signals in response to an input data enable signal (hereinafter, referred to as 'input DE') provided from an external system.

The timing controller operates in a no-signal mode when there is no input data enable signal (hereinafter referred to as 'input DE') input from the outside or is input abnormally. In the no-signal mode, the timing controller internally generates an internal data enable signal (hereinafter referred to as 'internal DE'), and transmits pre-stored image data (hereinafter referred to as 'internal data') to the data driver to synchronize with the internal DE. Output to prevent noise on the display screen.

However, when the conventional timing controller operates in the no-signal mode, the frame immediately before the operation in the no-signal mode is forcibly ended, and image data is supplied to only some horizontal lines among a plurality of horizontal lines provided in the display panel. In this frame driving state, the point in time when the internal DE is input again is recognized as a new frame.

As described above, when the frame immediately before operation in the no-signal mode is forcibly terminated, the timing controller does not secure a sufficient vertical blank section in the frame, and accordingly, panel data and touch sensing or image performed by the display device in the vertical blank section A problem occurs in driving the display device because an operation algorithm such as data compensation is performed abnormally.

The present invention has been devised in order to solve the above problem, and the period during which the data voltage should be supplied to the last horizontal line of the frame in which the no-signal mode starts, that is, the DE signal from the frame in which the no-signal mode starts to the time when the data voltage supply ends A timing controller capable of preventing an operation algorithm of a display device from being abnormally performed by generating and outputting it and then driving it using an internal DE after securing a sufficient vertical blank section, a driving method thereof, and a display device using the same Make what you provide as the task you want to solve.

In order to solve the above problem, the timing controller according to the present invention generates a delay DE using the last input DE in the no-signal mode, and the data voltage must be supplied to all horizontal lines of the frame in which the no-signal mode is started. After the delay DE is output for a period corresponding to the time to be executed, a sufficient vertical blank section is secured, and thereafter, internal data synchronized with the internal DE is output.

The timing controller according to the present invention continuously generates a delay DE (make_DE) for a period corresponding to the time when the data voltage is applied to all horizontal lines within the frame at the time of the no-signal mode driving, even when driving in the no-signal mode, so that the data driver output to Then, until the internal DE (internal_DE) and the internal data (internal_data) are output, the drive is performed in a vertical blank section. Therefore, the timing controller according to the present invention secures a sufficient vertical blank section even in a frame driven in the no-signal mode, and the frame in which the no-signal mode starts driving is also normally ended.

1 and 2 are exemplary diagrams for explaining in more detail an organic light emitting display device and a liquid crystal display including a timing controller according to the present invention.
3 is a block diagram illustrating a timing controller according to the present invention.
4 is a waveform diagram illustrating waveforms of DE and image data output when the timing controller is driven in a no-signal mode.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description are selected in consideration of the ease of writing the specification, and may be different from the part names of the actual product.

1 and 2 are exemplary views for explaining in more detail an organic light emitting display device and a liquid crystal display including a timing controller according to the present invention.

The display device illustrated in FIGS. 1 and 2 includes a display panel 1 defined in a region where a plurality of gate lines GL and a data line DL intersect and including a plurality of pixels arranged in a matrix form; , a timing controller 4 that aligns image signals input from the outside and controls an operation timing of a panel driving circuit to output the aligned image signals to the display panel 1 , and output from the timing controller 4 . and a gate driver 3 and a data driver 2 for driving the gate line GL and the data line DL provided in the display panel 1 according to a signal to be generated.

When the display panel 1 is an organic light emitting diode display, each pixel includes an organic light emitting diode (OLED) including an organic light emitting layer between an anode and a cathode, and a pixel circuit independently driving the organic light emitting diode (OLED). .

The pixel circuit includes at least one switching transistor TR1 and TR3 , at least one capacitor Cst, and a driving transistor TR2 . The plurality of switching transistors TR1 and TR3 charges the capacitor Cst with a data signal in response to a scan signal generated in units of every horizontal period. In addition, the driving transistor TR2 drives the organic light emitting diode by supplying a constant voltage V _DD to the organic light emitting device according to the data voltage charged in the capacitor Cst.

When the display panel 1 is a liquid crystal display, each pixel includes a thin film transistor (TFT) and a liquid crystal capacitor Clc connected to the thin film transistor. The liquid crystal capacitor Clc includes a pixel electrode connected to the thin film transistor and a common electrode Vcom disposed with the pixel electrode and the liquid crystal interposed therebetween. The thin film transistor supplies an image signal from each data line DL to the pixel electrode in response to a scan pulse from each gate line GL.

The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage Vcom applied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage to adjust the grayscale. to implement

3 is a block diagram for explaining the timing controller 4 according to the present invention.

As shown in FIG. 3 , the timing controller 4 according to the present invention includes a non-signal detection unit 41 , a delayed DE generation unit 42 , a delay unit 43 , and an internal DE generation unit 44 , , an internal data generating unit 45 , and a first selecting unit 46 and a second selecting unit 47 .

The no-signal detection unit 41 receives the input DE input from the external system, analyzes the input DE, and sets the timing controller 4 to the no-signal mode when there is no input of the input DE or an abnormal signal is detected. A non-signal mode signal (abnormal_signal) for driving is output. At this time, the non-signal mode signal (abnormal_signal) is transmitted to the delayed DE generating unit 41 , the internal DE generating unit 42 , the delay unit 43 , and the first and second selectors 46 and 47 . is output

The delay DE generating unit 42 generates a first delay DE in which the input DE is delayed by n horizontal periods (n is a natural number equal to or greater than 1). The timing controller 4 receives image data from the outside, undergoes various image processing, and outputs the image data to the data driver 3 , so that even if the image data is output in synchronization with the input DE, the output is delayed compared to the input DE. Accordingly, the delay DE generator 42 generates the first delay DE by using the input DE, synchronizes the image data with the first delay DE, and outputs it to the data driver 3 .

However, when there is no input of the input DE or an abnormal signal is input, the delay DE generating unit 42 generates a problem in driving to generate the first delay DE delayed the input DE.

In the no-signal mode, the delayed DE generating unit 42 according to the present invention responds to the non-signal mode signal (abnormal_signal) input from the non-signal detecting unit 41, even when there is no input of the input DE. In the frame to which the signal is input, the period during which the data voltage corresponding to the last horizontal line of the display panel 1 should be output, that is, if the no-signal mode is not input, repeats until the point in time when the output of all image data of the frame is normally completed to generate and output the second delay DE. To this end, the delay DE generator 42 may include a latch unit (not shown) and a clock counter (not shown).

The latch unit latches the last input DE among the externally inputted inputs DE. Then, when the signal-free mode signal is supplied, a second delay DE is generated using the latched input DE based on the falling edge of the last input DE.

At this time, the latch unit latches the voltage level when the input DE(input_DE) rises, and then the second delay DE so that the maximum voltage level of the second delay DE becomes the latched voltage level of the input DE in the no-signal mode. to output In addition, the delay DE generator 42 counts an external clock supplied from an external system or an internal clock generated using an external clock from the timing controller 4 up to a predetermined value k by using the clock counter, and the counted An output section of the second delay DE having a width corresponding to the number of k internal clock or external clock inputs may be generated. Also, the delay DE generator 42 may determine the width of the non-output section of the second delay DE by using an external clock or an internal clock, and accordingly, the second delay DE has the same waveform as that of the first delay DE. is formed with

The delay DE generator 42 generates and outputs the second delay DE before the period in which the data voltage corresponding to the last horizontal line of the display panel 1 is to be output, that is, before the vertical blank period within the frame to which the signal-free mode signal is received. By doing so, the frame receiving the signal-free mode signal is stably ended.

The delay unit 43 delays the output of the input image data input_data in synchronization with the input DE(input_DE), receives the first delay DE, and synchronizes the image data input_data with the first delay DE 2 is outputted to the selection unit 47 . To this end, the delay unit 43 may include a data memory. Meanwhile, the delay unit 43 stops outputting the image data input_data when the timing controller 4 is driven in the no-signal mode because the input DE(input_DE) is not input or an abnormal signal is input.

The internal DE generation unit 44 generates an internal DE (internal_DE) in response to the non-signal mode signal abnormal_signal input from the non-signal detection unit 41 , and uses the internal DE as a first selector and an internal data generation unit 45 . ) is output.

The internal data generator 45 stores internal data internal_data to be output to the display panel 1 in the non-signal mode. The internal data (internal_data) may be set to the minimum data such as a predetermined message, logo, and time data. The internal data generator 45 receives the internal DE(internal_DE) and outputs the internal data to the second selector 47 in synchronization with the internal DE(internal_DE).

In the normal mode, the first selector 46 outputs the delay DE as an output DE(output_DE), and the second selector 47 synchronizes the image data input_data with the output DE(output_DE). print out

In the non-signal mode, the non-signal mode signal Abnormal_mode is input to the first selector 46 and the second selector 47 .

In response to the non-signal mode signal abnormal_mode, the first selector 46 is configured to output a data voltage corresponding to the last horizontal line of the display panel 1 within a frame to which the non-signal mode signal abnormal_mode is input. The data driver ( 3) is printed.

In the no-signal mode, the supply of the image data input_data input from the delay unit 43 to the second selector 47 is stopped. That is, after the non-signal mode signal abnormal_signal is input to the second selector 47 , the second selector 47 stops outputting the image data input_data during a period in which the second delay DE is inputted. . Next, when internal data internal_data is input to the second selector 47 after the vertical blank period, the second selector 47 outputs the internal data internal_data as output data output_data. Accordingly, the internal data (internal_data) is output to the data driver 3 in synchronization with the internal DE (internal_DE).

Here, the first and second selectors may be provided as multiplexers (MUX).

The non-signal detection unit 41 may include a counter (not shown) that counts the number of times the external DE is input. In the no-signal mode, the no-signal detection unit 41 counts the number of times the input DE is normally input by using a counter.

When the input DE(input_DE) is normally input one or more times (l is a natural number greater than or equal to 1) during the non-signal mode driving, the non-signal detection unit 41 stops outputting the non-signal mode signal abnormal_mode, and the timing controller (4) drive in normal mode. Here, the value of l may vary from as little as 1 to 5 to as much as 10 to 100 depending on the design.

Even when the timing controller 4 according to the present invention is driven in the no-signal mode, the delay is continued for a period corresponding to the time for applying the data voltage to all the horizontal lines of the display panel 1 within the frame at the time of the no-signal mode driving. DE(make_DE) is generated and output to the data driver 3 . Then, until the internal DE (internal_DE) and the internal data (internal_data) are output, the drive is performed in a vertical blank section. Accordingly, the timing controller 4 according to the present invention secures a sufficient vertical blank section even in a frame driven in the no-signal mode, and the frame in which the no-signal mode starts driving is also normally ended.

Therefore, the timing controller according to the present invention can secure a sufficient vertical blank section in the frame, and accordingly, the operation algorithm such as compensation of panel data and touch sensing or image data performed by the display device in the vertical blank section abnormally You can solve the problem you are doing.

Hereinafter, a method of driving the timing controller according to the present invention will be described.

In the normal mode, the timing controller 4 according to the present invention receives an input DE(input_DE), and the delay DE generating unit 42 generates a first delay DE delayed by n horizontal periods of the input DE(input_DE), , the first delay DE 42 is output to the delay unit 43 and the first selection unit 46 .

The delay unit 43 receives the first delay DE(make_DE) and the image data input_data, synchronizes the image data with the first delay DE(make_DE), and outputs it to the second selector 47 .

The first selector 46 outputs the first delay DE(make_DE) as an output DE(output_DE) to the data driver 3 , and the second selector 47 outputs the image data input_data as output data. (output_data) is outputted to the data driver 3 in synchronization with the first delay DE(make_DE).

4 is a waveform diagram illustrating waveforms of DE and image data output when the timing controller 4 is driven in a no-signal mode.

When the input DE(input_DE) is not input or an abnormal signal is input while the input DE(input_DE) is being input, the timing controller 4 drives in the no-signal mode.

For the non-signal mode driving, the non-signal detection unit 41 outputs a non-signal mode signal abnormal_signal. At this time, the non-signal mode signal (abnormal_signal) is transmitted to the delayed DE generating unit 42 , the internal DE generating unit 42 , the delay unit 43 , and the first and second selection units 46 and 47 . is output

The delay DE generator 42 responds to the non-signal mode signal abnormal_signal from the frame in which the non-signal mode is started until the period in which the data voltage corresponding to the last horizontal line of the display panel 1 is to be output. A second delay DE (make_DE_2) is generated based on the input DE (input_DE) and output to the delay unit 43 and the first selection unit 46 .

The delay unit 43 stops outputting image data when the non-signal mode signal abnormal_signal is input.

The internal DE generator 42 generates an internal DE (internal_DE) in response to the non-signal mode signal abnormal_signal, and outputs the internal DE (internal_DE) to the first selector 46 and the internal data generator 45 . do.

The internal data generator 45 generates internal data to be output to the display panel 1 in the no-signal mode and outputs the generated internal data to the second selector 47 . In this case, the internal data may be pre-stored data.

The first selector 46 receives a second delay until the data voltage corresponding to the last horizontal line of the display panel 1 is to be output in a frame to which the non-signal mode signal is input in response to the non-signal mode signal abnormal_signal After outputting DE, when an internal DE(internal_DE) is input after having a predetermined vertical blank period, the internal DE(internal_DE) is outputted to the data driver 3 as an output DE(output_DE).

At this time, the second selection unit 47 outputs the internal data in synchronization with the internal DE (internal_DE).

Here, the delay DE generator 42 latches the last input DE(input_DE) among the externally inputted inputs DE(input_DE), and then selects the latched input DE based on the falling edge of the last input DE. A second delay DE (make_DE_2) is generated as a reference. At this time, the maximum voltage level of the second delay DE (make_DE_2) is equal to the maximum voltage level of the latched input DE. Meanwhile, the delay DE generator 42 may determine the output period and period of the second delay DE by counting the external clock input from the outside or the internal clock generated by the timing controller 4 using the external clock.

On the other hand, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is a technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those with prior knowledge in

1: Display panel 2: Gate driver
3: Data Driver 4: Timing Controller
41: no signal detection unit 42: delay DE generation unit
43: delay unit 44: internal DE generating unit
45: internal data generating unit 46: first selection unit
47: second selection unit

Claims (8)

A timing controller for driving in a normal mode and a no-signal mode, aligning and outputting image data input from the outside in the normal mode, and controlling a display timing of the image data, the timing controller comprising:
A no-signal detection unit that analyzes an external DE input from the outside and outputs a no-signal mode signal for driving in a no-signal mode when the external DE is not input or an abnormal signal is detected;
generating a first delay DE delaying the outer DE, and in response to the no-signal mode signal, generating a second delay DE having the same pulse width as that of the outer DE based on a falling edge of the outer DE to generate the abnormal a delay DE generator for repeatedly outputting the second delay DE until a period in which output of all image data of a frame in which a signal is detected is completed;
and an internal DE generator for generating and outputting an internal DE while driving in the no-signal mode after a predetermined vertical blank period after the second delay DE is output. The method of claim 1,
a delay unit receiving the image data and outputting it in synchronization with the first delayed DE signal;
an internal data generating unit receiving the internal DE while driving in the no-signal mode and outputting internal data of a specific pattern synchronized with the internal DE;
One of the first and second delay DE and the internal DE are inputted and the second delay is delayed until a period in which output of all image data of a frame in which the abnormal signal is detected in response to the no-signal mode signal is completed. a first selector for outputting DE and outputting the internal DE from after the vertical blank section to a time point at which the external DE is normally input; and
Timing further comprising a second selector configured to stop outputting the image data until the vertical blank period in response to the no-signal mode and output the internal data from the vertical blank period to a point in time when driving in the normal mode again controller. 3. The method of claim 2,
The delay DE generation unit,
a latch unit outputting the second delay DE such that the maximum voltage level of the second delay DE becomes the latched voltage level in the no-signal mode after latching the voltage level when the external DE rises; and
By counting an external clock input from the outside or an internal clock generated using the external clock up to a preset m (m is the number of clock pulses input to reach 1 horizontal period), the clock pulse is used to count the first 2 Timing controller with a clock counter that sets the active period of delay DE. The method of claim 1,
The no-signal detection unit includes a counter for counting the number of times the input DE is input, and when the input DE is normally input one or more times (l is a natural number equal to or greater than 1) during the no-signal mode driving, the no-signal detection unit includes a counter Signal mode Timing controller to drive back to normal mode by stopping the output of the signal. Analyzing the external DE input from the outside and outputting a no-signal mode signal for driving in the no-signal mode when the external DE is not input or an abnormal signal is detected;
In response to the no-signal mode signal, a second delay DE having the same pulse width as that of the external DE is generated based on the falling edge of the external DE, and outputting of all image data of the frame in which the abnormal signal is detected is completed. repeatedly outputting the second delay DE until the
generating an internal DE and internal data by receiving the no-signal mode signal;
having a predetermined vertical blank period after the output of the second delay DE;
and outputting the internal DE and internal data after the vertical blank period. 6. The method of claim 5,
Outputting the second delay DE comprises:
After latching the voltage level when the external DE rises, the maximum voltage level of the second delay DE in the no-signal mode has the same voltage level as the latched voltage level, and an external clock input from the outside or A timing controller that sets the active period of the second delay DE using the clock pulse by counting the internal clock generated therein until a preset value of m (where m is the number of clock pulses input to reach 1 horizontal period) driving method. 7. The method of claim 6,
When the input DE is normally input one or more times during the no-signal mode driving, the output of the no-signal mode signal is stopped to drive the timing controller in the normal mode again. A display panel comprising: a display panel including a plurality of sub-pixels positioned in a matrix form in a region where a plurality of gate lines and data lines intersect;
a gate driver driving the gate line;
a data driver for driving the data line;
5 . The display device comprising any one of the timing controllers according to claim 1 , wherein the display device controls the display timing of image data inputted from the outside by driving the gate driver and the data driver.

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