KR102409024B1 - 네트워크 프로세서에서의 멀티-코어 상호접속 - Google Patents

네트워크 프로세서에서의 멀티-코어 상호접속 Download PDF

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KR102409024B1
KR102409024B1 KR1020197035633A KR20197035633A KR102409024B1 KR 102409024 B1 KR102409024 B1 KR 102409024B1 KR 1020197035633 A KR1020197035633 A KR 1020197035633A KR 20197035633 A KR20197035633 A KR 20197035633A KR 102409024 B1 KR102409024 B1 KR 102409024B1
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processor cores
banks
requests
cache
interconnect
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KR20190137948A (ko
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리차드 이. 케슬러
데이비드 에이치. 애셔
존 엠. 퍼베일러
브레들리 디. 도비
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마벨 아시아 피티이 엘티디.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
KR1020197035633A 2011-10-31 2012-10-29 네트워크 프로세서에서의 멀티-코어 상호접속 Active KR102409024B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13/285,629 US9330002B2 (en) 2011-10-31 2011-10-31 Multi-core interconnect in a network processor
US13/285,629 2011-10-31
PCT/US2012/062378 WO2013066798A1 (en) 2011-10-31 2012-10-29 Multi-core interconnect in a network processor
KR1020147012490A KR20140084155A (ko) 2011-10-31 2012-10-29 네트워크 프로세서에서의 멀티-코어 상호접속

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020147012490A Division KR20140084155A (ko) 2011-10-31 2012-10-29 네트워크 프로세서에서의 멀티-코어 상호접속

Publications (2)

Publication Number Publication Date
KR20190137948A KR20190137948A (ko) 2019-12-11
KR102409024B1 true KR102409024B1 (ko) 2022-06-14

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Application Number Title Priority Date Filing Date
KR1020197035633A Active KR102409024B1 (ko) 2011-10-31 2012-10-29 네트워크 프로세서에서의 멀티-코어 상호접속
KR1020147012490A Ceased KR20140084155A (ko) 2011-10-31 2012-10-29 네트워크 프로세서에서의 멀티-코어 상호접속

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KR1020147012490A Ceased KR20140084155A (ko) 2011-10-31 2012-10-29 네트워크 프로세서에서의 멀티-코어 상호접속

Country Status (6)

Country Link
US (1) US9330002B2 (enExample)
JP (2) JP2014534529A (enExample)
KR (2) KR102409024B1 (enExample)
CN (1) CN103959261B (enExample)
DE (1) DE112012004551B4 (enExample)
WO (1) WO2013066798A1 (enExample)

Families Citing this family (14)

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Publication number Priority date Publication date Assignee Title
US9892063B2 (en) * 2012-11-27 2018-02-13 Advanced Micro Devices, Inc. Contention blocking buffer
US9652396B2 (en) 2013-12-27 2017-05-16 Samsung Electronics Co., Ltd. Cache element processing for energy use reduction
US9811467B2 (en) * 2014-02-03 2017-11-07 Cavium, Inc. Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor
US9432288B2 (en) 2014-02-28 2016-08-30 Cavium, Inc. System on chip link layer protocol
US9411644B2 (en) 2014-03-07 2016-08-09 Cavium, Inc. Method and system for work scheduling in a multi-chip system
US9372800B2 (en) 2014-03-07 2016-06-21 Cavium, Inc. Inter-chip interconnect protocol for a multi-chip system
US10592459B2 (en) * 2014-03-07 2020-03-17 Cavium, Llc Method and system for ordering I/O access in a multi-node environment
US9529532B2 (en) 2014-03-07 2016-12-27 Cavium, Inc. Method and apparatus for memory allocation in a multi-node system
US9436972B2 (en) * 2014-03-27 2016-09-06 Intel Corporation System coherency in a distributed graphics processor hierarchy
US10235203B1 (en) * 2014-03-31 2019-03-19 EMC IP Holding Company LLC Techniques for increasing storage system performance in processor-bound workloads with large working sets and poor spatial locality
US10740236B2 (en) 2017-05-12 2020-08-11 Samsung Electronics Co., Ltd Non-uniform bus (NUB) interconnect protocol for tiled last level caches
US10592452B1 (en) 2018-09-12 2020-03-17 Cavium, Llc Low latency interconnect protocol for coherent multi-chip communication
US11442868B2 (en) * 2019-05-24 2022-09-13 Texas Instruments Incorporated Aggressive write flush scheme for a victim cache
US11899585B2 (en) * 2021-12-24 2024-02-13 Western Digital Technologies, Inc. In-kernel caching for distributed cache

Citations (3)

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JP2002149353A (ja) * 2000-11-08 2002-05-24 Nec Corp ディスクアレイ制御装置及びディスクアレイ制御方法
WO2005020079A2 (en) * 2003-08-19 2005-03-03 Sun Microsystems, Inc. Cache crossbar arbitration
US20060059316A1 (en) * 2004-09-10 2006-03-16 Cavium Networks Method and apparatus for managing write back cache

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JPS58220287A (ja) * 1982-06-15 1983-12-21 Nec Corp メモリアクセス制御装置
US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
JP4240610B2 (ja) * 1998-11-27 2009-03-18 株式会社日立製作所 計算機システム
US7248585B2 (en) * 2001-10-22 2007-07-24 Sun Microsystems, Inc. Method and apparatus for a packet classifier
US7873785B2 (en) * 2003-08-19 2011-01-18 Oracle America, Inc. Multi-core multi-thread processor
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US7606998B2 (en) * 2004-09-10 2009-10-20 Cavium Networks, Inc. Store instruction ordering for multi-core processor
US20060112226A1 (en) * 2004-11-19 2006-05-25 Hady Frank T Heterogeneous processors sharing a common cache
US7477641B2 (en) * 2004-12-30 2009-01-13 Intel Corporation Providing access to data shared by packet processing threads
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JP2002149353A (ja) * 2000-11-08 2002-05-24 Nec Corp ディスクアレイ制御装置及びディスクアレイ制御方法
WO2005020079A2 (en) * 2003-08-19 2005-03-03 Sun Microsystems, Inc. Cache crossbar arbitration
US20060059316A1 (en) * 2004-09-10 2006-03-16 Cavium Networks Method and apparatus for managing write back cache

Also Published As

Publication number Publication date
KR20190137948A (ko) 2019-12-11
JP2018045700A (ja) 2018-03-22
KR20140084155A (ko) 2014-07-04
CN103959261A (zh) 2014-07-30
JP6676027B2 (ja) 2020-04-08
US20130111141A1 (en) 2013-05-02
DE112012004551T5 (de) 2014-08-14
WO2013066798A1 (en) 2013-05-10
US9330002B2 (en) 2016-05-03
CN103959261B (zh) 2019-06-21
JP2014534529A (ja) 2014-12-18
DE112012004551B4 (de) 2024-08-08

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