JP6676027B2 - ネットワークプロセッサにおけるマルチコア相互接続 - Google Patents
ネットワークプロセッサにおけるマルチコア相互接続 Download PDFInfo
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- JP6676027B2 JP6676027B2 JP2017213851A JP2017213851A JP6676027B2 JP 6676027 B2 JP6676027 B2 JP 6676027B2 JP 2017213851 A JP2017213851 A JP 2017213851A JP 2017213851 A JP2017213851 A JP 2017213851A JP 6676027 B2 JP6676027 B2 JP 6676027B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G—PHYSICS
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Description
Claims (8)
- 相互接続回路と、
複数のメモリバスであって、各メモリバスが、複数のプロセッサコアの群のそれぞれを前記相互接続回路に接続する、複数のメモリバスと、
複数のバンクに分割されるキャッシュであって、各バンクは、個々のバスを介して前記相互接続回路に接続される、キャッシュとを備えた、コンピュータチップ上のコンピュータシステムであって、
前記相互接続回路が、前記複数のプロセッサコアの群から受信される複数の要求を前記複数のバンクに分配し、
前記相互接続回路が、前記要求のそれぞれにハッシュ関数を実行し、このハッシュ関数が、前記複数のバンクへの前記要求の疑似ランダム分配を提供し、
前記相互接続回路及び前記複数のメモリバスは、前記相互接続回路からのコミット信号が前記複数のバンクの1つに到達するため、かつ、前記コミット信号に続く前記相互接続回路からの信号が無効化信号を受信する前記複数のプロセッサコアの群の1つに到達するために必要な時間未満で前記複数のプロセッサコアの群の1つに結合された1次キャッシュに到達するように、前記相互接続回路からの無効化信号を制御する
コンピュータシステム。 - 前記相互接続回路が、前記要求のアドレスコンポーネントを変更することによって前記要求を変換する、請求項1に記載のシステム。
- 前記相互接続回路は、前記複数のプロセッサコアの群の1つに結合された1次キャッシュの状態を示すタグを保持し、前記相互接続回路は、前記複数の要求のタグを複数のチャネルに誘導し、これにより、前記各タグを同時に処理する、請求項1に記載のシステム。
- 前記相互接続回路は、複数のデータ出力バッファを更に備え、前記データ出力バッファのそれぞれは、前記複数のバンクのそれぞれからデータを受信し、前記複数のメモリバスのそれぞれ1つを通してデータを出力する、請求項1に記載のシステム。
- 前記相互接続回路は、複数の要求バッファを更に備え、前記要求バッファのそれぞれは、複数のプロセッサの各群から要求を受信し、前記要求を前記複数のバンクの1つに出力する、請求項1に記載のシステム。
- 前記メモリバスのうちの少なくとも1つに結合された少なくとも1つのブリッジ回路を更に備え、当該少なくとも1つのブリッジ回路は、前記複数のプロセッサコアの群を少なくとも1つのオンチップコプロセッサに接続する、請求項1に記載のシステム。
- 前記バンクは、前記複数のプロセッサコアの群へのコミット信号の送信を遅延させるものであり、前記バンクは、無効化信号が前記複数のプロセッサコアの群全てに送信されたことの表明の受信に応答して、前記コミット信号を送信する、請求項1に記載のシステム。
- 前記キャッシュは2次キャッシュである、請求項1に記載のシステム。
Applications Claiming Priority (2)
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US13/285,629 | 2011-10-31 | ||
US13/285,629 US9330002B2 (en) | 2011-10-31 | 2011-10-31 | Multi-core interconnect in a network processor |
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JP2014539104A Division JP2014534529A (ja) | 2011-10-31 | 2012-10-29 | ネットワークプロセッサにおけるマルチコア相互接続 |
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JP2018045700A JP2018045700A (ja) | 2018-03-22 |
JP6676027B2 true JP6676027B2 (ja) | 2020-04-08 |
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JP2014539104A Pending JP2014534529A (ja) | 2011-10-31 | 2012-10-29 | ネットワークプロセッサにおけるマルチコア相互接続 |
JP2017213851A Active JP6676027B2 (ja) | 2011-10-31 | 2017-11-06 | ネットワークプロセッサにおけるマルチコア相互接続 |
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US (1) | US9330002B2 (ja) |
JP (2) | JP2014534529A (ja) |
KR (2) | KR102409024B1 (ja) |
CN (1) | CN103959261B (ja) |
DE (1) | DE112012004551T5 (ja) |
WO (1) | WO2013066798A1 (ja) |
Families Citing this family (12)
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US9652396B2 (en) | 2013-12-27 | 2017-05-16 | Samsung Electronics Co., Ltd. | Cache element processing for energy use reduction |
US9811467B2 (en) * | 2014-02-03 | 2017-11-07 | Cavium, Inc. | Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor |
US9432288B2 (en) | 2014-02-28 | 2016-08-30 | Cavium, Inc. | System on chip link layer protocol |
US10592459B2 (en) * | 2014-03-07 | 2020-03-17 | Cavium, Llc | Method and system for ordering I/O access in a multi-node environment |
US9529532B2 (en) * | 2014-03-07 | 2016-12-27 | Cavium, Inc. | Method and apparatus for memory allocation in a multi-node system |
US9411644B2 (en) | 2014-03-07 | 2016-08-09 | Cavium, Inc. | Method and system for work scheduling in a multi-chip system |
US9372800B2 (en) | 2014-03-07 | 2016-06-21 | Cavium, Inc. | Inter-chip interconnect protocol for a multi-chip system |
US9436972B2 (en) * | 2014-03-27 | 2016-09-06 | Intel Corporation | System coherency in a distributed graphics processor hierarchy |
US10235203B1 (en) * | 2014-03-31 | 2019-03-19 | EMC IP Holding Company LLC | Techniques for increasing storage system performance in processor-bound workloads with large working sets and poor spatial locality |
US10740236B2 (en) * | 2017-05-12 | 2020-08-11 | Samsung Electronics Co., Ltd | Non-uniform bus (NUB) interconnect protocol for tiled last level caches |
US10592452B1 (en) | 2018-09-12 | 2020-03-17 | Cavium, Llc | Low latency interconnect protocol for coherent multi-chip communication |
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- 2011-10-31 US US13/285,629 patent/US9330002B2/en active Active
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- 2012-10-29 DE DE112012004551.3T patent/DE112012004551T5/de active Granted
- 2012-10-29 WO PCT/US2012/062378 patent/WO2013066798A1/en active Application Filing
- 2012-10-29 JP JP2014539104A patent/JP2014534529A/ja active Pending
- 2012-10-29 KR KR1020197035633A patent/KR102409024B1/ko active IP Right Grant
- 2012-10-29 CN CN201280059239.5A patent/CN103959261B/zh active Active
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Publication number | Publication date |
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DE112012004551T5 (de) | 2014-08-14 |
KR20190137948A (ko) | 2019-12-11 |
JP2014534529A (ja) | 2014-12-18 |
JP2018045700A (ja) | 2018-03-22 |
KR20140084155A (ko) | 2014-07-04 |
US9330002B2 (en) | 2016-05-03 |
US20130111141A1 (en) | 2013-05-02 |
CN103959261B (zh) | 2019-06-21 |
WO2013066798A1 (en) | 2013-05-10 |
KR102409024B1 (ko) | 2022-06-14 |
CN103959261A (zh) | 2014-07-30 |
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