CN103959261B - 网络处理器中的多内核互联 - Google Patents

网络处理器中的多内核互联 Download PDF

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Publication number
CN103959261B
CN103959261B CN201280059239.5A CN201280059239A CN103959261B CN 103959261 B CN103959261 B CN 103959261B CN 201280059239 A CN201280059239 A CN 201280059239A CN 103959261 B CN103959261 B CN 103959261B
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China
Prior art keywords
processor cores
cache
data
request
interconnection circuit
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CN201280059239.5A
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Chinese (zh)
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CN103959261A (zh
Inventor
R·E·凯斯勒
D·H·阿舍
J·M·珀维勒
B·D·多比
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Kaiwei International Co
Marvell Asia Pte Ltd
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Kaiwei LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
CN201280059239.5A 2011-10-31 2012-10-29 网络处理器中的多内核互联 Active CN103959261B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/285,629 2011-10-31
US13/285,629 US9330002B2 (en) 2011-10-31 2011-10-31 Multi-core interconnect in a network processor
PCT/US2012/062378 WO2013066798A1 (en) 2011-10-31 2012-10-29 Multi-core interconnect in a network processor

Publications (2)

Publication Number Publication Date
CN103959261A CN103959261A (zh) 2014-07-30
CN103959261B true CN103959261B (zh) 2019-06-21

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CN201280059239.5A Active CN103959261B (zh) 2011-10-31 2012-10-29 网络处理器中的多内核互联

Country Status (6)

Country Link
US (1) US9330002B2 (enExample)
JP (2) JP2014534529A (enExample)
KR (2) KR102409024B1 (enExample)
CN (1) CN103959261B (enExample)
DE (1) DE112012004551B4 (enExample)
WO (1) WO2013066798A1 (enExample)

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US9892063B2 (en) * 2012-11-27 2018-02-13 Advanced Micro Devices, Inc. Contention blocking buffer
US9652396B2 (en) 2013-12-27 2017-05-16 Samsung Electronics Co., Ltd. Cache element processing for energy use reduction
US9811467B2 (en) * 2014-02-03 2017-11-07 Cavium, Inc. Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor
US9432288B2 (en) 2014-02-28 2016-08-30 Cavium, Inc. System on chip link layer protocol
US10592459B2 (en) * 2014-03-07 2020-03-17 Cavium, Llc Method and system for ordering I/O access in a multi-node environment
US9372800B2 (en) 2014-03-07 2016-06-21 Cavium, Inc. Inter-chip interconnect protocol for a multi-chip system
US9411644B2 (en) 2014-03-07 2016-08-09 Cavium, Inc. Method and system for work scheduling in a multi-chip system
US9529532B2 (en) * 2014-03-07 2016-12-27 Cavium, Inc. Method and apparatus for memory allocation in a multi-node system
US9436972B2 (en) * 2014-03-27 2016-09-06 Intel Corporation System coherency in a distributed graphics processor hierarchy
US10235203B1 (en) * 2014-03-31 2019-03-19 EMC IP Holding Company LLC Techniques for increasing storage system performance in processor-bound workloads with large working sets and poor spatial locality
US10740236B2 (en) * 2017-05-12 2020-08-11 Samsung Electronics Co., Ltd Non-uniform bus (NUB) interconnect protocol for tiled last level caches
US10592452B1 (en) 2018-09-12 2020-03-17 Cavium, Llc Low latency interconnect protocol for coherent multi-chip communication
US11442868B2 (en) * 2019-05-24 2022-09-13 Texas Instruments Incorporated Aggressive write flush scheme for a victim cache

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CN101221551A (zh) * 2007-01-09 2008-07-16 国际商业机器公司 用于对称多处理器互连的方法和设备以及多处理器
CN101470691A (zh) * 2004-11-19 2009-07-01 英特尔公司 共享公共高速缓存的异构处理器
CN101572726A (zh) * 2008-05-01 2009-11-04 英特尔公司 在基于多处理器网格的系统中用于分层路由的方法和装置
CN101593159A (zh) * 2008-05-30 2009-12-02 英特尔公司 使用关键度信息来路由高速缓存一致性通信

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US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
JP4240610B2 (ja) * 1998-11-27 2009-03-18 株式会社日立製作所 計算機システム
JP2002149353A (ja) * 2000-11-08 2002-05-24 Nec Corp ディスクアレイ制御装置及びディスクアレイ制御方法
US7248585B2 (en) * 2001-10-22 2007-07-24 Sun Microsystems, Inc. Method and apparatus for a packet classifier
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Patent Citations (4)

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CN101470691A (zh) * 2004-11-19 2009-07-01 英特尔公司 共享公共高速缓存的异构处理器
CN101221551A (zh) * 2007-01-09 2008-07-16 国际商业机器公司 用于对称多处理器互连的方法和设备以及多处理器
CN101572726A (zh) * 2008-05-01 2009-11-04 英特尔公司 在基于多处理器网格的系统中用于分层路由的方法和装置
CN101593159A (zh) * 2008-05-30 2009-12-02 英特尔公司 使用关键度信息来路由高速缓存一致性通信

Also Published As

Publication number Publication date
CN103959261A (zh) 2014-07-30
DE112012004551B4 (de) 2024-08-08
JP2018045700A (ja) 2018-03-22
JP2014534529A (ja) 2014-12-18
US9330002B2 (en) 2016-05-03
US20130111141A1 (en) 2013-05-02
KR20140084155A (ko) 2014-07-04
KR20190137948A (ko) 2019-12-11
KR102409024B1 (ko) 2022-06-14
WO2013066798A1 (en) 2013-05-10
JP6676027B2 (ja) 2020-04-08
DE112012004551T5 (de) 2014-08-14

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