KR102404843B1 - Light emitting, power generating or other electronic apparatus and method of manufacturing same - Google Patents

Abstract

An exemplary printable composition of a liquid or gel suspension of diodes includes a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary apparatus includes a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. Various exemplary diodes have a lateral dimension of about 10-50 μm and a height of about 5-25 μm. Other aspects may also include a plurality of substantially chemically inert particles having a size range from about 10 to about 50 μm.

Description

LIGHT EMITTING, POWER GENERATING OR OTHER ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING SAME

Copyright notice and permission

Some of the disclosures of this patent document contain matters subject to copyright protection. The copyright owner does not object to any copying of this patent document or the patent disclosure as it appears in the Patent Office patent files or records, but retains the copyright in all other respects. The following notice applies to this document and the following data, content and drawings thereto: Copyright © 2010-2011, NthDegree Technologies Worldwide, Inc. All rights reserved.

Cross-referencing of related applications

This application is a conversion of and priority to U.S. Provisional Patent Application Serial No. 61/379,225, filed September 1, 2010, to William Johnstone Ray et al. entitled "Printable Composition of a Liquid or Gel Suspension of Diodes" claiming that this application is assigned to the general public, the entire contents of which are hereby incorporated by reference with the same effect as if set forth in their entirety and with priority to all generally disclosed subject matter.

This application is a diversion and claims priority to U.S. Provisional Patent Application Serial No. 61/379,284, filed September 1, 2010, by William Johnstone Ray et al. entitled "Light Emitting, Photovoltaic and Other Electronic Apparatus" and, this application is assigned to the general public, the entire contents of which are hereby incorporated by reference together with the priority claimed to all generally disclosed subject matter with the same effect as set forth in its entirety.

This application relates to U.S. Provisional Patent Application No. 61/379,830, filed September 3, 2010 (inventor: William Johnstone Ray et al., entitled "Printable Composition of a Liquid ot Gel Suspension of Diodes and Method of Making Same"). Conversion and priority thereto, this application is commonly assigned, the entire contents of which are hereby incorporated by reference together with priority to all generally disclosed subject matter with the same effect as set forth in its entirety.

This application is a diversion of and claims priority to U.S. Provisional Patent Application Serial No. 61/379,820, filed September 3, 2010 by William Johnstone Ray et al. entitled "Light Emitting, Photovoltaic and Other Electronic Apparatus" and, this application is assigned to the general public, the entire contents of which are hereby incorporated by reference together with the priority claimed to all generally disclosed subject matter with the same effect as set forth in its entirety.

This application is a continuation-in-part of U.S. Patent Application Serial No. 11/756,616 (inventor: William Johnstone Ray et al., entitled "Method of Manufacturing Addressable and Static Electronic Displays"), filed on May 31, 2007, and has priority thereto Claims, this application is assigned to the general public, the entire contents of which are hereby incorporated by reference together with the priority claimed to all generally disclosed subject matter with the same effect as set forth in its entirety.

This application is a portion of U.S. Patent Application Serial No. 12/601,268, filed November 22, 2009, by William Johnstone Ray et al. entitled "Method of Manufacturing Addressable and Static Electronic Displays, Power Generating and Other Electronic Apparatus" This is a serial application and claims priority thereto, which is filed on May 31, 2007 in U.S. Patent Application Serial No. 11/756,616 by William Johnstone Ray et al. entitled "Method of Manufacturing Addressable and Static Electronic Displays" ), and claims priority thereto, and also claims priority to U.S. Patent Application Serial No. 11/756,616, filed on May 31, 2007, an international application filed on May 30, 2008 35 U.S.C. in PCT/US2008/65237 (inventor: William Johnstone Ray et al., titled "Method of Manufacturing Addressable and Static Electronic Displays, Power Generating and Other Electronic Apparatus"). This is a U.S. national stage application under Section 371 and claims priority thereto, which applications are commonly assigned, the entire contents of which are herein incorporated by reference, with priority asserted to all generally disclosed subject matter, having the same effect as set forth in its entirety. is incorporated by reference in

This application is also a continuation-in-part of U.S. Patent Application Serial No. 13/149,681, filed May 31, 2011 by William Johnstone Ray et al. entitled "Addressable or Static Light Emitting or Electronic Apparatus" Priority is claimed, and this application is filed on May 31, 2007, and in U.S. Patent Application Serial No. 11/756,619, issued July 5, 2011, as U.S. Patent No. US 7,972,031 B2 by William Johnstone Ray et al., entitled : "Addressable or Static Light Emitting or Electronic Apparatus"), claiming priority thereto, in part successive applications, all of which are assigned to the general public, the entire content of which has the same effect as set forth in its entirety and to all generally disclosed subject matter This specification is incorporated herein by reference with the priority claimed to it.

This application is a continuation-in-part of U.S. Patent Application Serial No. 12/601,271, filed on November 22, 2009 (inventor: William Johnstone Ray et al., entitled "Addressable or Static Light Emitting, Power Generating or Other Electronic Apparatus") Priority is claimed thereto, and this application is a portion of US Patent Application Serial No. 11/756,619, filed May 31, 2007 (inventor: William Johnstone Ray et al., entitled "Addressable or Static Light Emitting or Electronic Apparatus"). International Application Serial No. PCT/US2008, filed May 30, 2008, claiming priority thereto, and claiming priority to U.S. Patent Application Serial No. 11/756,619, filed May 31, 2007 /65230 (inventor: William Johnstone Ray et al., titled "Addressable or Static Light Emitting, Power Generating or Other Electronic Apparatus"), 35 U.S.C. This is a U.S. national stage application under Section 371 and claims priority thereto, which applications are commonly assigned, the entire contents of which are herein incorporated by reference, with priority asserted to all generally disclosed subject matter, having the same effect as set forth in its entirety. is incorporated by reference in

This application also applies to the following patent applications: (1) U.S. Patent Application Serial No. 13/223,279, filed August 31, 2011 by Mark D. Lowenthal et al. entitled "Printable Composition of a Liquid or Gel Suspension of Diodes"); (2) U.S. Patent Application Serial No. 13/223,289, filed August 31, 2011 by Mark D. Lowenthal et al. entitled "Light Emitting, Power Generating or Other Electronic Apparatus"; (3) U.S. Patent Application Serial No. 13/223,286, filed August 31, 2011 by Mark D. Lowenthal et al. entitled "Method of Manufacturing a Printable Composition of a Liquid or Gel Suspension of Diodes"; (4) US Patent Application Serial No. 13/223,293, filed on August 31, 2011 by Mark D. Lowenthal et al. entitled "Method of Manufacturing a Light Emitting, Power Generating or Other Electronic Apparatus"; (5) U.S. Patent Application Serial No. 13/223,294, filed August 31, 2011 by Mark D. Lowenthal et al. entitled "Diode For a Printable Composition"; (6) U.S. Patent Application Serial No. 13/223,297, filed August 31, 2011 by Mark D. Lowenthal et al. entitled "Diode For a Printable Composition"; and (7) U.S. Patent Application Serial No. 13/223,302, filed on August 31, 2011 by Mark D. Lowenthal et al. entitled "Printable Composition of a Liquid or Gel Suspension of Two-Terminal Integrated Circuits and Apparatus" ) is a continuation application and claims priority thereto, these applications being commonly assigned, the entire contents of which are hereby incorporated by reference herein together with the priority claimed to all generally disclosed subject matter having the same effect as set forth in its entirety. are cited

technical field

FIELD OF THE INVENTION The present invention relates generally to light-emitting and photovoltaic technology, and more particularly, to compositions of light-emitting or photovoltaic diodes or other two-terminal integrated circuits suspended in liquid or gel and printable; and to a method of making a composition of a light emitting, photovoltaic or other diode or two-terminal integrated circuit suspended in a liquid or gel.

Lighting devices with light emitting diodes (“LEDs”) typically require fabrication of the LEDs on semiconductor wafers using integrated circuit process steps. The obtained LED is substantially flat and is relatively large with a width of about 200 mu m or more. Each of these LEDs is typically a two-terminal device with two metal terminals on the same side of the LED, typically to provide ohmic contact for the p-type and n-type portions of the LED. The LED wafer is then divided into individual LEDs, typically through a mechanical process such as sawing. The individual LEDs are then placed in a reflective casing and a bonding wire is individually attached to each of the two metal terminals of the LED. Because this process is time consuming, labor intensive and expensive, the LED-based lighting devices produced are generally too expensive for many consumer applications.

Similarly, energy generating devices, such as photovoltaic panels, also typically require the fabrication of photovoltaic diodes on semiconductor wafers or other substrates using integrated circuit process steps. The obtained wafer or other substrate is then packaged and assembled to manufacture a photovoltaic panel. Because this process is also time consuming, labor intensive, and expensive, the photovoltaic devices produced are too expensive for widespread use, without third party subsidies or other government subsidies.

Many techniques are being tried to fabricate new types of diodes or other semiconductor devices for light emitting or energy generating purposes. For example, it has been proposed that a graphic can be formed by printing quantum dots that are functionalized or capped by organic molecules to be miscible with an organic resin and solvent, and that the graphic emits light when pumped with a second light. A number of approaches for device formation are also being practiced, using semiconductor nanoparticles, such as particles in the range of about 1.0 nm to about 100 nm (1/10 μm). Another approach uses a larger-scale silicon powder dispersed in a solvent-binder carrier, and a colloidal suspension of the resulting silicon powder is used to form the active layer in a printed transistor. Another different approach uses very flat AlInGaP LED structures formed on a GaAs wafer, each LED having a breakaway photoresist anchor to each of two neighboring LEDs on the wafer, each The LEDs are then picked and placed to form the final device.

Other approaches have been to "lock and key" fluid self-assembly by placing trapezoidal diodes in a solvent and then pouring them onto a substrate with matching trapezoidal apertures, holding the trapezoidal diodes in place. is using However, trapezoidal diodes in the solvent are not suspended and dispersed in the solvent. Instead, the trapezoidal diodes precipitate quickly, becoming aggregates of diodes that adhere to each other, unable to be maintained in suspension or dispersed in the solvent, and require active sonication or agitation immediately prior to use. These trapezoidal diodes in solvent cannot be used as diode-based inks for storage, packaging or other use as inks, nor are they suitable for printing process applications.

Neither of these approaches use a liquid or gel containing a two-terminal integrated circuit or other semiconductor device (the two-terminal integrated circuit or other semiconductor device is in fact dispersed and suspended in the liquid or gel medium, e.g. For example, to form an ink, the two-terminal integrated circuit is suspended as a particle, the semiconductor device is complete and functional, and can be formed into an apparatus or system in a non-inert atmospheric environment using a printing process) .

LED-based devices and photovoltaic devices according to these recent developments in diode-based technology are still too complex and expensive to achieve commercial practicality. Consequently, there is a need for a light emitting and/or photovoltaic device designed to be less expensive in terms of inserted members and ease of manufacture. There is also a need for a method of producing LED-based lighting devices and photovoltaic panels that allows for widespread use and adoption by consumers and commerce by manufacturing such light emitting or photovoltaic devices using less expensive and more robust processes. . Thus, liquid or gel suspensions of fully functional diodes or other two-terminal integrated circuits that can be printed to make LED-based devices and photovoltaic devices, printing to make these LED-based devices and photovoltaic devices Various needs exist for methods, and final printed LED-based devices and photovoltaic devices.

The exemplary embodiments provide liquid or gel suspensions and dispersions of “diode ink”, i.e., diodes or other two-terminal integrated circuits that can be printed via screen printing or flexographic printing, for example. do. As described in more detail below, the diodes themselves, prior to inclusion in the diode ink composition, can function to emit light when energized (if implemented as an LED) or (implemented as a photovoltaic diode). completed semiconductor devices that can function to provide power when exposed to a light source. The exemplary method also includes a method of making a diode ink by dispersing and suspending a plurality of diodes in a solvent and a viscous resin or polymer mixture, as discussed in more detail below, by printing the diode ink to print the diode-based device. and photovoltaic devices. Exemplary devices and systems formed by printing such diode inks are also described.

While the present disclosure focuses on a two-terminal integrated circuit type of diode, those skilled in the art will recognize that other types of semiconductor devices can be equally substituted to form what is more broadly referred to as "semiconductor device ink". It will be appreciated that all such modifications are equivalent and are within the scope of this disclosure. Thus, no reference to “diode” herein is made using any two-terminal integrated circuit of any kind, such as resistors, inductors, capacitors, RFID circuits, sensors, piezoelectric devices, etc., and using two terminals or electrodes. It will be understood to mean and include any other integrated circuit capable of operating.

An exemplary aspect includes a plurality of diodes; a first solvent; and a viscosity modifier.

In an exemplary embodiment, the first solvent is water; Alcohols such as methanol, ethanol, N-propanol (including 1-propanol, 2-propanol (isopropanol), 1-methoxy-2-propanol), butanol (1-butanol, 2-butanol (isobutanol) ), pentanol (including 1-pentanol, 2-pentanol, 3-pentanol), octanol, N-octanol (including 1-octanol, 2-octanol, 3-octanol) , tetrahydrofurfuryl alcohol, cyclohexanol, terpineol; ethers such as methyl ethyl ether, diethyl ether, ethyl propyl ether, and polyethers; esters such as ethyl acetate, dimethyl adipate, propylene glycol monomethyl ether acetate, dimethyl glutarate, dimethyl succinate, glycerin acetate; glycols such as ethylene glycol, diethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol, glycol ethers, glycol ether acetates; carbonates such as propylene carbonate; glycerol such as glycerin; acetonitrile, tetrahydrofuran (THF), dimethyl formamide (DMF), N-methyl formamide (NMF), dimethyl sulfoxide (DMSO); and at least one solvent selected from the group consisting of mixtures thereof. The first solvent may be present, for example, in an amount of about 0.3% to 50% by weight or 60% by weight.

In various exemplary aspects, each diode of the plurality of diodes has a diameter of about 20-30 μm and a height of about 5-15 μm; have a diameter of about 10-50 μm and a height of about 5-25 μm; each having a width and a length of about 10 to 50 μm and a height of about 5 to 25 μm; Each has a width and a length of about 20 to 30 μm and a height of about 5 to 15 μm. The plurality of diodes may be, for example, a light emitting diode or a photovoltaic diode.

The exemplary composition may further comprise a plurality of substantially optically clear and chemically inert particles having a size range of from about 10 to about 50 μm and present in an amount of from about 0.1% to about 2.5% by weight. Another exemplary composition may further comprise a plurality of substantially optically clear and chemically inert particles having a size range of about 10 to about 30 μm and present in an amount of about 0.1% to 2.5% by weight. .

In an exemplary embodiment, the viscosity modifier is a clay, eg, hectorite clay, garamite clay, organo-modified clay; saccharides and polysaccharides such as guar gum, xanthan gum; Cellulose and modified celluloses such as hydroxy methylcellulose, methylcellulose, ethyl cellulose, propyl methylcellulose, methoxy cellulose, methoxy methylcellulose, methoxy propyl methylcellulose, hydroxy propyl methylcellulose, carboxymethylcellulose, hydroxy ethylcellulose, ethyl hydroxyl ethylcellulose, cellulose ether, cellulose ethyl ether, chitosan; polymers such as acrylate and (meth)acrylate polymers and copolymers; glycols such as ethylene glycol, diethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol, glycol ethers, glycol ether acetates; Fumed silica, silica powder; modified urea; and at least one viscosity modifier selected from the group consisting of mixtures thereof. The viscosity modifier may be present, for example, in an amount of about 0.30 wt% to 5 wt%, or about 0.10 wt% to 3 wt%.

The composition may further include a second solvent different from the first solvent. The second solvent is present, for example, in an amount of about 0.1% to 60% by weight.

In an exemplary embodiment, the first solvent is N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol or cyclo hexanol or mixtures thereof, and is present in an amount from about 5% to 50% by weight; the viscosity modifier comprises a methoxy propyl methylcellulose resin or a hydroxy propyl methylcellulose resin or a mixture thereof and is present in an amount of about 0.10% to 5.0% by weight; The second solvent is N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol or cyclohexanol or their admixture, and is present in an amount of from about 0.3% to 50% by weight.

In another exemplary embodiment, the first solvent is N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol or cyclohexanol or mixtures thereof, present in an amount of about 5% to 30% by weight; the viscosity modifier comprises a methoxy propyl methylcellulose resin or a hydroxy propyl methylcellulose resin or a mixture thereof and is present in an amount of about 1.0% to 3.0% by weight; The second solvent is N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol or cyclohexanol or their admixture and present in an amount of from about 0.2% to 8.0% by weight; The remainder of the composition further comprises water.

In another exemplary embodiment, the first solvent is N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol or cyclohexanol or mixtures thereof, present in an amount of about 40% to 60% by weight; the viscosity modifier comprises a methoxy propyl methylcellulose resin or a hydroxy propyl methylcellulose resin or a mixture thereof and is present in an amount of about 0.10% to 1.5% by weight; The second solvent is N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol or cyclohexanol or their mixture, and is present in an amount of about 40% to 60% by weight.

An exemplary method of making the composition comprises: mixing the plurality of diodes with the first solvent; adding the mixture of the first solvent and the plurality of diodes to the viscosity modifier; adding the second solvent; It may include mixing the plurality of diodes, the first solvent, the second solvent, and the viscosity modifier in the air for about 25 to 30 minutes. The exemplary method may further include releasing the plurality of diodes from the wafer, wherein releasing the plurality of diodes from the wafer comprises, for example, etching the back side of the wafer or grinding and polishing the backside, or laser lift-off from the backside of the wafer.

In various exemplary embodiments, the composition comprises substantially from about 50 cps to about 25,000 cps at about 25° C., or from about 100 cps to about 25,000 cps at about 25° C., or from about 1,000 cps to about 10,000 cps at about 25° C., or about It has a viscosity of about 10,000 cps to about 25,000 cps at 25°C.

In various exemplary aspects, each diode of the plurality of diodes may comprise GaN, wherein the GaN portion of each diode of the plurality of diodes is substantially hexagonal, square, triangular, rectangular, lobed ), stellate or toroidal. In an exemplary aspect, the light emitting or light absorbing area of each diode of the plurality of diodes is a group consisting of a plurality of circular rings, a plurality of substantially curved trapezoids, a plurality of parallel stripes, a radial pattern, and combinations thereof. It may have a surface texture selected from

In an exemplary aspect, each diode of the plurality of diodes has a first metal terminal on a first side of the diode and a second metal terminal on a second, back side of the diode, wherein the first and first The two terminals each have a height of about 1 to 6 mu m. In another exemplary aspect, each diode of the plurality of diodes has a diameter of about 20-30 μm and a height of 5-15 μm, and wherein each diode of the plurality of diodes has a first a plurality of metal terminals and one second metal terminal on the first surface, wherein a contact portion of the second metal terminal is about 2 to 5 μm in height dimension from the contact portions of the first plurality of metal terminals. far enough away In an exemplary embodiment, each of the first metal terminals of the first plurality of metal terminals has a height of about 0.5 to 2 μm, and the second metal terminal has a height of about 1 to 8 μm. In another exemplary aspect, each diode of the plurality of diodes has a diameter of about 10-50 μm and a height of 5-25 μm, and wherein each diode of the plurality of diodes has a first a plurality of metal terminals and one second metal terminal on the first surface, wherein the contact portion of the second metal terminal is about 1 to 7 μm in height dimension from the contact portions of the first plurality of metal terminals. far enough away

In another exemplary aspect, each diode of the plurality of diodes has at least one metal via structure extending from at least one p+ or n+ GaN layer on the first side of the diode to a second, back side of the diode. (metal via structure). The metal via structure includes, for example, a central via, a peripheral via, or a perimeter via.

In various exemplary aspects, each diode of the plurality of diodes is less than about 30 μm in any dimension. In another exemplary embodiment, the diode has a diameter of about 20-30 μm and a height of about 5-15 μm; or have a diameter of about 10-50 μm and a height of about 5-25 μm; laterally substantially hexagonal and having a diameter of about 10 to 50 μm and a height of about 5 to 25 μm, measured opposing face-to-face; laterally substantially hexagonal and having a diameter of about 20-30 microns and a height of about 5-15 microns, measured opposite face-to-face; each having a width and a length of about 10 to 50 μm and a height of about 5 to 25 μm; Each has a width and a length of about 20 to 30 μm and a height of about 5 to 15 μm. In various exemplary aspects, the sides of each diode of the plurality of diodes are less than about 10 μm in height. In another exemplary embodiment, the sides of each diode of the plurality of diodes are about 2.5 to 6 μm in height. In another exemplary aspect, the sides of each diode of the plurality of diodes are substantially S-shaped and terminate at a bend point.

In various exemplary embodiments, the viscosity modifier further comprises an adhesive viscosity modifier. The viscosity modifier, when dried or cured, can form a polymeric or resinous lattice or structure substantially around a perimeter of each diode of the plurality of diodes. The composition may be, for example, opaque to the naked eye when wet and substantially optically clear when dried or cured. The composition may have a contact angle greater than about 25 degrees or greater than about 40 degrees. The composition may have a relative evaporation rate of less than one, wherein the evaporation rate is compared with the evaporation rate of butyl acetate equal to one. A method of using the composition may comprise printing the composition onto a substrate or onto a first conductor coupled to the substrate.

In an exemplary embodiment, each diode of the plurality of diodes comprises at least one inorganic selected from the group consisting of silicon, gallium arsenide (GaAs), gallium nitride (GaN), GaP, InAlGaP, InAlGaP, AlInGaAs, InGaNAs, and AlInGASb. including semiconductors. In another exemplary embodiment, each diode of the plurality of diodes comprises: a π-conjugated polymer, poly(acetylene), poly(pyrrole), poly(thiophene), polyaniline, polythiophene, poly(p-phenylene) sulfide), poly(para-phenylene vinylene) (PPV) and PPV derivatives, poly(3-alkylthiophene), polyindole, polypyrene, polycarbazole, polyazulene, polyazepine, poly(fluorene), Polynaphthalene, polyaniline, polyaniline derivative, polythiophene, polythiophene derivative, polypyrrole, polypyrrole derivative, polytianaphthene, polytianaphthane derivative, polyparaphenylene, polyparaphenylene derivative, polyacetylene, polyacetylene derivative , polydiacetylene, polydiacetylene derivative, polyparaphenylenevinylene, polyparaphenylenevinylene derivative, polynaphthalene, polynaphthalene derivative, polyisothianaphthene (PITN), polyheteroarylenevinylene (ParV) (wherein the heteroarylene group is thiophene, furan or pyrrole), polyphenylene-sulfide (PPS), polyperinaphthalene (PPN), polyphthalocyanine (PPhc), and derivatives thereof, copolymers thereof and at least one organic semiconductor selected from the group consisting of mixtures thereof.

Another exemplary aspect includes a plurality of diodes; a first solvent; and a viscosity modifier; wherein the composition has a viscosity of substantially from about 100 cps to about 25,000 cps at about 25°C. Another exemplary aspect includes a plurality of diodes, each diode of the plurality of diodes having an arbitrary dimension less than about 50 μm; a first solvent; a second solvent different from the first solvent; and a viscosity modifier; wherein the composition has a viscosity of from about 50 cps to about 25,000 cps substantially at about 25°C. Another exemplary aspect includes a plurality of diodes having any dimension less than about 50 μm; and a viscosity modifier to provide a composition viscosity of substantially from about 100 cps to about 20,000 cps at about 25°C. Another exemplary aspect includes a plurality of diodes; from the group consisting of N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclohexanol and mixtures thereof. a first solvent of choice; a viscosity modifier selected from the group consisting of methoxy propyl methylcellulose resin, hydroxy propyl methylcellulose resin, and mixtures thereof; and a second solvent different from the first solvent (the second solvent is N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetra hydrofurfuryl alcohol, cyclohexanol and mixtures thereof).

Another exemplary aspect includes a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. In an exemplary embodiment, the polymeric or resinous film comprises a methylcellulose resin having a thickness of about 10 nm to 300 nm. In another exemplary embodiment, the polymeric or resinous film comprises a methoxy propyl methylcellulose resin or a hydroxy propyl methylcellulose resin or mixtures thereof. The device may further comprise at least a trace amount of a second solvent different from the first solvent.

In an exemplary embodiment, the polymeric or resinous film comprises a clay, such as a hectorite clay, a garamite clay, an organo-modified clay; saccharides and polysaccharides such as guar gum, xanthan gum; Cellulose and modified celluloses such as hydroxy methylcellulose, methylcellulose, ethyl cellulose, propyl methylcellulose, methoxy cellulose, methoxy methylcellulose, methoxy propyl methylcellulose, hydroxy propyl methylcellulose, carboxymethylcellulose, hydroxy ethylcellulose, ethyl hydroxyl ethylcellulose, cellulose ether, cellulose ethyl ether, chitosan; polymers such as acrylate and (meth)acrylate polymers and copolymers; glycols such as ethylene glycol, diethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol, glycol ethers, glycol ether acetates; Fumed silica, silica powder; modified urea; and a cured, dried or polymerized viscosity modifier selected from the group consisting of mixtures thereof.

The exemplary device further comprises a plurality of substantially optically clear and chemically inert particles, each inert particle of the plurality of substantially optically clear and chemically inert particles being between about 10 and about 50 μm. can; wherein the polymeric or resin film further at least partially surrounds each inert particle of the plurality of substantially optically transparent and chemically inert particles.

Exemplary devices include: a substrate; one or more first conductors coupled to the first terminal; at least one dielectric layer coupled to the one or more first conductors; and one or more second conductors coupled to the second terminal and to the dielectric layer. In an exemplary aspect, at least one diode of the plurality of diodes has a first terminal coupled to the at least one second conductor and a second terminal coupled to the at least one first conductor. In another exemplary aspect, a first portion of the plurality of diodes has a first terminal coupled to at least one first conductor and a second terminal coupled to at least one second conductor, the plurality of diodes having a second terminal coupled to at least one second conductor A second portion of the rods has a first terminal coupled to the at least one second conductor and a second terminal coupled to the at least one first conductor. The exemplary apparatus can further include an interface circuit coupled to the one or more first conductors and the one or more second conductors, and the interface circuit can be further coupled to a power source.

In various exemplary aspects, the one or more first conductors include: a first electrode comprising a first busbar and a first plurality of elongated conductors extending from the first busbar; and a second electrode including a second bus bar and a second plurality of rectangular conductors extending from the second bus bar. The second plurality of rectangular conductors may be interdigitated with the first plurality of rectangular conductors. The one or more second conductors may further be coupled to the second plurality of rectangular conductors.

In various exemplary aspects, the device is collapsible and bendable. The device may be substantially flat and may have a total thickness of less than about 3 mm. The device can be die cut and folded into a selected shape. In the device, the average surface area concentration of the plurality of diodes may be about 25 to 50,000 diodes/cm 2 . In various exemplary aspects, the apparatus does not include a heat sink or heat sink component.

In another exemplary aspect, an apparatus comprises: a substrate; a plurality of diodes, each diode of the plurality of diodes having a first terminal and a second terminal, each diode of the plurality of diodes having an arbitrary dimension less than about 50 μm; a film substantially surrounding each diode of said plurality of diodes, said film comprising a polymer or resin having a thickness of about 10 nm to 300 nm; one or more first conductors coupled to a first first plurality of terminals; a first dielectric layer coupled to the one or more first conductors; and one or more second conductors coupled to the first second plurality of terminals.

In another exemplary aspect, an apparatus comprises: a substrate; one or more first conductors; a dielectric layer coupled to the one or more first conductors; one or more second conductors; a plurality of diodes, each diode of the plurality of diodes having an arbitrary dimension less than about 50 μm, and a first portion of the plurality of diodes in the one or more first conductors and in the one or more second conductors. coupled in a forward bias orientation, wherein at least one diode of the plurality of diodes is coupled to the one or more first conductors and to the one or more second conductors in a reverse bias orientation; and a film substantially surrounding each diode of the plurality of diodes, the film comprising a polymer or resin having a thickness of about 10 nm to 300 nm.

In various exemplary aspects, a diode comprises a light emitting or light absorbing region having a diameter of about 20 and 30 μm and a height of about 2.5 to 7 μm; a first terminal coupled to the light emitting region on a first side, the first terminal having a height of about 1 to 6 μm; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height of about 1 to 6 μm.

In another exemplary embodiment, a diode comprises: a light emitting or light absorbing region having a diameter of about 6 and 30 μm and a height of about 1 to 7 μm; a first terminal coupled to the light emitting region on a first side, the first terminal having a height of about 1 to 6 μm; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height of about 1 to 6 μm; wherein the diode is laterally substantially hexagonal and has a diameter of about 10 to 50 μm and a height of about 5 to 25 μm measured in opposite face-to-face, wherein the sides of the diode are each about a height of about It is less than 10 μm, has a substantially S-shaped curvature and terminates at a curved point.

In another exemplary embodiment, a diode comprises: a light emitting or light absorbing region having a diameter of about 6 and 30 μm and a height of about 1 to 7 μm; a first terminal coupled to the light emitting region on a first side, the first terminal having a height of about 1 to 6 μm; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height of about 1 to 6 μm; wherein the diode has a width and a length of about 10 to 50 μm and a height of about 5 to 25 μm, wherein the sides of the diode are each less than about 10 μm in height, have a substantially S-shaped curvature and have a curved point ends in

In various exemplary aspects, a diode comprises a light emitting or light absorbing region having a diameter of about 6 and 30 μm and a height of about 2.5 to 7 μm; a first terminal coupled to the light emitting region on a first side, the first terminal having a height of about 3 to 6 μm; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height of about 3 to 6 μm; wherein the diode has a width and a length of about 10 to 30 μm and a height of about 5 to 15 μm, wherein the sides of the diode are each less than about 10 μm in height, have a substantially S-shaped curvature and are curved points ends in

In another exemplary embodiment, a diode comprises: a light emitting or light absorbing region having a diameter of about 20 and 30 μm and a height of about 2.5 to 7 μm; a first plurality of terminals coupled away and coupled to the light emitting region around a first surface, each first terminal of the first plurality of terminals having a height of about 0.5 to 2 μm; and one second terminal centrally coupled to a mesa region of the light emitting region on the first surface, the second terminal having a height of 1 to 8 μm.

In another exemplary embodiment, a diode comprises: a light emitting or light absorbing region having a mesa region, wherein the mesa region has a height of 0.5 to 2 μm and a diameter of about 6 to 22 μm; a first plurality of terminals, each first terminal of the first plurality of terminals coupled to the light emitting region on a first surface, and peripherally coupled to the mesa region, each having a height of about 0.5 to 2 μm have); and one second terminal centrally coupled to the mesa region of the light emitting region on the first side, the second terminal having a height of 1 to 8 μm; Here, the diode has a lateral dimension of about 10 to 50 μm and a height of about 5 to 25 μm.

In another exemplary embodiment, a diode comprises: a light emitting or light absorbing region having a diameter of about 20 and 30 μm and a height of about 2.5 to 7 μm; a first plurality of terminals spaced apart and coupled to the light emitting region on a periphery on a first side, each first terminal having a height of about 0.5 to 2 μm; and one second terminal centrally coupled to the mesa region of the light emitting region on the first side, the second terminal having a height of 3 to 6 μm; wherein the diode is laterally substantially hexagonal and has a diameter of about 20-30 μm and a height of about 5-15 μm, wherein each side of the diode is less than about 10 μm in height and is substantially S-shaped It has curvature and ends at the bend point.

In another exemplary embodiment, a diode comprises: a light emitting or light absorbing region having a mesa region, wherein the mesa region has a height of 0.5 to 2 μm and a diameter of about 6 to 22 μm; a first plurality of terminals, each first terminal of the first plurality of terminals coupled to the light emitting region on a first surface, and peripherally coupled to the mesa region, each having a height of about 0.5 to 2 μm have); and one second terminal centrally coupled to the mesa region of the light emitting region on the first side, the second terminal having a height of 1 to 8 μm, the second metal terminal having a contact , the one contact portion of the second terminal is spaced apart from the contact portions of the first plurality of metal terminals by about 1 to 7 μm in height; wherein the diode is laterally substantially hexagonal and has a diameter of about 10-50 μm and a height of about 5-25 μm, wherein each side of the diode is less than about 15 μm in height and is substantially S-shaped It has curvature and ends at the bend point.

An exemplary method of making a liquid or gel suspension of a printing diode comprises: adding a viscosity modifier to a plurality of diodes in a first solvent; mixing the plurality of diodes, the first solvent and the viscosity modifier to form a liquid or gel suspension of the plurality of diodes.

In another exemplary aspect, an exemplary method of making a liquid or gel suspension of a printing diode comprises: adding a second solvent (the second solvent is different from the first solvent) to a plurality of diodes in a first solvent; adding a viscosity modifier to the plurality of diodes, the first solvent and the second solvent; adding a plurality of chemically inert particles to the plurality of diodes, the first solvent, the second solvent and the viscosity modifier; when the plurality of diodes, the first solvent, the second solvent, the viscosity modifier, and the plurality of chemically substantially inert particles have a viscosity measured at about 25° C. of at least about 100 centipoise (cps). mixing to form a liquid or gel suspension of the plurality of diodes.

In another exemplary embodiment, an exemplary method of making a liquid or gel suspension of a printing diode comprises: a viscosity modifier in a plurality of diodes, a first solvent and a second solvent, wherein the second solvent is different from the first solvent. , wherein each diode of the plurality of diodes has a lateral dimension of about 10-50 μm and a height of about 5-25 μm; adding a plurality of chemically inert particles to the plurality of diodes, the first solvent, the second solvent and the viscosity modifier, wherein each particle of the plurality of chemically inert particles is any dimensions of from about 10 μm to about 70 μm); when the plurality of diodes, the first solvent, the second solvent, the viscosity modifier and the plurality of chemically inert particles have a viscosity measured at about 25° C. of at least about 1,000 centipoise (cps). mixing to form a liquid or gel suspension of the plurality of diodes.

In an exemplary aspect, a method of manufacturing an electronic device includes depositing one or more first conductors; and depositing a plurality of diodes suspended in a mixture of a first solvent and a viscosity modifier.

In another exemplary embodiment, a method comprises depositing a plurality of diodes suspended in a mixture of a first solvent and a viscosity modifier on a first side of an optically transmissive substrate, wherein each diode of the plurality of diodes is disposed on the first side. having a first plurality of terminals and one second terminal on said first face, each diode of said plurality of diodes having a lateral dimension of about 10-50 μm and a height of 5-25 μm); depositing one or more first conductors coupled to the first terminal; depositing at least one dielectric layer coupled to the one or more first conductors; depositing one or more second conductors coupled to the second terminal; depositing a first phosphor layer over the second side of the optically transmissive substrate.

In another exemplary aspect, a method comprises depositing one or more first conductors over a first side of a substrate; A plurality of diodes suspended in a mixture of a first solvent and a viscosity modifier are deposited over the one or more first conductors, each diode of the plurality of diodes having a first terminal on a first side and a second terminal on a second side. having two terminals, each diode of said plurality of diodes having a lateral dimension of about 10-50 μm and a height of 5-25 μm); depositing at least one dielectric layer over the plurality of diodes and the one or more first conductors; depositing at least one optically transmissive second conductor over the dielectric layer; depositing a first phosphor layer.

In another exemplary aspect, a composition comprises: a plurality of two-terminal integrated circuits, each two-terminal integrated circuit of the plurality of two-terminal integrated circuits having an arbitrary dimension less than about 75 μm; a first solvent; a second solvent different from the first solvent; and a viscosity modifier; wherein the composition has a viscosity of from about 50 cps to about 25,000 cps substantially at about 25°C. In various exemplary aspects, the plurality of two-terminal integrated circuits are selected from the group consisting of a diode, a light emitting diode, a photovoltaic diode, a resistor, an inductor, a capacitor, an RFID integrated circuit, a sensor integrated circuit, and a piezoelectric integrated circuit. a two-terminal integrated circuit.

In another exemplary aspect, an apparatus comprises: a substrate; a plurality of two-terminal integrated circuits, each two-terminal integrated circuit of the plurality of two-terminal integrated circuits having an arbitrary dimension less than about 75 μm; at least a trace amount of a first solvent; a film substantially surrounding each diode of said plurality of diodes, said film comprising methylcellulose resin and having a thickness of about 10 nm to 300 nm; one or more first conductors coupled to the plurality of two-terminal integrated circuits; a first dielectric layer coupled to the one or more first conductors; and one or more second conductors coupled to the plurality of two-terminal integrated circuits.

In another exemplary aspect, a composition comprises: a plurality of two-terminal integrated circuits, each two-terminal integrated circuit of the plurality of two-terminal integrated circuits having an arbitrary dimension less than about 75 μm; a first solvent; a second solvent different from the first solvent; a plurality of chemically substantially inert particles having a size range from about 10 to about 100 μm and present in an amount from about 0.1% to about 2.5% by weight; and a viscosity modifier; wherein the composition has a viscosity of from about 50 cps to about 25,000 cps substantially at about 25°C.

Many other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and aspects thereof, the claims and the accompanying drawings.

The present invention provides light emitting and/or photovoltaic devices that are easy to manufacture and less expensive.

BRIEF DESCRIPTION OF THE DRAWINGS The objects, features and advantages of the present invention will become more readily recognized when reference is made to the following description in conjunction with the accompanying drawings, in which like reference numbers are used to denote like elements in the various drawings, and alphabetized reference numbers are Used in the drawings to indicate further types, examples or variations of selected member aspects.
Figure (or "FIG") 1 is a perspective view illustrating an exemplary first diode embodiment.
FIG. (or “FIG”) 2 is a plan (or top) view illustrating the above exemplary first diode embodiment.
FIG. (or “FIG”) 3 is a cross-sectional view illustrating the exemplary first diode embodiment.
FIG. (or “FIG”) 4 is a perspective view illustrating an exemplary second diode embodiment.
FIG. (or “FIG”) 5 is a plan (or top) view illustrating the above exemplary second diode embodiment.
FIG. (or “FIG”) 6 is a perspective view illustrating a third exemplary diode embodiment.
Figure (or "FIG") 7 is a top (or top) view of the above exemplary third diode embodiment.
FIG. (or “FIG”) 8 is a perspective view illustrating a fourth exemplary diode embodiment.
Figure (or “FIG”) 9 is a plan (or top) view of the above exemplary fourth diode embodiment.
FIG. (or “FIG”) 10 is a cross-sectional view illustrating an exemplary second, third and/or fourth diode embodiment.
FIG. (or “FIG”) 11 is a perspective view illustrating exemplary fifth and sixth diode embodiments.
Figure 12 (or "FIG") is a plan (or top) view of the above exemplary fifth and sixth diode embodiments.
Figure (or "FIG") 13 is a cross-sectional view illustrating the above exemplary fifth diode embodiment.
Figure (or "FIG") 14 is a cross-sectional view illustrating the above exemplary sixth diode embodiment.
FIG. (or “FIG”) 15 is a perspective view illustrating an exemplary seventh diode embodiment.
Figure (or “FIG”) 16 is a plan (or top) view illustrating the seventh exemplary diode embodiment above.
FIG. (or “FIG”) 17 is a cross-sectional view illustrating the above exemplary seventh diode embodiment.
FIG. (or “FIG”) 18 is a perspective view illustrating an exemplary eighth diode embodiment.
FIG. (or “FIG”) 19 is a plan (or top) view illustrating an eighth exemplary diode embodiment above.
Figure (or "FIG") 20 is a cross-sectional view illustrating the above exemplary eighth diode embodiment.
Figure (or “FIG”) 21 is a perspective view illustrating a tenth exemplary diode embodiment.
Figure (or "FIG") 22 is a cross-sectional view illustrating the above exemplary tenth diode embodiment.
Figure (or “FIG”) 23 is a perspective view illustrating an exemplary eleventh diode embodiment.
Figure (or “FIG”) 24 is a cross-sectional view illustrating the exemplary eleventh diode embodiment.
FIG. (or “FIG”) 25 is a cross-sectional view illustrating a portion of a composite GaN heterostructure and metal layers illustrating arbitrary geometries and textures of the exterior and/or interior surfaces of the composite GaN heterostructure.
Figure (or "FIG") 26 is a cross-sectional view of a wafer having an oxide layer, such as silicon dioxide.
Figure (or "FIG") 27 is a cross-sectional view of a wafer having an oxide layer etched in a grating pattern.
Figure (or "FIG") 28 is a top (or top) view of a wafer having an oxide layer etched in a grating pattern.
FIG. (or “FIG”) 29 is a cross-sectional view of a wafer having a buffer layer (eg, aluminum nitride or silicon nitride), a lattice pattern of a silicon dioxide layer, and gallium nitride (GaN) layers.
FIG. (or “FIG”) 30 is a cross-sectional view of a substrate having a buffer layer and a composite GaN heterostructure (n+ GaN layer, quantum well region, and p+ GaN layer).
FIG. (or “FIG”) 31 is a cross-sectional view of a substrate having a buffer layer and a first mesa-etched GaN heterostructure.
Figure (or "FIG") 32 is a cross-sectional view of a substrate having a buffer layer and a second mesa-etched composite GaN heterostructure.
FIG. (or “FIG”) 33 is a cross-sectional view of a substrate having a buffer layer, a mesa-etched composite GaN heterostructure, and an etched substrate for via connections.
Figure (or "FIG") 34 is a cross-sectional view of a substrate having a buffer layer, a mesa-etched composite GaN heterostructure, metallization forming ohmic contact with the p+ GaN layer, and metallization forming vias; to be.
Figure (or "FIG") 35 has a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming ohmic contact with the p+ GaN layer, a metallization forming vias, and lateral etched trenches. It is a cross-sectional view of the substrate.
Figure (or "FIG") 36 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a metallization forming vias, lateral etched trenches, and A cross-sectional view of a substrate having passivation layers (eg, silicon nitride).
Figure (or “FIG”) 37 shows a buffer layer, mesa-etched composite GaN heterostructure, metallization forming ohmic contact with the p+ GaN layer, metallization forming vias, lateral etched trenches, passivation It is a cross-sectional view of a substrate having layers and metallizations forming protrusions or bump structures.
Figure (or "FIG") 38 is a cross-sectional view of a substrate having a composite GaN heterostructure (n+ GaN layer, quantum well region, and p+ GaN layer).
Figure (or "FIG") 39 is a cross-sectional view of a substrate having a third mesa-etched composite GaN heterostructure.
FIG. (or “FIG”) 40 is a cross-sectional view of a substrate with a mesa-etched composite GaN heterostructure, an etched substrate for via connections, and lateral etched trenches.
Figure (or "FIG") 41 is a cross-sectional view of a substrate having a mesa-etched composite GaN heterostructure, metallization forming vias and forming ohmic contact with the n+ GaN layer, and lateral etched trenches.
Figure (or "FIG") 42 shows a mesa-etched composite GaN heterostructure, a metallization forming through vias and forming an ohmic contact with the n+ GaN layer, and a metallization forming an ohmic contact with the p+ GaN layer. , and a cross-sectional view of the substrate with the etched trenches on the side.
Figure (or "FIG") 43 shows a mesa-etched composite GaN heterostructure, a metallization forming via vias and forming an ohmic contact with the n+ GaN layer, and a metallization forming an ohmic contact with the p+ GaN layer. , lateral etched trenches, and a cross-sectional view of a substrate with passivation layers (eg, silicon nitride).
Figure (or "FIG") 44 shows a mesa-etched composite GaN heterostructure, a metallization forming via vias and forming an ohmic contact with the n+ GaN layer, and a metallization forming an ohmic contact with the p+ GaN layer. .
Figure (or "FIG") 45 is a cross-sectional view of a substrate having a buffer layer, a composite GaN heterostructure (n+ GaN layer, quantum well region, and p+ GaN layer), and a metallization forming an ohmic contact with the p+ GaN layer. to be.
Figure (or "FIG") 46 is a cross-sectional view of a substrate having a buffer layer, a fourth mesa-etched composite GaN heterostructure, and a metallization forming an ohmic contact with the p+ GaN layer.
Figure (or "FIG") 47 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, and a metallization forming an ohmic contact with the n+ GaN layer. It is a cross-sectional view of a board|substrate with
FIG. (or “FIG”) 48 is a cross-sectional view of a substrate having a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the n+ GaN layer, and lateral etched trenches.
Figure (or "FIG") 49 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a metallization forming an ohmic contact with the n+ GaN layer, and A cross-sectional view of a substrate with etched trenches on the side with metallization forming through the outer vias.
Figure (or "FIG") 50 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a metallization forming an ohmic contact with the n+ GaN layer, and A cross-sectional view of a substrate having lateral etched trenches with metallization forming through the outer vias, passivation layers (eg, silicon nitride), and metallization forming a protrusion or bump structure.
Figure (or "FIG") 51 is a cross-sectional view of a substrate having a buffer layer, a fifth mesa-etched composite GaN heterostructure, and a metallization forming an ohmic contact with the p+ GaN layer.
Figure (or "FIG") 52 is a diagram of a substrate having a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, and an etched GaN heterostructure for central via connection. It is a cross section.
Figure (or "FIG") 53 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, and a central via and an ohmic contact with the n+ GaN layer. It is a cross-sectional view of a substrate having a metallization.
Figure (or "FIG") 54 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a central via, and a metal forming an ohmic contact with the n+ GaN layer. It is a cross-sectional view of a substrate having a flower portion and a first passivation layer (eg, silicon nitride).
Figure (or "FIG") 55 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a central via, and a metal forming an ohmic contact with the n+ GaN layer. It is a cross-sectional view of a substrate having a portion of the substrate, a first passivation layer (eg, silicon nitride), and a metallization forming a protrusion or bump structure.
Figure (or "FIG") 56 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a central via, and a metal forming an ohmic contact with the n+ GaN layer. It is a cross-sectional view of a substrate having a first passivation layer (eg, silicon nitride), a metallization forming a protrusion or bump structure, and lateral (or outer) etched trenches.
Figure (or "FIG") 57 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a central via, and a metal forming an ohmic contact with the n+ GaN layer. having a first passivation layer (e.g., silicon nitride), a metallization forming a protrusion or bump structure, lateral (or outer) etched trenches, and a second passivation layer (e.g., silicon nitride) It is a cross-sectional view of the substrate.
Figure (or "FIG") 58 is a cross-sectional view of a substrate having a buffer layer, a sixth mesa-etched composite GaN heterostructure, and a metallization forming an ohmic contact with the p+ GaN layer.
Figure (or "FIG") 59 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, and a metallization forming an ohmic contact with the n+ GaN layer. It is a cross-sectional view of a board|substrate with
Figure (or "FIG") 60 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a metallization forming an ohmic contact with the n+ GaN layer, and A cross-sectional view of the substrate with additional metallization for contact with the p+ GaN layer.
Figure (or "FIG") 61 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a metallization forming an ohmic contact with the n+ GaN layer, the A cross-sectional view of the substrate with additional metallizations for contact with the p+ GaN layer, and metallizations forming protrusions or bump structures.
Figure (or "FIG") 62 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a metallization forming an ohmic contact with the n+ GaN layer, the A cross-sectional view of a substrate with additional metallization for contact with a p+ GaN layer, a metallization forming a protrusion or bump structure, and passivation layers (eg, silicon nitride).
Figure (or "FIG") 63 shows a buffer layer, a mesa-etched composite GaN heterostructure, a metallization forming an ohmic contact with the p+ GaN layer, a metallization forming an ohmic contact with the n+ GaN layer, the It is a cross-sectional view of a substrate having additional metallization for contact with the p+ GaN layer, metallization forming a protrusion or bump structure, passivation layers (e.g., silicon nitride), and lateral (or outer) etched trenches. .
Figure (or "FIG") 64 is a cross-sectional view illustrating an exemplary diode wafer embodiment attached to a support device.
FIG. (or “FIG”) 65 is a cross-sectional view illustrating an exemplary diode wafer embodiment attached to a support device.
Figure (or "FIG") 66 is a cross-sectional view illustrating an exemplary tenth embodiment of a diode attached to a support device.
FIG. (or “FIG”) 67 is a cross-sectional view illustrating an exemplary tenth embodiment of a diode prior to backside metallization attached to a support device.
Figure (or "FIG") 68 is a cross-sectional view illustrating an exemplary diode embodiment attached to a support device.
FIG. (or “FIG”) 69 is a cross-sectional view illustrating an exemplary eleventh diode embodiment attached to a support device.
Figure (or "FIG") 70 is a flow chart illustrating a first exemplary aspect of a method for manufacturing a diode.
Figure 71 (or "FIG") 71 divided into Figures 71A and 71B is a flow chart illustrating a second exemplary aspect of a method for manufacturing a diode.
Figure 72 (or "FIG") 72 divided into Figures 72A and 72B is a flow chart illustrating a third exemplary aspect of a method for manufacturing a diode.
FIG. 73 (or “FIG”) divided into FIGS. 73A and 73B is a flow chart illustrating a fourth exemplary aspect of a method for manufacturing a diode.
FIG. (or “FIG”) 74 is a cross-sectional view illustrating an exemplary grounded and polished diode wafer embodiment attached to a support device and suspended in a dish with an adhesive solvent.
Figure (or "FIG") 75 is a flow chart illustrating an exemplary embodiment of a method for making a diode suspension.
Figure (or “FIG”) 76 is a perspective view of an exemplary first device aspect.
FIG. (or “FIG”) 77 is a plan (or top) view illustrating an exemplary first electrode structure of a first conductive layer for an exemplary device aspect.
Figure (or “FIG”) 78 is a first cross-sectional view of a first exemplary device aspect.
Figure (or “FIG”) 79 is a second cross-sectional view of an exemplary first device aspect.
Figure (or “FIG”) 80 is a perspective view of an exemplary second device aspect.
Figure (or “FIG”) 81 is a first cross-sectional view of an exemplary second device aspect.
Figure (or “FIG”) 82 is a second cross-sectional view of a second exemplary device aspect.
Figure (or "FIG") 83 is a second cross-sectional view of an exemplary diode coupled to a first conductor.
Figure (or “FIG”) 84 is a block diagram of a first exemplary system aspect.
Figure (or “FIG”) 85 is a block diagram of a second exemplary system aspect.
FIG. (or “FIG”) 86 is a flow chart illustrating an exemplary aspect of a method of manufacturing a device.
Figure (or "FIG") 87 is a cross-sectional view of a third exemplary device embodiment for providing light emission from two sides.
Figure (or "FIG") 88 is a cross-sectional view of a fourth exemplary device embodiment for providing light emission from two sides.
Figure (or “FIG”) 89 is a more detailed partial cross-sectional view of an exemplary first device aspect.
FIG. (or “FIG”) 90 is a more detailed partial cross-sectional view of a second exemplary device embodiment.
Figure (or “FIG”) 91 is a perspective view of a fifth exemplary device aspect.
Figure (or “FIG”) 92 is a cross-sectional view of a fifth exemplary device embodiment.
Figure (or “FIG”) 93 is a perspective view of a sixth exemplary device aspect.
Figure (or “FIG”) 94 is a cross-sectional view of a sixth exemplary device embodiment.
Figure (or “FIG”) 95 is a perspective view of a seventh exemplary device embodiment.
Figure (or “FIG”) 96 is a cross-sectional view of a seventh exemplary device embodiment.
Figure (or “FIG”) 97 is a perspective view of an eighth exemplary device embodiment.
Figure (or “FIG”) 98 is a cross-sectional view of an eighth exemplary device embodiment.
FIG. (or “FIG”) 99 is a plan (or top) view illustrating an exemplary second electrode structure of a first conductive layer for exemplary device embodiments.
Figure (or “FIG”) 100 is a perspective view of third and fourth exemplary system aspects.
Figure (or “FIG”) 101 is a top (or top) view of an exemplary ninth and tenth device aspect.
Figure (or “FIG”) 102 is a cross-sectional view of a ninth exemplary device embodiment.
Figure (or “FIG”) 103 is a cross-sectional view of a tenth exemplary device embodiment.
FIG. (or “FIG”) 104 is a perspective view illustrating an exemplary first surface geometry of an exemplary light emitting or absorbing region.
FIG. (or “FIG”) 105 is a perspective view illustrating an exemplary second surface geometry of an exemplary light emitting or absorbing region.
FIG. (or “FIG”) 106 is a perspective view illustrating an exemplary third surface geometry of an exemplary light emitting or absorbing region.
FIG. (or “FIG”) 107 is a perspective view illustrating an exemplary fourth surface geometry of an exemplary light emitting or absorbing region.
FIG. (or “FIG”) 108 is a perspective view illustrating an exemplary fifth surface geometry of an exemplary light emitting or absorbing region.
Figure (or "FIG") 109 is a photograph of an exemplary device embodiment excited with light emission.
Figure (or "FIG") 110 is a scanning electron micrograph of an exemplary second diode embodiment.
Figure (or "FIG") 111 is a scanning electron micrograph of a plurality of exemplary second diode embodiments.

Detailed Description of Exemplary Aspects

While the present invention is susceptible to aspects in many different forms, it is hereby shown and described in the drawings specific exemplary aspects thereof, which are to be regarded as embodiments of the principles of the invention and are illustrative of the invention. It should be understood that the intention is not to be limited to particular aspects. In this regard, before describing in detail at least one aspect consistent with the present invention, the present invention is not limited to the details and arrangement of components as described above and below in its field, or as illustrated in the drawings or described in the embodiments. You have to understand that it doesn't. Methods and apparatus consistent with the present invention are capable of other aspects and of being practiced and carried out in various ways. Also, the phraseology and terminology used herein, as well as in the abstract included below, is for the purpose of description and should not be regarded as limiting.

Exemplary aspects of the present invention are printable diodes 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, which are printable and may equally be referred to herein as “diode ink”. liquid and/or gel dispersions and suspensions of (collectively referred to as “diodes 100-100L” herein and in the drawings), wherein “diode inks” include diodes or other two-terminal integrated circuits such as exemplary diodes 100-100L It should be understood that it means and refers to a liquid and/or gel suspension of As described in more detail below, the diodes 100 to 100L themselves, prior to inclusion in the diode ink composition, can function to emit light when energized (when implemented as an LED) or (when implemented as a photovoltaic diode). a) complete semiconductor devices that can function to provide power when exposed to a light source. An exemplary method of the present invention also includes a method of making a diode ink in which 100 to 100 L of a plurality of diodes are dispersed and suspended in a solvent and a viscous resin or polymer mixture, as discussed in more detail below, wherein the diode 100 to 100L or other two-terminal integrated circuits remain dispersed and suspended at room temperature (25°C) or refrigerated conditions (5-10°C) for a considerable period of time, e.g., 1 month or more, especially at higher viscosity In this case, it is maintained as a more gel-like composition and a refrigeration-derived gel-like composition, and the liquid or gel suspension can be printed to make LED-based devices and photovoltaic devices. While the present description focuses on diodes 100-100L of the two-terminal integrated circuit type, those skilled in the art will equally replace other types of semiconductor devices, more broadly referred to as "semiconductor device inks"; For example, any type of transistor (Field Effect Transistor (FET), Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Junction Field Effect Transistor (JFET), Bipolar Junction Transistor (BJT), etc.), diac ), triacs, silicon controlled rectifiers, and the like, can be formed without limitation.

The diode ink (or semiconductor device ink) may be used in any of a variety of products discussed in greater detail below, for example, apparatus 300, 300A, 300B 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, Signage for packaging products, such as consumer products, personal products, business products, industrial products, agricultural products, construction products, etc., that can be deposited, printed or applied to form aspects 760, 770 or systems 350, 375, 800, 810 can be deposited, printed or applied to, or to form, any article of any kind, including a signage or indicia.

do 1 is a perspective view illustrating an exemplary first diode 100 aspect. FIG. 2 is a plan (or top) view illustrating the exemplary first diode 100 embodiment. FIG. 3 is a cross-sectional view (through the 10-10′ plane of FIG. 2 ) illustrating the exemplary first diode 100 embodiment. 4 is a perspective view illustrating an exemplary second diode 100A embodiment. Fig. 5 is a plan (or top) view showing an embodiment of the second exemplary diode 100A. 6 is a perspective view illustrating an exemplary third diode 100B embodiment. Fig. 7 is a plan (or top) view showing an embodiment of the third exemplary diode 100B. 8 is a perspective view illustrating an exemplary fourth diode 100C embodiment. 9 is a plan (or top) view illustrating an exemplary embodiment of the fourth diode 100C. 10 is a cross-sectional view (through the 20-20' plane of FIGS. 5, 7, 9) illustrating exemplary second, third and/or fourth diode 100A, 100B, 100C embodiments. 11 is a perspective view illustrating exemplary fifth and sixth diodes 100D and 100E embodiments. 12 is a plan view (or top view) illustrating embodiments of the exemplary fifth and sixth diodes 100D and 100E. 13 is a cross-sectional view (through the 40-40' plane of FIG. 12) illustrating the fifth exemplary diode 100D embodiment. 14 is a cross-sectional view (through the 40-40' plane of FIG. 12) illustrating the sixth exemplary diode 100E embodiment. 15 is a perspective view illustrating an exemplary seventh diode 100F embodiment. Fig. 16 is a plan (or top) view showing the embodiment of the seventh exemplary diode 100F. FIG. 17 is a cross-sectional view (through the 42-42' plane of FIG. 16) illustrating the seventh exemplary diode 100F embodiment above. 18 is a perspective view illustrating an exemplary eighth diode 100G embodiment. 19 is a plan (or top) view illustrating the exemplary eighth diode 100G embodiment. FIG. 20 is a cross-sectional view (through the 43-43' plane of FIG. 19) illustrating the eighth exemplary diode 100G embodiment. 21 is a perspective view illustrating an exemplary tenth diode 100K embodiment. 22 is a cross-sectional view (through the 47-47' plane of FIG. 21) illustrating the exemplary tenth embodiment of the diode 100K. 23 is a perspective view illustrating an exemplary eleventh diode 100L embodiment. FIG. 24 is a cross-sectional view (through the 48-48' plane of FIG. 23) illustrating the exemplary eleventh diode 100L embodiment. Cross-sectional views of ninth, twelfth and thirteenth diode 100H, 100I and 100J embodiments are shown in FIGS. 44, 50 and 66, respectively, as illustrative portions of exemplary fabrication processes. 110 is a scanning electron micrograph of an exemplary second diode 100A embodiment. 111 is a scanning electron micrograph of an embodiment of a second plurality of exemplary diodes 100A.

1, 2, 4 to 9, 11, 12, 15, 16, 18, 19, 21 and 23 in the perspective and plan (or top) views of the passivation layer 135 by omitting the example of the outer passivation layer 135 provides a view of the external base layers and structures covered (and thus not visible) by The passivation layer 135 is illustrated in the cross-sectional views of FIGS. 3, 10, 13, 14, 17, 20, 22, 24, 44, 50, 57, 62, 63, and 66-69, which are manufactured by those skilled in the art of electronics. It will be appreciated that diodes 100 - 100L typically include at least one such passivation layer 135 . Additionally, in Figures 1-69, 74, 76-85, and 87-103, those skilled in the art will also recognize that the various drawings are for purposes of illustration and description and have not been drawn to scale.

As will be described in more detail below, the exemplary first through thirteenth diode aspects 100 through 100L include the shape, material, doping and other compositions of the substrate 105 and wafer 150, 150A that may be used; a manufacturing shape of the light emitting region of the diode; depth and location of vias 130 , 131 , 132 , 133 , 134 , 136 (eg, shallow or “blind”, deep or “through”, center, perimeter, and perimeter); having a first terminal 125 on a first (top or front) side or having both a first terminal 125 and a second terminal 127; use and size of the back (second side) metallization 122 to form the first terminal 125 or the second terminal 127; the shape, size and location of the other contact metals are generally different; They may also differ in the shape or location of other features, as described in more detail below. Exemplary methods and variations in method for fabrication of the exemplary diodes 100 - 100L are also described below. One or more of the above exemplary diodes 100-100L are also available and commercially available from NthDegree Technologies Worldwide, Inc. of Tempe, Arizona, USA.

1-24, exemplary diodes 100-100L may be, for example, but not limited to, a silicon wafer or a more complex substrate such as including a silicon substrate over insulator (“SOI”) 105 or A heavily-doped n+ (n plus) or p+ (p plus) substrate 105, which may be a wafer, for example a substrate 105 such as a heavily-doped n+ or p+ silicon substrate, or nitride on a sapphire 106 wafer Formed using a gallium (GaN) substrate 105 150A (illustrated in FIGS. 11-20). As discussed in more detail below, for example, other types of substrates (and/or wafers forming or having a substrate) including, but not limited to, Ga, GaAs, GaN, SiC, SiO ₂ , sapphire, organic semiconductors, etc. ) 105 can equally be used. Thus, reference to substrate 105 or 105A refers to n+ or p+ silicon, n+ or p+ GaN, e.g., an n+ or p+ silicon substrate 150 formed using a silicon wafer or n+ or p+ GaN 105A fabricated on a sapphire wafer (Fig. It should be understood broadly to include any type of substrates, such as those described below with reference to 11-20 and 38-50). 21-24 , substrates 105 , 105A (and buffer layer 145 ) may be ignored after substrate removal (leaving composite GaN heterostructures in place, as discussed in more detail below, as discussed in greater detail below) during fabrication. Substrate 105 or 105A may be used, with or without remaining to the extent of, for example, but not limited to, substrates. When implemented using silicon, the substrate 105 typically has a <111> or <110> crystal structure or orientation, but other crystal structures may equally be used. An optional buffer layer 145 is typically fabricated over a silicon substrate 105 such as aluminum nitride or silicon nitride to facilitate subsequent fabrication of GaN layers with different lattice constants.

GaN layers are fabricated over the buffer layer 145, for example via epitaxial growth, to form a composite GaN heterostructure, typically illustrated as an n+ GaN layer 110 , a quantum well region 185 and a p+ GaN layer 115 . In other aspects, as illustrated in FIGS. 15-17 as a more specific option, a composite GaN heterostructure (n+ GaN layer 110 , quantum well region 185 and p+ GaN layer 115 ) is deposited over a GaN substrate 105 (or sapphire 106 ), as illustrated in FIGS. ) the buffer layer 145 may or may not be used as in the case of direct) fabrication on wafer 105A. To form the light emitting (or light absorbing) region 140, there may be multiple p+, n+, other GaN layers with a wide range of dopants, potentially with multiple quantum wells, and possibly non-GaN layers with any of the various dopants. and n+ GaN layer 110, quantum well region 185, and p+ GaN layer 115 are exemplary only, and represent a generalized or simplified description of a composite GaN heterostructure or any other semiconductor structure forming one or more light emitting (or light absorbing) regions 140. It will be appreciated by those skilled in the art of providing Further, the positions of the n+ GaN layer 110 and the p+ GaN layer 115 may be the same or equivalently reversed as in the use of a p+ silicon or GaN substrate 105, to form one or more light emitting (or light absorbing) regions 140 . It will be understood by those skilled in the art that other compositions and materials may be used, many of which are described below, and all such modifications are within the scope of this disclosure. Although GaN has been described as a series of exemplary materials having different compounds, dopants, and structures to form the light emitting or light absorbing region 140, it is understood that any other suitable semiconductor material can be equally used and is within the scope of the art. Those skilled in the art will recognize. Further, any reference to GaN is not to be construed as "pure" GaN, and may be used to form a light emitting or light absorbing region 140, including any intermediate non-GaN layers, and/or a light emitting or light absorbing region 140 being It will be understood by those skilled in the art that it means and includes all of the various other compounds, dopants and layers that allow it to be deposited.

It is also noted that while many of the various diodes (diodes 100-100L) are discussed which may or may use silicon and GaN as selected semiconductors, other inorganic or organic semiconductors may equally be used and are within the scope of this disclosure. Should be. Examples of inorganic semiconductors include silicon, germanium and mixtures thereof; titanium dioxide, silicon dioxide, zinc oxide, indium-tin oxide, antimony-tin oxide and mixtures thereof; Compounds of at least one divalent metal (zinc, cadmium, mercury and lead) and at least one divalent non-metal (oxygen, sulfur, selenium and tellurium), for example zinc oxide, cadmium selenide, cadmium sulfide, selenium II-VI semiconductors which are mercury hydride and mixtures thereof; III-, which is a compound of at least one trivalent metal (aluminum, gallium, indium and thallium) and at least one trivalent nonmetal (nitrogen, phosphorus, arsenic and antimony), for example gallium arsenide, indium phosphide and mixtures thereof V semiconductor; and Group IV semiconductors including, but not limited to, hydrogenated silicon, carbon, germanium and alpha-tin and combinations thereof.

In addition to the GaN light emitting/absorbing region 140 (eg, a GaN heterostructure deposited on a substrate 105 such as n+ or p+ silicon or deposited on a GaN (105) 150 on a silicon wafer or a sapphire (106) wafer 150A), the plurality of The diodes 100 to 100L can be any type of semiconductor device, material or compound, for example, silicon, gallium arsenide (GaAs), gallium nitride (GaN), or GaP, InAlGaP, InAlGaP, AlInGaAs, InGaNAs, AlInGASb. It may be composed of any inorganic or organic semiconducting material, including but not limited to. Further, further, the wafer used to fabricate the two-terminal integrated circuit may also be of any type or type, such as, but not limited to, silicon, GaAs, GaN, sapphire, and silicon carbide.

Accordingly, the scope of the present disclosure is to include, but not limited to, any LEDs or photovoltaic semiconductors known in the art or fabricated using any type of semiconductor substrate known in the art. It should be understood to include epitaxial or compound semiconductors.

In various exemplary aspects, the n+ or p+ substrate 105 conducts current flowing into the n+ GaN layer 110 as illustrated. It should be noted again that any of the various exemplified layers of the light emitting or light absorbing region 140 above may be equally inverted or may have a different order, such as the exemplified positions of the n+ and p+ GaN layers 110 , 115 are reversed. The current flow path also passes through a metal layer forming one or more vias 130 (this is to provide an electrical bypass of a very thin (about 25 Å) buffer layer 145 between the n+ or p+ substrate 105 and the n+ GaN layer 110 . can also be used). Additional types of vias 131 through 134 and 136 that provide other connections to the conductive layers are described below. One or more metal layers 120 (which can also be used to form vias 130, 131, 132, 133, 134, 136), exemplified as two (or more) individually deposited metal layers 120A and 120B above p+ providing ohmic contact with the GaN layer 115, a second additional metal layer 120B, such as a die metal, is used to form a “bump” or protrusion structure, and the metal layers 120A, 120B are first electrical for the various diodes 100-100L A terminal (or contact) 125 or a second terminal 127 is formed. Additional metal layers may also be used as discussed below. For the illustrated exemplary diode 100, 100A, 100B, 100C aspects, electrical terminal 125 is used above during manufacture for subsequent power (voltage) supply (for LED applications) or reception (for photovoltaic applications). The n+ or p+ substrate 105 may be the only ohmic metal terminal formed over the diodes 100, 100A, 100B, 100C, and to provide a second electrical terminal for the diodes 100, 100A, 100B, 100C for supplying or receiving power. used that the electrical terminal 125 and the n+ or p+ substrate 105 are on opposing sides that are the top (first side) and bottom (or back side, second side) of the diodes 100, 100A, 100B and 100C, respectively, and not on the same side It should be noted As an option for these diode 100, 100A, 100B, 100C aspects, and as shown in other exemplary diode aspects, on a second, backside of a diode (eg, diode 100D, 100F, 100G, 100J) The metal layer 122 is used to form an optional second ohmic metal terminal 127 . As an option to the diode 100K embodiment illustrated in FIGS. 21 and 22 , a metal layer 122 is used to form a first ohmic metal terminal 125 over a second, backside, flipping or inverting the diode 100K for later use. As another option illustrated in FIGS. 23 and 24 for the exemplary diode 100L, the first terminal 125 and the second terminal 127 are both on the same first (top) side of the diode 100L. Silicon nitride passivation 135 (or any other equivalent passivation) is used in particular for electrical insulation, environmental stability and possibly further structural integrity. Although not separately illustrated, as discussed below, during fabrication a plurality of trenches 155 are formed along the sides of the diodes 100 - 100L, which isolate (singulate) the diodes 100 - 100L from each other on wafers 150 and 150A. ) and is also used to isolate the diodes 100-100L from the rest of the wafers 150, 150A.

1-24 also show various shape and form factors of one or more light emitting (or light absorbing) regions 140, illustrated as GaN heterostructures (n+ GaN layer 110, quantum well region 185, and p+ GaN layer 115), substrate 105 and and/or illustrate some of the various shapes and form factors of the composite GaN heterostructure. Also, as illustrated, the example diodes 100-100L are nearly hexagonal in the x-y plane to provide greater device density for silicon wafers (as discussed in more detail below, but with concave or convex curves or arcs) Other diode shapes and shapes such as having sides 121 (or having both of them to form a more complex S-shape), square, circular, oval, oval, rectangular, triangular, octagonal, annular, etc. are equivalent and claimed It is considered to be within the scope of the invention. Also, as illustrated in the exemplary aspects above, the hexagonal sides 121 may be convex (Figs. to avoid sticking or sticking to each other when the diodes 100 to 100L are suspended in a liquid. Additionally, for device 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 fabrication, individual dies (individual diodes 100 - 100L) may be mounted on their sides or Diodes 100 to 100L of relatively small thickness are used so as not to stand on the edges 121 . Also, as illustrated in the exemplary aspects above, the hexagonal sides 121 are convex at the center or center of each side 121, and concave at the periphery/lateral sides, slightly curved or arched to form a more complex S-shape ( can form overlapping double "S" shapes), yielding relatively sharp or protruding apex 114 (FIGS. 11-24), whereby the diodes 100-100L stick or stick together when released from the wafer and suspended in a liquid. can be avoided, and can push each other when rolling or moving relative to another diode. Variations from planar surface topologies (ie, non-planar surface topologies) for diodes 100-100L also help prevent dies from sticking together when suspended in liquid or gel. Again, also for the manufacture of devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 (relative to lateral dimensions (diameter or width/length)) Diodes 100-100L (or the light emitting area of diodes 100K and 100L) of relatively small thickness or height tend to prevent individual dies (individual diodes 100-100L) from standing on their sides or edges 121 .

Various shapes and form factors of the emitting (or absorbing) region 140 (n+ GaN layer 110, quantum well region 185 and p+ GaN layer 115) are also illustrated, with FIGS. 1-3 being substantially annular or disk-shaped emitting (or absorbing) ) region 140 (n+ GaN layer 110, quantum well region 185 and p+ GaN layer 115), wherein Figures 4 and 5 are substantially torus (or toroidal) emitting (or absorbing) region 140 ( Illustrated is an n+ GaN layer 110 , a quantum well region 185 and a p+ GaN layer 115 ), with a second metal layer 120B extending into the center of the toroid (and potentially also providing a reflective surface). 6 and 7 , the light emitting (or light absorbing) region 140 (n+ GaN layer 110, quantum well region 185, and p+ GaN layer 115) has a substantially annular inner (lateral) surface and a substantially lobed outer (lateral) surface. On the other hand, in FIGS. 8 and 9 , the light emitting (or light absorbing) region 140 (n+ GaN layer 110, quantum well region 185, and p+ GaN layer 115) has a substantially annular inner (lateral) surface while the outer (lateral) surface is substantially Radial or star-shaped. 11 to 24 , one or more light emitting (or light absorbing) regions 140 have a substantially hexagonal (lateral) surface (which may or may not extend outside of the die) and is (at least in part) substantially annular or an elliptical inner (lateral) surface. In other exemplary aspects not shown separately, there may be multiple light emitting (or light absorbing) regions 140 that may be continuous or spaced apart over the die. These various settings of one or more light emitting (or light absorbing) regions 140 (n+ GaN layer 110, quantum well region 185, and p+ GaN layer 115) having an annular inner surface determine the potential for light output (for LED applications) and (solar light). For power generation applications) to increase light absorption. As discussed in more detail below, the inner and/or outer surface of any of n+ GaN layers 110 or p+ GaN layers 115 may have any of a variety of surface textures or surface geometries, including, but not limited to, any of a variety of surface geometries.

In an exemplary embodiment, first terminal 125 (or second terminal 127 of diode 100K) is comprised of one or more metal layers 120A, 120B and has bumps or protrusions (n+ or p+ silicon by first conductor 310 or 310A). After electrical contact is made to the substrate 105 (or the second terminal formed by the metal layer 122, or the second terminal formed by the metal layer 128) a significant portion of the diodes 100 to 100L is covered with one or more insulating or dielectric layers. while at the same time providing sufficient structure for contact with the electrical terminal 125 by one or more other conductive layers, such as the second conductor 320 discussed below. Additionally, in addition to the curvature of the sides 121 and the thickness (height) of the sides 121, the bump or protrusion structure of the terminal 125 may also potentially be a fabricated device 300, 300A, 300B, 300C, 300D, 700, 700A, 700B. , 720, 730, 740, 750, 760, 770 for rotation of diodes 100 to 100L in diode ink and their subsequent orientation (top up (forward bias) or bottom up (reverse bias)) It can be one of a number of factors influencing.

11-22, exemplary diodes 100D, 100E, 100F, 100G, 100K show some additional optional features in various combinations. As shown, the metal layer 120B forming the bump or protrusion structure, which is typically made of die metal, is substantially elliptical (or oval) (substantially hexagonal in FIG. Other shape and form factors are also within the scope of this disclosure. Additionally, the metal layer 120B, which forms the bump or protrusion structure, may contain several additional Objects, such as facilitating the formation of electrical contact with the second conductor 320 and facilitating the flow of the insulating dielectric 315 (and/or the first conductor 310) from the terminal 125 (metal layer 120B or metal 122). may have two or more rectangular extensions 124 providing The elliptical form factor may allow for additional light emission (or light absorption) in the light emitting (or light absorbing) region 140 along the major axis faces of the elliptical metal layer 120B forming the bump or protrusion structure. Metal layer 120A forming ohmic contact with p+ GaN layer 115, which may be deposited as a multilayer in multiple steps, is also shown as curved metal contact extensions 126 in FIGS. 11 , 12 , 15 , 16 , 18 and 19 , Having rectangular extensions over the p+ GaN layer 115 for selected aspects, which facilitates current conduction to the p+ GaN layer 115 while simultaneously allowing a potential for light emission or absorption by the light emitting (or absorbing) region 140 (Also don't overblock). Numerous other shapes of the metal contact extensions 126 may equally be used, such as a grid pattern, other curved shapes, and the like. Although not specifically illustrated, these rectangular metal contact extensions may also be used in other embodiments illustrated in FIGS. 1-10 and 21-24 . Additional seed layers or reflective metal layers may also be used, as described in more detail below.

In the fabricated diodes 100, 100A, 100B, 100C, relatively shallow or "blind" of the perimeter (ie off-center) described above that extend through the buffer layer 145 into the substrate 105 but do not extend relatively deep or penetrating into the substrate 105. " In addition to via 130 , additional types of via structures 131 , 132 , 133 , 134 , 136 are illustrated in FIGS. 11-22 . 13 (and 44, 66), a central (or centered) relatively deep “through” via 131 extends completely through the substrate 105 and creates an ohmic contact with the n+ GaN layer 110 . and to conduct current (or create other electrical contact) between the second (double) side metal layer 122 and the n+ GaN layer 110 . As illustrated in FIG. 22 , a central (or centrally located) relatively less deep or shallower “through” via 136 extends completely through the composite GaN heterostructures 115 , 185 , 110 and with the n+ GaN layer 110 and , and to conduct current (or create other electrical contacts) between the second (double) side metal layer 122 and the n+ GaN layer 110 . As illustrated in FIG. 14 , a central (or centered) relatively shallow or blind via 132, also referred to as “blind” via 132, extends through buffer layer 145 into substrate 105 and is in ohmic contact with n+ GaN layer 110 . and to conduct current (or create other electrical contact) between the n+ GaN layer 110 and the substrate 105 . 15-17 and 49-50, the outer relatively deep or through via 133 is a second, backside of diode 100F along sides 121 (although covered by passivation layer 135) from n+ GaN layer 110. (which in this aspect also includes the second (back) side metal layer 122 entirely around the sides of the substrate 105), creating an ohmic contact with the n+ GaN layer 110, and the second (back) side metal Used to conduct current (or create other electrical contact) between layer 122 and n+ GaN layer 110 . 18-20 , the peripheral relatively deep through via 134 extends completely through the substrate 105 and creates an ohmic contact with the n+ GaN layer 110 , and with the second (double) side metal layer 122 . Used to conduct current (or create other electrical contacts) between the n+ GaN layers 110 . In aspects that do not use the second (back) side metal layer 122 , these through via structures 131 , 133 , 134 , 136 may include conductor 310A (device 300 , 300A, 300B, 300C, 300D, 720 , 730 , 760), and to conduct current (or create other electrical contact) between conductor 310A and the n+ GaN layer 110 . These through via structures 131 , 133 , 134 , 136 are, after backside grinding and polishing or singulating of the diodes via laser lift off (discussed below with reference to FIGS. 64 and 65 ), the diode 110D, 100F, 100G, 100K exposed over the second, backside, and may remain exposed (as shown in FIG. 66 ) or covered by a second (back)side metal layer 122 (also said metal layer) may form electrical contact with the

The through via structures 131 , 133 , 134 , 136 are significantly narrower than conventional vias known in the art. The through via structures 131 , 133 , and 134 have a depth (height extending through the substrate 105) of about 7 to 9 μm, and the through via structure 136 has a depth (the height extending through the composite GaN heterostructure) of about 2 to 4 μm, and about 3 to 5 μm wide compared to the 30 μm or greater width of typical vias.

An optional second (back) side metal layer 122 forming a second terminal or contact 127 or a first terminal 125 (diode 100K) is also illustrated in FIGS. 11 to 13 , 17 , 18 , 20 to 22 , 66 , and 68 . has been This second terminal or contact 127 facilitates current conduction to the n+ GaN layer 110 through various through via structures 131 , 133 , 134 , 136 , for example, but not limited to, and/or electricity with conductor 310A. It can be used to facilitate making contact.

21-22, an exemplary diode 100K illustrates some additional optional features. 22 illustrates in cross-section the fabrication layers of how an exemplary diode 100K is fabricated; The exemplary diode 100K is then flipped or inverted to an upright position as illustrated in FIG. 21 for use in exemplary device 300 , 300A, 300B, 300C, 300D, 720, 730, 760 aspects, and the top n+ GaN layer It emits light through 110 (in LED aspects). Accordingly, the first terminal 125 is formed from the second (double) side metal 122, and the orientation of the n+ GaN layer 110 and the p+ GaN layer 115 is similarly reversed (compared to the other aspects 100 to 100J) and is similarly reversed (the n+ GaN layer). 110 is now the top layer in FIG. 21 ), and the second terminal 127 is formed from one or more metal layers 120B. Substrates 105, 105A or buffer layer 145 are very little or not illustrated, and have been substantially removed in manufacturing, composite GaN heterostructures (p+ GaN layer 115, quantum well region 185, and p+ GaN layer 115), and Potentially some additional GaN layer or substrate is also left in place. The sides or edges 121 are provided to prevent individual diode 100K from standing on their sides or edges 121 during device 300, 300A, 300B, 300C, 300D, 720, 730, 760 manufacturing process. , in exemplary embodiments 10 μm or less, or more particularly about 2 to 8 μm, or more particularly about 2 to 6 μm, or more particularly about 2 to 4 μm, or even more particularly 2.5 to 3.5 μm, or about 3 μm. , relatively thinner (or less thick) than other illustrated embodiments.

The second (double) side metal 122 forming the first terminal 125 is relatively thick, in exemplary embodiments, from about 3 to 6 μm, or from 4.5 to about 5.5 μm, or about 5 μm, such that the height of the diode 100K is about 11 to 15 μm, alternatively 12 to 14 μm, alternatively about 13 μm, and permitting deposition of the dielectric layer 315 and contact with the second conductor 320, including, but not limited to, about 14 μm on the major axis and about 6 μm on the minor axis. It has an elliptical shape, such as having a μm. The second (back) side metal 122 forming the first terminal 125 also does not extend across the entire back side for ease of back alignment and diode 100K singulation. The second terminal 127 formed from the metal layer(s) 120B is also, in exemplary embodiments, generally about 3 to 6 μm thick, or 4.5 to about 5.5 μm thick, or about 5 μm thick. Also, as illustrated, the insulating (passivation) layer 135A is also used to electrically insulate or isolate the metal layer 120B from the via 136 and, as illustrated by 135A, from the deposition of the passivation (nitride) layer 135 around the perimeter, as illustrated by 135A. It can be deposited as a separate step. In exemplary aspects, the width of the diode 100K (not vertex to vertex, but generally face to face across a hexagonal shape) may be, for example, but not limited to, about 10-50 μm, or more particularly about 20-30 μm. μm, or more particularly about 22 to 28 μm, or more particularly about 25 to 27 μm, or more particularly about 25.5 to 26.5 μm, or even more particularly about 26 μm. Although not separately illustrated, the metal layer 120A may also be included in manufacturing the second terminal 127 . In the diode 100K fabrication process (and other exemplary diode 100-100L aspects), the top GaN layer (illustrated as p+ GaN layer 115 , as illustrated in FIG. 25 , but may be other types of GaN layers) is placed into an ohmic contact. To facilitate the formation of (and potentially provide light reflection for the n+ GaN layer 110 ), a very thin optically reflective metal layer (illustrated as silver layer 103 in FIG. 25 ), and/or about 100 Å thick nickel - may be metallized and alloyed with an optically transmissive metal layer (not separately illustrated) such as gold or nickel-gold-nickel, some of which are removed by other GaN layers, for example during GaN mesa formation.

23 and 24 , an eleventh exemplary diode 100L embodiment is another exemplary diode 100 to 100K in that it has both a first terminal 125 and a second terminal 127 on the same (top or top) side of the diode 100L. different from all aspects. When used in the exemplary device 700, 700A, 700B, 740, 750, 770 aspects, light passes through the (bottom) n+ GaN layer 110, typically substantially optically transparent, as illustrated in FIGS. 80-82 . Through the phosphorous substrate 305A, it will either emit light (for LED embodiments) or absorb (for photovoltaic embodiments). As a result of having both a first terminal 125 and a second terminal 127 on the same (top or top) side of the diode 100L, this exemplary diode 100L does not use any second (double) side metal 122, and generally It does not require any of the various via structures discussed. Substrates 105 , 105A or buffer layer 145 are very little or not illustrated, and are substantially eliminated during fabrication, including composite GaN heterostructures (p+ GaN layer 115, quantum well region 185, and p+ GaN layer 115), and potential As a result, some additional GaN is also left in place. The sides or edges 121 are also relatively thinner (or less than in other illustrated embodiments), in exemplary embodiments about 2 to 4 μm, or more particularly 2.5 to 3.5 μm, or about 3 μm. thick), and also prevents the individual diodes 100L from standing on their sides or edges 121 during device 700, 700A, 700B, 740, 750, 770 fabrication. Although not specifically illustrated, in the diode 100L fabrication process (and other exemplary diode 100 - 100K aspects), a top GaN layer (illustrated as p+ GaN layer 115, as illustrated in FIG. 25 , but may be other types of GaN layers) to facilitate the formation of an ohmic contact (and potentially provide light reflection for the n+ GaN layer 110 ), a very thin optically reflective metal layer (illustrated as silver layer 103 in FIG. 25 ), and/or It may also be metallized and alloyed with an optically transmissive metal layer (not separately illustrated) such as nickel-gold or nickel-gold-nickel about 100 Å thick, some of which may be deposited on other GaN layers, for example during GaN mesa formation. is removed by

23 and 24, the GaN mesa (p+ GaN layer 115 and quantum well layer 185) generally provides room over the top surface of the n+ GaN layer 110 for metal contacts 128 (three are illustrated). To do so, it is atypically shaped as a triangle with flat vertices (eg formed by providing a plurality (three) cave-out portions from a hexagonal or annular shape), which is a diode Second terminals 127 are formed on the upper or upper surface of 100L. The GaN mesa, in various exemplary embodiments, generally has a height of about 0.5 to 1.5 μm, or more particularly 0.8 to 1.2 μm, or more particularly 0.9 to 1.1 μm, or more particularly about 1.0 μm. The metal contact 128 may be approximately 0.75 to 1.5 μm high, or more particularly about 0.9 to 1.1 μm high, or more particularly about 1.0 μm high via metal, such as about 100 Angstroms of titanium, 500 nm of aluminum, 500 nm of It may be formed from nickel, and 100 nm of gold, and may be about 2.5 to 3.5 μm wide (measured radially). A first terminal 125 formed from metal layers 120A and 120B, in various exemplary aspects, allows for the deposition of a first conductor 310A in contact with a metal contact 128, a first terminal 125 and a second conductor 320 (FIGS. 80- 82) to allow deposition of the dielectric layer 315 after contacting the GaN mesa similar but smaller, generally about 4 to 8 μm, or more particularly 5 to 7 μm, or more particularly about It has a height of 6 μm. In this exemplary aspect, the first terminal 125 formed from the metal layers 120A and 120B is also passivated 135 , which not only provides insulation and protection from contact of the first conductor 310 , but also the first terminal 125 . It can act to help the structural integrity of the product, and helps to protect it from the various forces applied in the printing process. In exemplary aspects, the width of the diode 100L (vertex to vertex, not face to face, generally across a hexagonal shape) is between about 10 and 50 μm, or more particularly between about 20 and 30 μm, or more particularly between about 22 and 28 μm, or more particularly about 25 to 27 μm, or more particularly about 25.5 to 26.5 μm, or more particularly about 26 μm. The height of the diode 100L is, in exemplary embodiments, generally from about 8 to 15 μm, or more particularly from 9 to 12 μm, or more particularly from about 10.5 to 11.5 μm.

More generally, it is noted that the size of two-terminal devices can be larger, such as about 10 to 75 μm in diameter (measured either in width or length depending on shape, face-to-face), and about 5 to 25 μm in height. It should be noted

25 is a cross-sectional view through a portion of a composite GaN heterostructure (or GaN mesa) (n+ GaN layer 110, quantum well region 185, p+ GaN layer 115) and metal layers 120A, 120B, outside and through the composite GaN heterostructure; and/or interior surfaces, eg, any geometry and texture of the surfaces of the p+ GaN layer 115 or the n+ GaN layer 110 or the additional silver or mirror layer 103 . Any of the various features illustrated in FIG. 25 may be applied as an option for any of the various exemplary diodes 100 - 100L. 1-24, the outer and/or inner surfaces of the composite GaN heterostructure may be relatively smooth. As illustrated in FIG. 25 , any of a variety of external and/or internal surfaces of the composite GaN heterostructure may be fabricated to have any of a variety of textures, geometries, mirrors, reflectors, or other surface treatments. For example, and not by way of limitation, the outer (top or top) surface (illustrated as n+ GaN layer 110 ) of the composite GaN heterostructure reduces internal reflection and enhances light extraction, for example within diode 100-100L embodiments. To increase, it may be etched to provide a surface roughness 112 (illustrated as a jagged cone or pyramidal structure). Additionally, external surfaces of the composite GaN heterostructure (eg, surfaces of the p+ GaN layer 115 or n+ GaN layer 110 ) may also include, but are not limited to, a dome or lens shape 116 ; toroidal, honeycomb, or waffle shape 118; It may be masked and etched or fabricated to have various geometries such as stripes 113, or other geometries (eg, hexagons, triangles, etc.) 117 . Still further, the sides 121 may also include various mirrors or reflectors 109 such as dielectric reflectors (eg SiO ₂ /Si ₃ N ₄ ) or metallic reflectors. A wide range of surface treatments and reflectors are described, for example, in US Pat. No. 7,704,763, issued Apr. 27, 2010 (Fujii et al.), US Pat. No. 7,897,420, issued Mar. 1, 2011 (Chu et al.), 2010 US Patent Application Publication No. 2010/0295014 A1 (Kang et al.), issued November 25, 2010, and US Patent No. 7,825,425 (Shum), issued November 2, 2010, both of which are herein incorporated by reference. is incorporated by reference in Additional surface textures and geometries are illustrated in FIGS. 104-108.

25, the inner surfaces of the composite GaN heterostructure (or more generally diodes 100-100L) can also be fabricated to have any of a variety of textures, geometries, mirrors, reflectors, or other surface treatments. have. As illustrated, for example and not by way of limitation, the reflective layer 103 provides light reflection towards the exposed surfaces of the diodes 100 - 100L by using a silver layer applied in the manufacturing process (prior to the manufacturing of the metal layers 102A, 102B). and may be used to increase light extraction, the silver layer may be smooth (111) or may have a textured surface (107). Also, for example and not by way of limitation, the inner surface of the composite GaN heterostructure may have a smooth or textured surface, for example, by using an additional layer 108, which may be a diffusive n-type InGaN material. Additionally, any of these various optional surface geometries and textures may be used alone or in combination with each other, such as a dual-diffusing structure having both an outer surface texture 112 and an inner surface texture 107 and/or a reflective layer 103 . and can be used Irrespective of any surface treatment that may or may not be used, any of a variety of optional layers may also be used for additional reasons to use an n-type InGaN material for layer 108 to provide better ohmic contact.

Diodes 100-100L are generally less than about 450 microns in all dimensions, more specifically less than about 200 microns in all dimensions, more specifically less than about 100 microns in all dimensions, and more specifically less than 50 microns in all dimensions. . In the exemplary embodiments shown, the diodes 100-100L are generally about 10-50 μm wide, or more specifically about 20-30 μm wide, and about 5-25 μm high, or more particularly 5-15 μm high. , or about 25 to 28 μm in diameter (measured face-to-face, not end-to-end) and 10 to 15 μm in height. In exemplary aspects, the height of the diode 100-100L (ie, the height of the sides 121 comprising the GaN heterostructure) excluding the metal layer 120B or 122 forming the bump or protrusion structure is, according to the above aspect, about 2 to 15 μm, or more specifically about 2 to 4 μm, or more specifically 7 to 12 μm, or more specifically 8 to 11 μm, or more specifically 9 to 10 μm, or more specifically Although less than 10-30 μm, the height of the metal layer 120B forming the bump or protrusion structure is generally about 3-7 μm. Since the dimensions of the diodes are machined to be within the tolerances selected during device manufacturing, the dimensions of the diodes may be determined by, for example, but not limited to, an optical microscope (which may also include software for measurement), a scanning electron microscope. Fraunhofer diffraction to measure particle size (and particle size distribution) while particles are present in dilute solution (SEM), which may be, for example, diode ink or any other liquid or gel, using a Horiba LA-920, or Horiba LA-920. (Fraunhofer diffraction) and light scattering. Any size or other measurement of a diode 100-100L should be considered an average (eg, centroid and/or median) of a plurality of diodes 100-100L, and will vary significantly depending on the aspect selected (eg, diode 110 to 100J, or 100K, or 100L will generally all have different individual values).

Diodes 100-100L may be fabricated using any semiconductor fabrication techniques currently known or developed in the future. 26-66 illustrate a number of exemplary methods of making exemplary diodes 100 - 100L, and illustrate several additional exemplary diodes 100H, 100I and 100J (cross-section). Those of skill in the art will appreciate that many of the various steps of manufacturing a diode 100-100L may occur in any of a variety of orders, may be omitted or included in other orders, and may result in multiple diode structures, not just those illustrated. you will realize that you can For example, FIGS. 38-44 illustrate the fabrication of a diode 100H comprising both central and peripheral through (or deep) vias 131 and 134, respectively, with or without an optional second (double) side metal layer 122. While the combined features of 100D and 100G are illustrated, FIGS. 45-50 illustrate the fabrication of a diode 100I comprising an outer via 133 with or without an optional second (back) side metal layer 122, which is a central or combined with other illustrated fabrication steps to include peripheral through vias 131 and 134, eg to form diode 100F.

26, 27, and 29-37 are cross-sectional views illustrating exemplary methods of manufacturing diodes 100, 100A, 100B, 100C in accordance with the teachings of the present invention, and FIGS. 26-29 illustrate fabrication at the wafer 150 level, and FIG. 30-37 illustrate fabrication at the diode 100, 100A, 100B, 100C levels. The various illustrated fabrication steps may also be used to form other diodes 100D-100L, and FIGS. 26-32 may be applied to any of diodes 100-100L depending on the substrate 105, 105A selected. 26 and 27 are cross-sectional views of a wafer 150 (eg, a silicon wafer) having a silicon dioxide (or “oxide”) layer 190 . 28 is a top (or top) view of a silicon wafer 150 having a silicon dioxide layer 190 etched in a grating pattern. The oxide layer 190 (typically about 0.1 μm thick) is deposited or grown over the wafer 150, as shown in FIG. As illustrated in FIG. 27 , portions of the oxide layer 190 are removed, via suitable or standard mask and/or photoresist layers and etching, as is known in the art, and as illustrated in FIG. 28 , the oxide 190 remains in a grid pattern (also referred to as “street”).

29 shows buffer layer 145, silicon dioxide (or “oxide”) layer 190, and GaN layers (in an exemplary embodiment, epitaxially grown or deposited to a thickness of typically about 1.25 to 2.50 μm, but to a smaller or greater thickness; also within the scope of the present disclosure) is a cross-sectional view of a wafer 150 (eg, a silicon wafer) with polycrystalline GaN 195 on the oxide 190 , and n+ GaN forming a composite GaN heterostructure as mentioned above. Illustrated as layer 110 , quantum well region 185 and p+ GaN layer 115 . As indicated above, a buffer layer 145 (eg, aluminum nitride or silicon nitride and generally about 25 Angstroms thick) is deposited over the silicon wafer 150 to facilitate subsequent GaN deposition. Polycrystalline GaN 195 grown or deposited over the oxide 190 may be subjected to stresses and/or strains (e.g., thermal due to mismatch) and usually has a single crystal structure. Other equivalent methods within the scope of the present invention for providing such stress and/or strain reduction include, for example, roughening the surface of silicon wafer 150 and/or buffer layer 145 in selected areas so that corresponding GaN regions are formed. This includes, but is not limited to, not having a single crystal, or etching trenches in the silicon wafer 150 so that there are no continuous GaN crystals throughout the wafer 150. These street formation and stress reduction fabrication steps may be omitted if other exemplary fabrication methods are used, for example other substrates such as GaN (Substrate 105) 150A on sapphire wafer. GaN deposition or growth to form composite GaN heterostructures may be provided via any selected process known in the art or known in the art and/or may be proprietary to the device manufacturer. In an exemplary embodiment, a composite GaN heterostructure composed of an n+ GaN layer 110, quantum well regions 185, and p+ GaN layer 115 is prepared by, for example, but not limited to, Blue Photonics, Inc. of Walnut, CA. Inc.) and other vendors.

30 is a cross-sectional view of a substrate 105 having a buffer layer 145 and a composite GaN heterostructure (n+ GaN layer 110, quantum well region 185 and p+ GaN layer 115) in accordance with the teachings of the present invention, illustrating the fabrication of single diodes 100-100L; To illustrate, a much smaller portion of wafer 150 (eg region 191 in FIG. 29 ) is illustrated. Through suitable or standard mask and/or photoresist layers and etching as known in the art, the composite GaN heterostructure (n+ GaN layer 110, quantum well region 185 and p+ GaN layer 115) is shown in FIGS. 31 and 32 . Etched to form a GaN mesa structure 187 as illustrated, FIG. 32 illustrates a GaN mesa structure 187A having relatively more angled faces, which may potentially facilitate light generation and/or absorption. Other GaN mesa structures 187 may also be implemented, such as partially or substantially toroidal GaN mesa structures 187 , as illustrated in FIGS. 10 , 13 , 14 , 17 , 20 , 22 , 39 - 44 , and 66 . After the GaN mesa etch, a via etch (shallow or blind) is performed, as illustrated in FIG. 33 , also via suitable or standard mask and/or photoresist layers and etching as known in the art, A relatively shallow trench 186 is made in the silicon substrate 105 through the layers and the buffer layer 145 .

Also via suitable or standard mask and/or photoresist layers and etching as known in the art, followed by deposition of metallization layers, metal contact 120A to p+ GaN layer 115 , as illustrated in FIG. 34 . to form a via 130 . In exemplary embodiments, several metal layers are deposited, a first or a first comprising two metal layers, typically nickel followed by gold (about 50-200 Angstroms each), to form an ohmic contact to the p+ GaN layer 115 . Depositing the initial layer followed by annealing at about 450-500° C. under an oxidizing atmosphere of about 20% oxygen and 80% nitrogen to raise the nickel to the top with the nickel oxide layer, and relatively good ohmic contact with the p+ GaN layer 115 A metal layer (as part of 120A) having As another example, in a diode 100L fabrication process (and other exemplary diode 100-100K aspects), a top GaN layer (illustrated as a p+ GaN layer 115 , as illustrated in FIG. 25 , but may be other types of GaN layers) to facilitate the formation of an ohmic contact (and potentially provide light reflection to the n+ GaN layer 110 ), a very thin optically reflective metal layer (illustrated as silver layer 103 in FIG. 25 ), and/or It may be metallized and alloyed with an optically transmissive metal layer (not separately illustrated), such as nickel-gold or nickel-gold-nickel, about 100 Å thick, some of which may be deposited on other GaN layers, for example during GaN mesa formation. is removed by Another metallization layer may also be deposited, for example, to form a thicker interconnect metal to the contour and full metal layer 120A (eg, for current distribution) and to form vias 130 . In another exemplary embodiment (illustrated in FIGS. 45-50 ), the metal contact 120A forming the ohmic contact to the p+ GaN layer 115 may be formed prior to GaN mesa etching, after GaN mesa etching, via an etchant, or the like. Numerous other metallization processes and corresponding materials, including metal layers 120A and 120B, are also within the scope of this disclosure, and different manufacturing facilities often use different processes and material choices. For example, and not by way of limitation, either or both of the metal layers 120A and 120B can be deposited with titanium to form an adhesion or seed layer typically 50-200 Angstroms thick, followed by a thin layer of nickel, and gold of 2-4 μm. or "flash" (a "flash" of gold is a layer about 50-500 Angstroms thick), depositing 3-5 μm of aluminum, followed by a “flash” of nickel (about 0.5 μm, physical vapor deposition or plating) and gold ", depositing titanium, followed by gold, followed by nickel (typically 3-5 μm thick for 120B), followed by gold, or aluminum followed by nickel, then gold, etc. have. Additionally, the height of the metal layer 120B forming the bump or protruding structure is also, in exemplary embodiments, the thickness of the substrate 105 (e.g. For example, GaN at about 7 to 8 μm versus silicon at about 10 μm), and may typically vary from about 3.5 to 5.5 μm.

For each subsequent singulation of diodes 100-100L from wafer 150, apply appropriate or standard mask and/or photoresist layers as known in the art, as illustrated in FIG. 35 and other FIGS. 40 and 48 . and etching to form trenches 155 around each diode 100 - 100L (eg, as illustrated in FIGS. 2 , 5 , 7 and 9 ). The trenches 155 are generally about 3-5 μm wide and 10-12 μm deep. Also, as illustrated in FIG. 36 , plasma-enhanced chemical vapor deposition of silicon nitride using, for example, but not limited to, suitable or standard mask and/or photoresist layers and etching as known in the art ( PECVD), followed by photoresist and etching steps to remove unwanted areas of silicon nitride, a nitride passivation layer 135 is grown or deposited, typically to a thickness of about 0.35 to 1.0 μm. In other exemplary aspects, the sidewalls of such singulating trenches may or may not be passivated. Bumps or protrusions, typically having a height of 3-5 μm, as illustrated in FIG. 37 , are then formed through suitable or standard mask and/or photoresist layers and etching as known in the art. A metal layer 120B is formed. In an exemplary embodiment, the formation of the metal layer 120B is performed in several steps using a metal seed layer followed by further metal deposition using an electroplating or lift-off process, removing the resist, and removing the Clean the area. In addition to subsequent singulation of diodes from wafer 150 (in this case diode 100, 100A, 100B, 100C), as described below, diodes 100, 100A, 100B, 100C are otherwise completed, and these completed diodes 100, It should be noted that 100A, 100B, and 100C have only one metal contact or terminal (first terminal 125) on the top surface of the respective diodes 100, 100A, 100B, 100C. Optionally, the second (back) side metal layer 122 may be fabricated, for example to form the second terminal 127, as described below and mentioned above with reference to other exemplary diodes.

38-44 illustrate another exemplary method of manufacturing a diode 100-100L, FIG. 38 illustrates fabrication at the wafer 150A level, and FIGS. 39-44 illustrate fabrication at the diode 100-100L level. 38 is a cross-sectional view of wafer 150A having a substrate 105 and a composite GaN heterostructure (n+ GaN layer 110, quantum well region 185, and p+ GaN layer 115). In this exemplary embodiment, a relatively thick layer of GaN is grown or deposited over sapphire 106 (of sapphire wafer 150A) (to form substrate 105), followed by a GaN heterostructure (n+ GaN layer 110, quantum well region 185; and p+ GaN layer 115) is deposited or grown.

Figure 39 is a cross-sectional view of a substrate 105 having a third mesa-etched composite GaN heterostructure, to illustrate the fabrication of a single diode (e.g., diodes 100H, 100K), a much smaller portion of wafer 150A (e.g. For example, area 192 of FIG. 38 is illustrated. The composite GaN heterostructure (n+ GaN layer 110, quantum well region 185 and p+ GaN layer 115) is etched through suitable or standard mask and/or photoresist layers and etching as known in the art to form a GaN mesa to form structure 187B. After the GaN mesa etch, via trench (through or deep) and singulation trench, as illustrated in FIG. 40 , also through suitable or standard mask and/or photoresist layers and etch as is known in the art. etching is performed to fabricate one or more relatively deep via trenches 188 through the non-mesa portion of the GaN heterostructure (n+ GaN layer 110) and through the GaN substrate 105 through the sapphire 106 of the wafer 150A; , to fabricate the above-described singulation trenches 155 . As illustrated, a central via trench 188 and a plurality of peripheral via trenches 188 are formed. For the diode 100K aspect, a shallow or blind via etch may be performed in the center of the mesa structure 187B without forming any peripheral vias or trenches.

Further, ohmic contact with the n+ GaN layer 110 is then achieved by depositing metallization layers via etching and appropriate or standard mask and/or photoresist layers and etching as is known in the art, as illustrated in FIG. 41 . forming a central through via 131 and a plurality of peripheral through vias 134 . In exemplary aspects, several metal layers may be deposited to form the through vias 131 , 134 . For example, titanium and tungsten are sputtered to cover the faces and the bottom of trench 188, a seed layer is formed, and then plated with nickel to form solid metal vias 131 and 134.

Further, ohmic contact with the p+ GaN layer 115 is then achieved by depositing metallization layers via appropriate or standard mask and/or photoresist layers and etching, as illustrated in FIG. 42 , as is known in the art. A metal layer 120A is provided. In exemplary aspects, several metal layers may be deposited as described above to form an ohmic contact to the metal layer 120A and the p+ GaN layer 115 . Also, as illustrated in FIG. 43 , plasma enhanced chemistry of silicon nitride or silicon oxynitride, including but not limited to, using suitable or standard mask and/or photoresist layers and etching as is known in the art. A nitride passivation layer 135 is grown or deposited, typically to a thickness of about 0.35 to 1.0 μm, by deposition (PECVD) followed by photoresist and etching steps to remove unwanted areas of silicon nitride. Then, as illustrated in FIG. 44 , a metal layer 120B having a bump or protrusion structure is formed via suitable or standard mask and/or photoresist layers and etching as known in the art. In an exemplary embodiment, as also described above, the formation of the metal layer 120B is performed in several steps using a metal seed layer, followed by further metal deposition using an electroplating or lift-off process, followed by removal of the resist. and washing the area of the seed layer. In addition to subsequent singulation of diodes from wafer 150A (diode 100H in this case), as described below, the diode 100H is otherwise completed, and these completed diodes 100H have only one on top surface of each diode 100H. It should be noted that it has metal contacts or terminals (first terminal 125 ). Also optionally, a second (back) side metal layer 122 may be fabricated, for example to form a second terminal 127, as described below and referenced above with reference to other exemplary diodes.

45-50 illustrate another exemplary method of manufacturing a diode 100-100L, FIG. 45 illustrates fabrication at a wafer 150 or 150A level, and FIGS. 46-50 illustrate fabrication at a diode 100-100L level do. 45 is a buffer layer 145, a composite GaN heterostructure (n+ GaN layer 110, quantum well region 185, and p+ GaN layer 115), and a metallization (metal layer 120A) forming an ohmic contact with the p+ GaN layer. It is a cross-sectional view of the board|substrate 105. As mentioned above, the buffer layer 145 is typically prepared when the substrate 105 is silicon (eg, using a silicon wafer 150), and may be omitted for other substrates such as a GaN substrate 105. Additionally, sapphire 106 is exemplified as optional, as in the case of thick GaN substrate 105 grown or deposited over sapphire wafer 150A. Also, as mentioned above, the metal layer 119 (as a seed layer for the subsequent deposition of the metal layer 120A) is not at a later stage of diode fabrication, but at an earlier stage, the GaN heterostructure (n+ GaN layer 110, both It is deposited after deposition or growth of the well region 185, and the p+ GaN layer 115). For example, the metal layer 119 may be a nickel and gold flash having a total thickness of about several hundred Å, or to facilitate the formation of an ohmic contact (and potentially also provide light reflection for the n+ GaN layer 110 ); may be metallized and alloyed with a very thin optically reflective metal layer (illustrated as silver layer 103 in FIG. 25 ), and/or with an optically transmissive metal layer such as nickel-gold or nickel-gold-nickel about 100 Angstroms thick, these Some of it is removed by other GaN layers, for example during GaN mesa formation.

46 is a cross-sectional view of a substrate having a buffer layer, a fourth mesa-etched composite GaN heterostructure, and a metallization (metal layer 119) forming an ohmic contact with the p+ GaN layer, and a single diode (eg, a diode). To illustrate the fabrication of 100I), a much smaller portion of wafer 150 or 150A (eg region 193 in FIG. 45 ) is illustrated. The composite GaN heterostructure (n+ GaN layer 110 , quantum well region 185 and p+ GaN layer 115 ) (metal layer 119 ) via suitable or standard mask and/or photoresist layers and etching as known in the art. ) to form a GaN mesa structure 187C (along with the metal layer 119). After the GaN mesa etch, a metallization is deposited (optional process and using the metals described above, such as titanium and aluminum, followed by annealing), forming a metal layer 120A, and also forming a metal layer 129 having an ohmic contact with the n+ GaN layer 110 .

After the metallization, also via suitable or standard mask and/or photoresist layers and etching known or known in the art, non-mesa portions of the GaN heterostructure ( through the n+ GaN layer 110 , and relatively deep into or through the substrate 105 (eg, through the GaN substrate 105 to the sapphire 106 of the wafer 150A, or as described above of the silicon substrate 105 ). through the portion) perform a singulation trench etch, and fabricate the singulation trench 155 described above.

Also, as illustrated in FIG. 49 , metallization layers are deposited into trench 155 through appropriate or standard mask and/or photoresist layers and etching as known in the art, through or deep outer via 133 , as illustrated in FIG. to provide conduction around the entire outer or lateral perimeter of the diode 100I, which also forms an ohmic contact with the n+ GaN layer 110 . In exemplary aspects, several metal layers may be deposited to form the through outer via 133. For example, titanium and tungsten are sputtered to cover the faces and the bottom of the trench 155, a seed layer is formed, and then plated with nickel to form a solid metal outer via 133.

Again, as illustrated in FIG. 50 , plasma-enhanced chemical vapor deposition of, for example, but not limited to, silicon nitride using suitable or standard mask and/or photoresist layers and etching as known in the art ( PECVD), followed by photoresist and etching steps to remove unwanted areas of silicon nitride, a nitride passivation layer 135 is grown or deposited, typically to a thickness of about 0.35 to 1.0 μm. A metal layer 120B having bumps or protruding structures is then formed as described above, as illustrated in FIG. 50 , via suitable or standard mask and/or photoresist layers and etching as known in the art. . In addition to subsequent singulation of diodes from wafer 150 or 150A (diode 100I in this case), as described below, diode 100I is otherwise completed, and these completed diodes 100I have only one over the top surface of each diode 100I. It should be noted that it has a metal contact or terminal (also first terminal 125) of Also optionally, a second (back) side metal layer 122 may be fabricated, for example to form a second terminal 127, as described below and referenced above with reference to other exemplary diodes.

51-57, 67 and 68 illustrate another exemplary method of manufacturing a diode 100K, following the fabrication at the wafer 150 or 150A level illustrated in FIG. 45 . 51 is a cross-sectional view of a substrate having a buffer layer, a fifth mesa-etched composite GaN heterostructure 187D, and a metallization forming an ohmic contact with a p+ GaN layer. As mentioned above, the buffer layer 145 is typically fabricated when the substrate 105 is silicon (eg, using a silicon wafer 150), and may be omitted for other substrates such as a GaN substrate 105. Additionally, sapphire 106 is illustrated as optional as in the case of thick GaN substrate 105 grown or deposited over sapphire wafer 150A, in which case the buffer layer 145 may be omitted. Also, as mentioned above, the metal layer 119 (as a seed layer for the subsequent deposition of the metal layer 120A) is not at a later stage of diode fabrication, but at an earlier stage, the GaN heterostructure (n+ GaN layer 110, quantum well). region 185, and after deposition or growth of the p+ GaN layer 115). For example, the metal layer 119 may be a nickel and gold flash having a total thickness of about several hundred Å, or to facilitate the formation of an ohmic contact (and potentially also provide light reflection for the n+ GaN layer 110 ); may be metallized and alloyed with a very thin optically reflective metal layer (illustrated as silver layer 103 in FIG. 25 ), and/or with an optically transmissive metal layer such as nickel-gold or nickel-gold-nickel about 100 Angstroms thick, these Some of it is removed by other GaN layers, for example during GaN mesa formation. The composite GaN heterostructure (n+ GaN layer 110 , quantum well region 185 and p+ GaN layer 115 ) (metal layer 119 ) via suitable or standard mask and/or photoresist layers and etching as known in the art. etched (with metal layer 119) to a depth of about 1 μm having a toroidal shape (measured face-to-face) with a generally inner annular diameter of about 14 μm and an external general hexagonal diameter of about 26 μm (with metal layer 119) Form the GaN mesa structure 187D.

After the GaN mesa etch 187D, also through suitable or standard mask and/or photoresist layers and etching known or known in the art, a blind or shallow via trench as illustrated in FIG. 52 is formed. Thus, a relatively shallow central via trench 211 is fabricated in the non-mesa portion (n+ GaN layer 110) of the GaN heterostructure. As illustrated, an annular central via trench 211 having a depth of about 2 μm and a diameter of 6 μm is formed.

Then, via suitable or standard mask and/or photoresist layers and etching as is known in the art, as illustrated in FIG. 53 , metallization layers are deposited to form a central via 136, which is also An ohmic contact with the n+ GaN layer 110 is formed. In exemplary aspects, several metal layers (eg, via metal) are deposited to form the central via 136 . For example, about 100 Å of titanium and about 1.5-2 μm of aluminum may be sputtered or plated to cover a portion of the faces, bottom, and top of the trench 211, and then alloyed at about 550° C., the n+ GaN layer 110 A solid metal via 136 with a maximum diameter of about 10 μm is formed on the upper part of the Further, as illustrated in FIG. 54 , a plasma of, for example, but not limited to, silicon nitride or silicon oxynitride is then followed using suitable or standard mask and/or photoresist layers and etching as known in the art. Enhanced chemical vapor deposition (PECVD) followed by photoresist and etch steps to remove unwanted areas of silicon nitride, the first nitride passivation layer 135A generally having a thickness of about 0.35 to 1.0 μm, more particularly about 0.5 μm and Grow or deposit to a maximum diameter of about 18 μm.

Also, as illustrated in FIG. 55 , metallization layers are then deposited via appropriate or standard mask and/or photoresist layers and etching as is known in the art, typically formed using die metal. A metal layer 120B having bumps or protrusions for contact to the p+ GaN layer 115 is formed. In exemplary aspects, several metal layers may be deposited as described hereinabove to form metal layer 120A and/or 120B for contact to p+ GaN layer 115, which is described herein for brevity. will not be repeated. In an exemplary embodiment, the metal layer 120B is generally hexagonal in shape, has a diameter (measured face-to-face) of about 22 μm, about 100 Å nickel, about 4.5 μm aluminum, about 0.5 μm nickel. , and about 100 nm of gold.

After the metallization, also as illustrated in FIG. 56 , through suitable or standard mask and/or photoresist layers and etching known or known in the art, using the methods described above, the GaN hetero A singulation trench etch is performed through a portion of the structure (within but not completely through the n+ GaN layer 110 ), generally to a depth of about 2 μm in an exemplary embodiment, to fabricate the singulation trench 155 described above.

Then, as illustrated in FIG. 57 , the second nitride passivation layer 135 is then deposited, for example, but not limited to, by plasma enhanced chemical vapor deposition (PECVD) of silicon nitride or silicon oxynitride, generally about 0.35 to 1.0 μm, or more particularly It is grown or deposited to a thickness of about 0.5 μm. Then, using suitable or standard mask and/or photoresist layers and etching as known in the art, the silicon nitride of the unwanted area is removed, for example cleaning the top of the metal layer 102B, which 2 will form terminal 127.

Subsequent substrate removal, singulation and fabrication of the second (back) side metal layer 122 is described below with reference to FIGS. 64 , 65 , 67 and 68 .

58-63 and 69 illustrate another exemplary method of manufacturing a diode 100L, following the fabrication at the wafer 150 or 150A level illustrated in FIG. 45 . 58 is a cross-sectional view of a substrate having a buffer layer, a sixth mesa-etched composite GaN heterostructure 187E, and a metallization forming an ohmic contact with a p+ GaN layer. As mentioned above, the buffer layer 145 is typically fabricated when the substrate 105 is silicon (eg, using a silicon wafer 150), and may be omitted for other substrates such as a GaN substrate 105. Additionally, sapphire 106 is illustrated as optional, as in the case of thick GaN substrate 105 grown or deposited over sapphire wafer 150A, in which case the buffer layer 145 may be omitted. Also, as mentioned above, the metal layer 119 (as a seed layer for the subsequent deposition of the metal layer 120A) is not at a later stage of diode fabrication, but at an earlier stage, the GaN heterostructure (n+ GaN layer 110, quantum well). region 185, and after deposition or growth of the p+ GaN layer 115). For example, the metal layer 119 may be a nickel and gold flash having a total thickness of about several hundred Å, or to facilitate the formation of an ohmic contact (and potentially also provide light reflection for the n+ GaN layer 110 ); metallization with a very thin optically reflective metal layer (illustrated as silver layer 103 in FIG. 25 ), and/or an optically transmissive metal layer such as nickel, nickel-gold or nickel-gold-nickel, from about 100 Å to about 2.5 nm thick and may be alloyed, some of which are then removed by other GaN layers, for example during GaN mesa formation. In an exemplary embodiment, about 2-3 nm, or more particularly about 2.5 nm of nickel or nickel and gold are deposited and alloyed at 500° C. to form metal layer 119 in p+ GaN layer 115 . The composite GaN heterostructure (n+ GaN layer 110 , quantum well region 185 and p+ GaN layer 115 ) (metal layer 119 ) via suitable or standard mask and/or photoresist layers and etching as known in the art. (with metal layer 119) to obtain a first radius of about 8 μm for the cut-out area leaving room for contact 128 (with metal layer 119) and a second radius of about 11 μm for the triangular vertices/faces. GaN mesa structure 187E of about 1 μm deep having the above-discussed planarization triangular shape with

After the GaN mesa etch 187E, first metallization layers are also deposited via suitable or standard mask and/or photoresist layers and etch as is known in the art, as illustrated in FIG. 59 . to form a contact 128, which also forms an ohmic contact with the n+ GaN layer 110. In exemplary aspects, several via metal layers are deposited to form a contact 128 used as the second terminal 127 . For example, and not by way of limitation, sputtering or plating about 100 Angstroms of titanium, about 500 nm of aluminum, 500 nm of nickel, and 100 nm of gold, as illustrated in FIG. It forms a solid metal contact 128 that is about 3 μm wide and extends around the perimeter of the n+ GaN layer 110 .

After deposition of the contacts 128, further metallization may be deposited via suitable or standard mask and/or photoresist layers known or known in the art (optional process), as illustrated in FIG. 60 . and metals described above, such as titanium and aluminum, followed by annealing) to form metal layer 120A as part of the ohmic contact for p+ GaN layer 115 . For example, in an exemplary embodiment, about 200 nm of silver (which forms a reflective or mirror layer), 200 nm of nickel, about 500 nm of aluminum, and 200 nm of nickel are sputtered or plated to achieve a thickness of about 1.1 μm and a diameter of about 8 Form a centrally located metal layer 120A, in μm.

Further, additional metallization layers may then be deposited, typically using die metal, via appropriate or standard mask and/or photoresist layers and etching as is known in the art, as illustrated in FIG. 61 , Deposited to form a metal layer 120B having bumps or protrusions for contact to the p+ GaN layer 115 . In exemplary aspects, several metal layers may be deposited as described hereinabove to form metal layer 120A and/or 120B for contact to p+ GaN layer 115, which is repeated herein for brevity. it won't be In an exemplary embodiment, the metal layer 120B, after alloying at 550° C. for about 10 minutes under a nitrogen environment, has a first radius to cut-out area (for contact 128) of about 6 μm, and triangular vertices/faces having a second radius of about 9 μm for (they are each about 3.7 μm wide), generally having the flattening triangular shape illustrated in FIG. 23, plus a height of about 1.1 μm of the metal layer 120A, plus about 5 μm for a total height of about 200 nm of silver (which also forms a reflective or mirror layer over the p+ GaN layer 115), about 200 nm of nickel, about 200 nm of aluminum, about 250 nm of nickel, about 200 nm of aluminum, about 250 nm of nickel, and about 100 nm of gold, each added as a continuous layer. It should be noted that this provides a separation of approximately 5 μm high between the first terminal 125 and the second terminal 127 .

62 , the second nitride passivation layer 135 is then applied, for example, but not limited to, by plasma enhanced chemical vapor deposition (PECVD) of silicon nitride or silicon oxynitride, generally between about 0.35 and 1.0 μm, or more particularly It is grown or deposited to a thickness of about 0.5 μm. Then, using suitable or standard mask and/or photoresist layers and etching as known in the art, the silicon nitride of the unwanted area is removed, for example cleaning the top of the metal layer 102B, which 1 will form terminal 125.

After the passivation, using the methods described above, also through suitable or standard mask and/or photoresist layers and etching known or known in the art, as illustrated in FIG. 63 , the GaN hetero Through a portion of the structure (within but not completely through the n+ GaN layer 110 ), a singulation trench etch is performed, typically to a depth of about 2 to 3.5 μm in an exemplary embodiment, to fabricate the singulation trench 155 described above.

Subsequent substrate removal and singulation are described below with reference to FIGS. 64 , 65 , 67 and 69 .

Numerous variations of the methodology for the fabrication of diodes 100-100L may be readily apparent in light of the teachings of the present disclosure, all of which are considered equivalent and within the scope of the present disclosure. In other exemplary aspects, such trench 155 formation and (nitride) passivation layer formation may be performed earlier or later in the device fabrication process. For example, trench 155 may be formed later after formation of metal layer 120B during fabrication, leaving substrate 105 exposed, or a second passivation may be subsequently formed. Also, for example, trench 155 may be formed following deposition of the (nitride) passivation layer 135 earlier in fabrication, eg, after GaN mesa etching. In the latter example, the passivated trench 155 may be filled with oxide, photoresist, or other material (using a photoresist mask and etch or unshielded etch process to maintain planarization during the remainder of the device fabrication process) A layer is deposited after removing the areas), and can be filled with resist (and potentially recharged after metal contact 120A formation). In another example, silicon nitride 135 deposition (after mask and etch steps) can be performed after GaN mesa etch and before metal contact 120A deposition.

64 is a cross-sectional view illustrating an exemplary silicon wafer 150 embodiment having a plurality of diodes 100-100L attached to a support device 160 (eg, a holding, handle, or holder wafer). 65 is a cross-sectional view illustrating an exemplary diode sapphire wafer 150A embodiment attached to a support device 160 . As illustrated in FIGS. 64 and 65 , diode wafers 150 , 150A containing a plurality of undeformed diodes 100 - 100L (generally illustrated without any significant detail for illustrative purposes) are fabricated diode 100 A diode wafer 150 with 100L to 100L is attached to a support device 160 (eg, a wafer holder) on the first side of 150A using any known commercially available wafer adhesive or wafer bond 165 . As illustrated and described above, a singulation or singulation trench 155 between each diode 100-100L is formed during wafer processing, for example via etching, and adjoins each diode 100-100L without a mechanical process such as sawing. is used to isolate from the diode 100 to 100L. 64 , while the diode wafer 150 is still attached to the support device 160 , a second, back side 180 of the diode wafer 150 may be etched, such as, but not limited to, to expose the trench 155 , or subsequently etched. It can be etched (eg wet or dry etched) to some level (illustrated by dashed lines), mechanically ground and polished, or both, to leave some additional substrate that can be removed via . When sufficiently etched or ground and polished or both have been performed (and/or with any further etching), each individual diode 100 - 100L is released from each other while still attached to support device 160 with adhesive 165 and any It is also released from the remaining diode wafer 150. As illustrated in FIG. 65 , a second, back side 180 of diode wafer 150A is exposed to laser light (illustrated as one or more laser beams 162 ), while diode wafer 150A is still attached to support device 160 , which in turn is Cleave the GaN substrate 105 from the sapphire 106 of wafer 150A (illustrated by the dashed line) (also referred to as laser lift-off) followed by any further chemical-mechanical polishing and any necessary etching (e.g. , wet or dry etching), each individual diode 100 - 100L is released from each other and also from wafer 150A while still attached to the support device 160 with adhesive 165. In this exemplary aspect, the wafer 150A may then be ground and/or polished and reused.

Additionally, epoxy beads (not separately illustrated) are placed around the perimeter of the wafer 150 to prevent release of non-diode fragments from the wafer edge into the diode 100 - 100L fluid during the diode release process generally discussed below. Apply.

66 is a cross-sectional view illustrating an exemplary diode 100J embodiment attached to a support device. After singulation of the diodes 100-100K (as described above with reference to FIGS. 64 and 65), a second, backside of the diodes 100-100K, while the diodes 100-100K are still attached to the support device 160 with adhesive 165. this is exposed As illustrated in FIG. 66 , a second, backside metallization is then deposited (angled to avoid filling trench 155), for example via vapor deposition, followed by a second, backside metallization layer 122 and a diode. Forms 100J aspect. Also, as illustrated, the diode 100J has an ohmic contact with the n+ GaN layer 110 and an ohmic contact with the second, back side metal layer 122 for current conduction between the n+ GaN layer 110 and the second, back metal layer 122. and has one central through via 131. Exemplary diode 100D is very similar to exemplary diode 100J having a second, backside metal layer 122 to form a second terminal 127 . As mentioned above, the second, backside metal layer 122 (or substrate 105 or any of the various through vias 131, 133, 134) may be used in devices 300, 300A, 300B, 300C, to energize diodes 100-100K; It can be used to make an electrical connection with the first conductor 310 in 300D, 720, 730, 760.

67 is a cross-sectional view illustrating an exemplary tenth embodiment of a diode prior to backside metallization attached to a support device 160 . As illustrated in FIG. 67, an exemplary diode in process is singulated, any substrates 105, 105A are removed as described above, and also an n+ GaN layer by an etching step (eg, wet or dry etching). Expose the surfaces of 110 and via 136, leaving the composite GaN heterostructure to a depth of about 2-6 μm (or more particularly about 2-4 μm, or more particularly about 3 μm). Then, as shown in FIG. 68, a second, backside, for example via sputtering, plating or deposition, using appropriate or standard mask and/or photoresist layers and etching as known in the art. A second, backside metal layer 122 and a diode 100K aspect are formed by depositing a metallization thereon. In an exemplary embodiment, the metal layer 122, as illustrated in FIG. 21 , is generally about 12 to 16 μm wide about the major axis, about 4 to 8 μm wide about the minor axis and 4 to 6 μm deep, or more particularly generally It has an elliptical shape with a width of about 14 μm about its major axis, a width of about 6 μm about its short axis, and a depth of about 5 μm, and is composed of about 100 Å of titanium, about 4.5 μm of aluminum, about 0.5 μm of nickel, and 100 nm of gold. . Also, as illustrated for the diode 100K, what was originally a relatively shallow central via is now an ohmic contact with the n+ GaN layer 110 for current conduction between the n+ GaN layer 110 and the second, backside metal layer 122 and a second , is a through via 136 with contact with the backside metal layer 122 . As noted above, for this exemplary diode 100K embodiment, the diode 100K is then flipped or inverted, a second, backside metal layer 122 forms the first terminal 125, and device 300 to energize the diode 100K. , 300A, 300B, 300C, 300D, 720, 730, 760 may be used to make an electrical connection with the second conductor 320.

69 is a cross-sectional view illustrating an exemplary eleventh diode 100L embodiment attached to a support device. 69, the exemplary diode 100L is singulated, any substrates 105, 105A are removed as described above, and also exposes the surface of the n+ GaN layer 110 by an etching step, about 2-6 leaving the composite GaN heterostructures to a depth of microns (or more particularly about 3-5 microns, or more particularly about 4-5 microns, or more particularly about 4.5 microns).

After singulation of the diodes 100 - 100L, they can be used, for example, to form the diode inks discussed below with reference to FIGS. 74 and 75 .

It should also be noted that various surface geometries and/or textures may be fabricated for any of the various diodes 100-100L to help reduce internal reflection and increase light extraction when implemented as an LED. Any of these various surface geometries may have any of the various surface textures discussed above with reference to FIG. 25 . 104 is a perspective view illustrating an exemplary first surface geometry of an exemplary light emitting or light absorbing region, implemented as a plurality of concentric rings or toroidal shapes on the top light emitting (or light absorbing) surface of diode 100K. This geometry is typically etched into the second, backside of the diode 100K either before or after addition of the backside metal 122, via suitable or standard mask and/or photoresist layers and etching known or known in the art. . 105 is a perspective view illustrating an exemplary second surface geometry of an exemplary light emitting or light absorbing region, implemented as a shape of a plurality of substantially curved trapezoids over the top light emitting (or light absorbing) surface of diode 100K. This geometry is typically also known or known in the art, via suitable or standard mask and/or photoresist layers and etching, before or after addition of the backing metal 122, etching into the second, backside of the diode 100K. do.

106 is a perspective view illustrating an exemplary third surface geometry of an exemplary light-emitting or light-absorbing region, implemented as a shape of a plurality of substantially curved trapezoids over the bottom (or bottom) light-emitting (or light-absorbing) surface of diode 100L; to be. 107 is a perspective view illustrating an exemplary fourth surface geometry of an exemplary light emitting or light absorbing region, implemented as a substantially star or radial shape over the bottom (or bottom) light emitting (or light absorbing) surface of diode 100L. 108 is a perspective view illustrating an exemplary fifth surface geometry of an exemplary light-emitting or light-absorbing region, implemented as a plurality of substantially parallel rods or stripes shapes over the bottom (or bottom) light-emitting (or light-absorbing) surface of diode 100L; . Such geometries are also typically known in the art, as part of the substrate removal process and/or the diode singulation process discussed above with reference to FIG. 69, or a suitable or standard mask and/or photoresist known in the art. The layers and etching are etched into the second, backside of the diode 100L.

70, 71, 72 and 73 are flow charts illustrating first, second, third and fourth exemplary method aspects of diodes 100-100L, respectively, and provide a useful overview. It should be noted that many of the steps of these methods may be performed in any various order, and that steps of one exemplary method may be used in other exemplary methods. Thus, each of the above methods will generally be referred to as the manufacture of any diode 100-100L rather than the manufacture of a specific diode 100-100L embodiment, and those skilled in the art will recognize that these steps can be used for any selected diode 100-100L embodiment. It will be appreciated that they can be “mixed and matched” to make them.

Referring to Figure 70, starting from a starting step 240, an oxide layer is grown or deposited over a semiconductor wafer, such as a silicon wafer (step 245). The oxide layer is etched to form, for example, a grating or other pattern (step 250). A buffer layer and a light emitting or light absorbing region (eg, GaN heterostructure) are grown or deposited (step 255) and then etched to form the mesa structure of each diode 100-100L (step 260). The wafer 150 is then etched to form via trenches in the substrate 105 for each diode 100-100L (step 265). One or more metallization layers are then deposited to form metal contacts and vias for each diode 100-100L (step 270). The singulation trenches are then etched between the diodes 100-100L (step 275). A passivation layer is then grown or deposited (step 280). A bump or protruding metal structure may then be deposited or grown over the metal contact (step 285), and the method may end (transport step 290). It should be noted that many of these manufacturing steps may be performed by different members and components, and that the method may include other variations and sequences of the steps discussed above.

71 , starting from a starting step 500, a relatively thick GaN layer (eg, 7-8 μm) is grown or deposited on a wafer, such as a sapphire wafer 150A (step 505). Growing or depositing a light emitting or light absorbing region (e.g., a GaN heterostructure) (step 510) followed by etching (on the first side of each diode 100-100L) to form the mesa structure for each diode 100-100L form (step 515). The wafer 150 is then etched to form one or more through or deep via trenches and singulation trenches in the substrate 105 for each diode 100-100L (step 520). One or more metallization layers are then deposited, typically by depositing a seed layer (step 525), followed by further metal deposition using any of the methods described above, followed by central, perimeter, or outer through vias (respectively). 131, 134, 133), forming through vias for each diode 100-100L. Metal is also deposited to form one or more metal contacts to the GaN heterostructure (e.g., the p+ GaN layer 115 or the n+ GaN layer 110) (step 535) and any additional current-distributing metal (e.g., , 120A, 126 (step 540). A passivation layer is then grown or deposited (step 545) to etch or remove areas as described and illustrated above. A bump or protruding metal structure 120B is then deposited or grown over the metal contact(s) (step 550). The wafer 150A is then attached to a support wafer (step 555) and the sapphire or other wafer is removed (eg, via laser cleaving) to singulate or singulate the diodes 100-100L (step 560). . A metal may then be deposited over the second, backside of the diodes 100-100L to form the second, backside metal layer 122 (step 565), and the method may end (transfer step 570). It should be noted that many of these manufacturing steps may be performed by different members and components, and that the method may include other variations and sequences of the steps discussed above.

Referring to FIG. 72, starting from a starting step 600, a relatively thick GaN layer (eg, 7-8 μm) is grown or deposited on a wafer 150, such as a sapphire wafer 150A (step 605). A light emitting or light absorbing region (eg, GaN heterostructure) is grown or deposited (step 610 ). Metal is deposited to form one or more metal contacts in the GaN heterostructure (eg, the p+ GaN layer 115 as illustrated in FIG. 45 ) (step 615 ). The light emitting or light absorbing region (e.g., the GaN heterostructure) having the metal contact layer 119 is then etched (on the first side of each diode 100-100L) for each diode 100-100L. A mesa structure is formed (step 620). Metal is deposited to form one or more metal contacts in the GaN heterostructure (eg, the n+ metal contact layer 129 and the n+ GaN layer 110 as illustrated in FIG. 47 ) (step 625 ). The wafer 150A is then etched to form one or more through or deep via trenches and/or singulation trenches in the substrate 105 for each diode 100-100L (step 630). One or more metallization layers are then deposited using any of the metal deposition methods described above for each diode 100-100L, which may be a central, peripheral or outer through via (131, 134, 133, respectively). A through via is formed (step 635). A metal may also be deposited to form one or more metal contacts in the GaN heterostructure (eg, the p+ GaN layer 115 or the n+ GaN layer 110 ) and any additional current-distributing metal (eg, 120A, 126 ) ) is formed (step 640). If the singulation trench is not previously fabricated (step 630), the singulation trench is etched (step 645). A passivation layer is then grown or deposited (step 645) to etch or remove areas as described and illustrated above. A bump or protruding metal structure 120B is then deposited or grown over the metal contact(s) (step 655). The wafers 150, 150A are then attached to a support wafer (step 660), and the sapphire or other wafer is removed (eg, via laser cleaving or backside grinding and polishing) to singulate the diodes 100-100L. make or individualize (step 665). A metal may then be deposited over a second, backside of the diodes 100-100L to form the second, backside conductive (eg, metal) layer 122 (step 670), terminating the method (step 670). return step 675). It should also be noted that many of these manufacturing steps may be performed by different members and components, and that the method may include other variations and sequences of the steps discussed above.

73, starting from a starting step 611, grow or deposit a relatively thick GaN layer (e.g., 7-8 μm) on a wafer 150, such as a sapphire wafer 150A, or on a buffer layer 145 of a silicon wafer 150 (e.g., 7-8 μm). step 611). A light emitting or light absorbing region (eg, GaN heterostructure) is grown or deposited (step 616 ). Metal is deposited to form one or more metal bonds to the GaN heterostructure (eg, the p+ GaN layer 115 as illustrated in FIG. 45 ) (step 621 ). The light emitting or light absorbing region (eg, the GaN heterostructure) with the metal contact layer 119 is then etched (on the first side of each diode 100-100L) to the mesa for each diode 100-100L. A structure is formed (step 626). Then, for the diode 100K embodiment, the GaN heterostructure is etched to form a central via trench for each diode 100K (step 631 ), otherwise step 631 may be omitted. One or more metallization layers are then deposited using any of the metal deposition methods described above to form central via 136 for each diode 100K or metal contact 128 for diode 100L (step 636). For the diode 100K embodiment, a passivation layer 135A may then be grown or deposited (step 641) to etch or remove areas as described and illustrated above, otherwise step 641 may be omitted. Metal is also deposited to form one or more metal contacts, such as metal layer 120B or metal layers 120A and 120B, to the GaN heterostructure (eg, the p+ GaN layer 115) (step 646). If the singulation trench has not been previously fabricated, the singulation trench is etched (step 651). A passivation layer is then grown or deposited (step 656) to etch or remove areas as described and illustrated above. It should be noted that steps 656 and 651 are performed in the reverse order for diode 100L fabrication, performing passivation followed by etching the singulation trench. The wafers 150, 150A are then attached to a support wafer (step 661), and the silicon, sapphire or other wafer is removed (e.g., via laser cleaving or backside grinding and polishing) to form the diodes 100-100L. Singulate or singulate (step 666) and remove any additional GaN, for example via etching. Then, for the diode 100K embodiment, metal is deposited over the second, backside of the diode 100K to form a second, backside conductive (eg, metal) layer 122 (step 671), terminating the method. (return step 676). It should also be noted that many of these manufacturing steps may be performed by different members and components, and that the method may include other variations and sequences of the steps discussed above. For example, steps 611 and 612 may be performed by a specific vendor.

74 shows that diode wafers 150, 150A are no longer coupled together (the second side of diode wafers 150, 150A is grounded or polished, cleaved (laser lift-off) and/or etched to singulation (individualization)) individual diodes 100-100L (also generally optional for illustrative purposes), attached to the support device 160 by means of a wafer adhesive 165 and suspended or impregnated in a dish 175 with a wafer adhesive solvent 170 (illustrated without important detailed features of ) is a cross-sectional view. As an exemplary method of using a polytetrafluoroethylene (PTFE or Teflon) dish 175, any suitable dish 175 may be used, such as a Petri dish. The wafer adhesion solvent 170 may be any including, but not limited to, for example, 2-dodecene wafer bond remover available from Brewer Science, Inc. of Lola, Mo. commercially available wafer adhesion solvents or wafer bond removers, or any other relatively long chain alkane or alkene or short chain heptane or heptene. Diodes 100-100L attached to support device 160 may be immersed in wafer adhesion solvent 170, typically at room temperature (eg, about 65°F to 75°F) or higher, for about 5 to about 15 minutes, see also can be sonicated in other aspects. As the wafer adhesion solvent 170 dissolves the adhesive 165, the diodes 100-100L separate from the adhesive 165 and the support device 160, and most or generally sink to the bottom of the dish 175 either individually or in groups or clusters. When all or most of the diodes 100-100L have been released from the support device 160 and deposited on the bottom of the dish 175, a portion of the support device 160 and the currently used wafer adhesion solvent 170 is removed from the dish 175. Then, additional wafer adhesion solvent 170 is added (about 120-140 ml), and the mixture of wafer adhesion solvent 170 and 100-100 L of diode is typically for about 5-15 minutes at room temperature or higher (e.g., After shaking (using a sonicator or impeller mixer), 100-100L of the diodes are again deposited on the bottom of dish 175. This process is then typically repeated at least one or more times to remove some of the currently used wafer adhesion solvent 170 from the dish 175 when all or most of the diodes 100 to 100 L have settled to the bottom of the dish 175, followed by adding (about 120 to 140 ml) of wafer adhesion solvent 170 is added, then the mixture of wafer adhesion solvent 170 and diode 100 to 100 L is shaken at room temperature or higher for about 5 to 15 minutes, and then the diode 100 to 100 L is stirred Re-deposit on the bottom of the dish 175, and a part of the remaining wafer adhesion solvent 170 is removed. At this stage, generally a sufficient amount of any residual wafer adhesive 165 is removed from the diodes 100-100L, or the wafer adhesion solvent 170 process is repeated so as to no longer potentially interfere with the printing or functionalization of the diodes 100-100L.

Removal of the wafer adhesion solvent 170 (with the wafer adhesive 165 dissolved), or any of the other solvents, solutions or other liquids discussed below, may be accomplished in any of a variety of ways. For example, the wafer adhesion solvent 170 or other liquids may be removed by vacuum, aspiration, aspiration, pumping, etc., for example via a pipette. Also, for example, wafer adhesion solvent 170 or other liquids can be mixed with a mixture of diode 100-100L and wafer adhesion solvent 170 (or other liquids) using, for example, a screen or porous silicon membrane with appropriate opening or pore sizes. It can be removed by filtration. It should also be mentioned that the various fluids used in this diode ink (and dielectric inks discussed below) are all filtered to remove particles larger than about 10 microns.

Diode Ink Example 1:

a plurality of diodes 100 to 100L; and

menstruum

A composition comprising a.

Substantially all or most of the wafer adhesion solvent 170 is removed. In an exemplary embodiment, for example, a solvent, more particularly a polar solvent such as isopropyl alcohol (“IPA”), is added to a mixture of wafer adhesion solvent 170 and diodes 100-100L, followed by IPA, wafer adhesion solvent 170 and diodes. 100-100 L of the mixture is shaken for about 5-15 minutes, typically at room temperature (higher temperatures can equally be used), then 100-100 L of the diode is re-settled to the bottom of dish 175, and wafer adhesion with IPA A portion of the mixture of solvent 170 is removed. Additional IPA is added (120-140 mL) and the process is repeated two more times, i.e., a mixture of IPA, wafer adhesion solvent 170 and 100-100 L of diodes is shaken for about 5-15 minutes, usually at room temperature. Next, 100-100L of the above diodes are again deposited on the bottom of dish 175, a portion of the mixture of IPA and wafer adhesion solvent 170 is removed, and additional IPA is added. In an exemplary embodiment, the mixture obtained is about 100 to 110 ml of IPA having approximately 9 million to 10 million diodes 100 to 100 L (approximately 9.7 million diodes 100 to 100 L per 150 4 inch wafer) from a 4 inch wafer, which It is then transferred to another larger container, such as a PTFE bottle, which may include further cleaning of the diodes in the bottle, for example with additional IPA. one or more solvents such as, but not limited to, water; alcohols such as methanol, ethanol, N-propanol (“NPA”) (including 1-propanol, 2-propanol (IPA), 1-methoxy-2-propanol), butanol (1-butanol, 2- butanol (including isobutanol), pentanol (including 1-pentanol, 2-pentanol, 3-pentanol), octanol, N-octanol (1-octanol, 2-octanol, 3- octanol), tetrahydrofurfuryl alcohol (THFA), cyclohexanol, terpineol; ethers such as methyl ethyl ether, diethyl ether, ethyl propyl ether, and polyethers; esters such as ethyl acetate, dimethyl adipate, propylene glycol monomethyl ether acetate, dimethyl glutarate, dimethyl succinate, glycerin acetate; glycols such as ethylene glycol, diethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol, glycol ethers, glycol ether acetates; carbonates such as propylene carbonate; glycerol such as glycerin; acetonitrile, tetrahydrofuran (THF), dimethyl formamide (DMF), N-methyl formamide (NMF), dimethyl sulfoxide (DMSO); and mixtures thereof may equally be used. The resulting mixture of diodes 100-100L and a solvent (eg IPA) is a first example of a diode ink as Example 1 above, and can be provided as a stand-alone composition, for example for subsequent modification or use in printing. have. In other exemplary embodiments discussed below, the resulting mixture of diodes 100-100L and a solvent (eg, IPA) is an intermediate mixture that is further modified to form a diode ink for printing, as described below.

In various exemplary embodiments, the selection of the first (or second) solvent is based on at least two characteristics or properties. The first property of the solvent is its ability to dissolve or solubilize in a viscosity modifier or adhesive viscosity modifier such as hydroxy propyl methylcellulose resin, methoxy propyl methylcellulose resin, or other cellulosic resins or methylcellulose resins. A second characteristic or characteristic is its rate of evaporation, which must be slow enough to allow sufficient screen retention (for screen printing) of the diode ink or to satisfy other printing parameters. In various exemplary embodiments, exemplary evaporation rates are less than 1 (<1, relative rate compared to butyl acetate), or more specifically between 0.0001 and 0.9999.

Diode Ink Example 2:

a plurality of diodes 100 to 100L; and

viscosity modifier

A composition comprising a.

Diode Ink Example 3:

a plurality of diodes 100 to 100L; and

solvating agent

A composition comprising a.

Diode Ink Example 4:

a plurality of diodes 100 to 100L; and

wetting solvent

A composition comprising a.

Diode Ink Example 5:

a plurality of diodes 100 to 100L;

menstruum; and

viscosity modifier

A composition comprising a.

Diode Ink Example 6:

a plurality of diodes 100 to 100L;

menstruum; and

adhesive viscosity modifier

A composition comprising a.

Diode Ink Example 7:

a plurality of diodes 100 to 100L;

menstruum; and

viscosity modifier

A composition comprising a.

Here, the composition is opaque when wet and almost optically transmissive or transparent when dry.

Diode Ink Example 8:

a plurality of diodes 100 to 100L;

a first polar solvent;

viscosity modifiers; and

a second non-polar solvent (or rewetting agent)

A composition comprising a.

Diode Ink Example 9:

a plurality of diodes 100 to 100L, wherein each diode of the plurality of diodes 100 to 100L has a size of less than 450 μm in any dimension; and

menstruum

A composition comprising a.

Diode Ink Example 10:

a plurality of diodes 100 to 100L; and

at least one substantially non-insulating carrier or solvent

A composition comprising a.

Diode Ink Example 11:

a plurality of diodes 100 to 100L;

menstruum; and

viscosity modifier

A composition comprising a.

wherein the composition has a dewetting or contact angle greater than 25 degrees or greater than 40 degrees.

Referring to Diode Ink Examples 1-11, a wide variety of exemplary diode ink compositions exist within the scope of the present invention. In general, as in Example 1, the liquid suspension of diodes 100-100L is prepared by mixing the plurality of diodes 100-100L and a first solvent (eg, IPA or N-propanol, 1-M as discussed above). toxy-2-propanol, dipropylene glycol, 1-octanol (or more generally, N-octanol), or diethylene glycol as discussed above); As in Example 2, the liquid suspension of diodes 100-100L is a plurality of diodes 100-100L and a viscosity modifier (discussed below, which may be an adhesive viscosity modifier as in Example 6). ); As in Examples 3 and 4, the liquid suspension of diodes 100-100L is formed of a plurality of diodes 100-100L and a solvating or wetting solvent (eg, one of the second solvents discussed below). , for example, a dibasic ester). More particularly, as in embodiments 2, 5, 6, 7 and 8, the liquid suspension of diodes 100 to 100L is composed of a plurality of diodes 100 to 100L (and/or a plurality of diodes 100 to 100L). and a first solvent (eg, N-propanol, 1-octanol, 1-methoxy-2-propanol, dipropylene glycol, terpineol, or diethylene glycol)), and at room temperature (about 25° C.) about a viscosity modifier (or equivalently, a viscous agent) to provide a diode ink having a viscosity of 1,000 centipoise (cps) to 25,000 cps (or about 20,000 cps to 60,000 cps at refrigeration temperature (eg, 5 to 10°C)) compounds, viscous reagents, viscous polymers, viscous resins, viscous binders, thickeners, and/or rheology modifiers) or adhesive viscosity modifiers (discussed in more detail below) such as, but not limited to, the E-10 viscosity described below including modulators. Depending on the above viscosities, the resulting composition may be referred to as equivalent to a liquid or gel suspension of a diode or other two-terminal integrated circuit, and any reference to a liquid or gel herein means and includes others. will be understood

Additionally, the final viscosity of the diode ink will generally depend on the type of printing process used, and may also depend on the diode composition, such as a silicon substrate 105 or a GaN substrate 105. For example, a diode ink for screen printing, wherein the diodes 100-100L has a silicon substrate 105, is about 1,000 centipoise (cps) to 25,000 cps at room temperature, or more specifically about 6,000 centipoise (cps) to 15,000 cps at room temperature; or more specifically about 6,000 centipoise (cps) to 15,000 cps at room temperature, or more specifically about 8,000 centipoise (cps) to 12,000 cps at room temperature, or more specifically about 9,000 centipoise (cps) at room temperature. It may have a viscosity of to 11,000 cps. In another example, a diode ink for screen printing wherein the diodes 100-100L has a GaN substrate 105 is between about 10,000 centipoise (cps) and 25,000 cps at room temperature, or more specifically between about 15,000 centipoise (cps) and 22,000 cps at room temperature. , or more specifically about 17,500 centipoise (cps) to 20,500 cps at room temperature, or more specifically about 18,000 centipoise (cps) to 20,000 cps at room temperature. Also, for example, a diode ink for flexographic printing in which the diodes 100 to 100L has a silicon substrate 105 may be about 1,000 centipoise (cps) to 10,000 cps at room temperature, or more specifically about 1,500 centipoise (cps) at room temperature. to 4,000 cps, or more specifically from about 1,700 centipoise (cps) to 3,000 cps at room temperature, or more specifically from about 1,800 centipoise (cps) to 2,200 cps at room temperature. Also, for example, diode inks for flexographic printing in which diodes 100 to 100L have a GaN substrate 105 may be about 1,000 centipoise (cps) to 10,000 cps at room temperature, or more specifically about 2,000 centipoise (cps) at room temperature. to 6,000 cps, or more specifically from about 2,500 centipoise (cps) to 4,500 cps at room temperature, or more specifically from about 2,000 centipoise (cps) to 4,000 cps at room temperature.

Viscosity can be measured in a wide variety of ways. For comparative purposes, the various ranges of viscosities specified and/or claimed herein were measured using a Brookfield viscometer (available from Brookfield Engineering Laboratories, Middleboro, MA) using a Brookfield viscometer. , using spindle SC4-27 at a speed of about 10 rpm (or particularly, for example, but not limited to, more typically 1 to 30 rpm for refrigerated fluids), in a water jacket at about 25° C., in a water jacket of about 200 Pascals (or more commonly 190 to 210 Pascals).

(as viscosity modifier) one or more thickening agents such as, but not limited to, clays such as hectorite clay, garamite clay, organo-modified clay; saccharides and polysaccharides such as guar gum, xanthan gum; Cellulose and modified celluloses such as hydroxy methylcellulose, methylcellulose, ethyl cellulose, propyl methylcellulose, methoxy cellulose, methoxy methylcellulose, methoxy propyl methylcellulose, hydroxy propyl methylcellulose, carboxymethylcellulose, hydroxy ethylcellulose, ethyl hydroxyl ethylcellulose, cellulose ether, cellulose ethyl ether, chitosan; polymers such as acrylate and (meth)acrylate polymers and copolymers; glycols such as ethylene glycol, diethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol, glycol ethers, glycol ether acetates; fumed silica (eg Cabosil), silica powder and modified urea, such as BYK® 420 (available from BYK Chemie GmbH); and mixtures thereof may be used. Other viscosity modifiers, as described in US Patent Application Publication 2003/0091647 (Lewis et al.), as well as particle additives for viscosity control may be used. polyvinyl pyrrolidone, polyethylene glycol, polyvinyl acetate (PVA), polyvinyl alcohol, polyacrylic acid, polyethylene oxide, polyvinyl butyral (PVB); Other viscosity modifiers discussed below with reference to dielectric inks may also be used, including, but not limited to, diethylene glycol, propylene glycol, 2-ethyl oxazoline.

Referring to Diode Ink Example 6, the liquid suspension of diodes 100 to 100L may further comprise an adhesive viscosity modifier, ie, any of the above-mentioned viscosity modifiers having additional adhesive properties. Such adhesive viscosity modifiers may be used in the device 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 during manufacture (eg, printing) of the first conductor (eg, printing). 310A) or to substrates 305, 305A both provide adhesion of the diodes 100 to 100L, followed by devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740. , 750 , 760 , and 770 ) further provide an infrastructure (eg, polymerizable) (drying or curing) for holding the diodes 100 - 100L in place. While providing such adhesion, such viscosity modifiers should also have some ability to dewet from contacts of diodes 100 - 100L, for example terminals 125 and/or 127. This adhesion, tack, and dewetting properties are the reasons methylcellulose, methoxy propyl methylcellulose, or hydroxy propyl methylcellulose resins are used in various exemplary embodiments, among other things. Other suitable viscosity modifiers can also be selected empirically.

Additional properties of the above viscosity modifiers or adhesive viscosity modifiers are also useful and are within the scope of the present disclosure. First, this viscosity modifier should prevent the suspended diodes 100-100L from settling at the selected temperature. Second, these viscosity modifiers make the diodes 100 to 100L uniform during the manufacture of the devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770. Orient and help print the diodes 100-100L. Third, in some embodiments, the viscosity modifier should also act to buffer or protect the diodes 100-100L during the printing process, and in other embodiments, the glass that acts to protect the diodes 100-100L during the printing process. Add inert particles such as beads (diode ink examples 17-19, discussed below).

With reference to diode ink examples 3, 4 and 8, the liquid suspension of diodes (100-100L) is added with a second solvent (Example 8) or a solvating agent (Example 3) or a wetting solvent (Example 4) , a number of embodiments are discussed in more detail below. This (first or second) solvent is applied to the first (through the substrate 105 , the through via structures 131 , 133 , 134 , and/or the second, backside metal layer 122 , as illustrated in FIG. 83 ). ohmic contact between a conductor (eg, 310A, which may be composed of a conductive polymer such as silver ink, carbon ink, or a mixture of silver ink and carbon ink) and the diode 100 to 100L, and the diode in subsequent device fabrication. to facilitate printing and drying of the ink, wetting agents (equivalently solvating agents) or rewetting agents, for example, non-polar resin solvents including, but not limited to, one or more dibasic esters. For example, when the diode ink is printed over the first conductor 310, the wetting or solvating agent partially dissolves the first conductor 310; When the wetting or solvating agent is subsequently dissipated, the first conductor 310 strengthens again and forms contact with the diodes 100 - 100L.

The remainder of the liquid or gel suspension of diodes 100-100L is usually another third solvent, for example deionized water, and all ratios described herein are those of the liquid or gel suspension of diodes 100-100L. It is assumed that the residue is this third solvent (eg water), and all proportions stated are by weight and not by volume or some other measure. It should also be noted that the various diode ink suspensions can all be mixed in conventional atmospheric configurations without requiring air of any particular composition or other contained or filtered environment.

Solvent selection may also be based on the polarity of the solvent. In exemplary embodiments, diodes 100-100L and other conductors (eg, 310) during device 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 fabrication. ) to facilitate the dewetting of and at the same time be dissolved or solubilized in the viscosity modifier, a first solvent, such as an alcohol, may be selected as a polar or hydrophilic solvent.

Another useful property of an exemplary diode ink is illustrated by Example 7. For this exemplary embodiment, the diode ink may be opaque when wetted during the printing process to aid in various printing processes such as registration. However, when dried or cured, the dried or cured diode ink may be substantially optically transmissive at a selected wavelength or Transparent. However, in other exemplary aspects, the diode ink may also be substantially optically transmissive or transparent.

Another method of identifying an exemplary diode ink is based on the size of the diodes 100-100L, as illustrated in Example 9, wherein the diodes 100-100L generally have a dimension of less than about 450 μm, more specifically Any dimension is less than about 200 μm, more specifically any dimension is less than about 100 μm, more specifically any dimension is less than 50 μm, and more specifically any dimension is less than 30 μm. In the exemplary embodiments shown, the diodes 100-100L are generally about 10-50 microns wide, or more specifically about 20-30 microns wide, and about 5-25 microns high, or have a diameter (vertex to not vertex). Measured face to face) about 25 to 28 μm and 8 to 15 μm in height or 9 to 12 μm in height. In some exemplary embodiments, the height of the diode 100-100L (ie, the height of the side 121 comprising the GaN heterostructure) excluding the metal layer 120B forming the bump or protrusion structure is about 5-15 μm, or more specifically is less than 7 to 12 μm, or more specifically 8 to 11 μm, or more specifically 9 to 10 μm, or more specifically 10 to 30 μm, and the height of the metal layer 120B forming the bump or protrusion structure is It is generally about 3 to 7 μm.

In other exemplary embodiments, the height of the diode (eg, 100L) excluding the back metal 122 and the metal layer 120B forming the bump or protrusion structure (ie, the height of the side 121 comprising the GaN heterostructure) is about 10 less than microns, or more specifically less than about 8 microns, or more specifically about 2-6 microns, or more specifically about 3-5 microns, or more specifically about 4.5 microns; The height of the forming metal layer 120B is generally about 3 to 7 μm, or more specifically about 5 to 7 μm, and the overall height of the diode 100L is less than about 15 μm, or more specifically less than about 12 μm, or more specifically is about 9 to 11 μm, or more specifically about 10 to 11 μm, or more specifically about 10.5 μm.

In other exemplary embodiments, the height of the diode (eg, 100K) excluding the back metal 122 and the metal layer 120B forming the bump or protrusion structure (ie, the height of the side 121 comprising the GaN heterostructure) is about 10 less than microns, or more specifically less than about 8 microns, or more specifically about 2-6 microns, or more specifically about 2-4 microns, or more specifically about 3.0 microns; The height of the forming metal layer 120B and the backing metal 122 is generally about 3 to 7 μm, or more specifically about 4 to 6 μm, or more specifically about 5 μm, and the overall height of the diode 100K is less than about 15 μm; or more specifically less than about 14 μm, or more specifically about 12-14 μm, or more specifically about 13 μm. In other exemplary embodiments, the height of the diode 100K that does not include the height of the backing metal 122 that forms the bump or protrusion but that does include the metal layer 120B is between about 5 and 10 μm.

This diode ink can also be identified by its electrical properties as exemplified in Example 10. In this exemplary embodiment, diodes 100 - 100L are suspended in at least one substantially non-insulating carrier or solvent as opposed to, for example, an insulating binder.

This diode ink can also be identified by its surface properties as exemplified in Example 11. In this exemplary aspect, the diode ink has a dewetting or contact angle of greater than 25 degrees or greater than 40 degrees, depending on the surface energy of the substrate used for the measurement (eg, 34 to 42 dynes).

Diode Ink Example 12:

a plurality of diodes 100 to 100L;

a first solvent comprising about 5% to 50% of N-propanol, terpineol or diethylene glycol, ethanol, tetrahydrofurfuryl alcohol, and/or cyclohexanol, or mixtures thereof;

a viscosity modifier comprising about 0.75% to 5.0% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof;

a second solvent (or rewetting agent) comprising about 0.5% to 10% of a non-polar resin solvent such as a dibasic ester; and

remainder including a third solvent such as water

A composition comprising a.

Diode Ink Example 13:

a plurality of diodes 100 to 100L;

a first solvent comprising from about 15% to 40% of N-propanol, terpineol or diethylene glycol, ethanol, tetrahydrofurfuryl alcohol, and/or cyclohexanol, or mixtures thereof;

a viscosity modifier comprising about 1.25% to 2.5% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof;

a second solvent (or rewetting agent) comprising about 0.5% to 10% of a non-polar resin solvent such as a dibasic ester; and

remainder including a third solvent such as water

A composition comprising a.

Diode Ink Example 14:

a plurality of diodes 100 to 100L;

a first solvent comprising about 17.5% to 22.5% of N-propanol, terpineol or diethylene glycol, ethanol, tetrahydrofurfuryl alcohol, and/or cyclohexanol or mixtures thereof;

a viscosity modifier comprising about 1.5% to 2.25% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof;

a second solvent (or rewetting agent) comprising about 0.0% to 6.0% of at least one dibasic ester; and

remainder including a third solvent such as water

A composition comprising: wherein the composition has a viscosity of from about 5,000 cps to about 20,000 cps at substantially 25°C.

Diode Ink Example 15:

a plurality of diodes 100 to 100L;

a first solvent comprising about 20% to 40% of N-propanol, terpineol or diethylene glycol, ethanol, tetrahydrofurfuryl alcohol, and/or cyclohexanol, or mixtures thereof;

a viscosity modifier comprising about 1.25% to 1.75% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof;

a second solvent (or rewetting agent) comprising from about 0% to 6.0% of at least one dibasic ester; and

remainder including a third solvent such as water

A composition comprising: wherein the viscosity of the composition is from about 1,000 cps to about 5,000 cps at substantially 25°C.

Diode Ink Example 16:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

menstruum; and

viscosity modifier

A composition comprising a.

Diode Ink Example 17:

a plurality of diodes 100 to 100L;

menstruum;

viscosity modifiers; and

at least one mechanical stabilizer or spacer

A composition comprising a.

Diode Ink Example 18:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

menstruum;

viscosity modifiers; and

a plurality of inert particles having a size range of about 10 to 50 μm

A composition comprising a.

Diode Ink Example 19:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 20-30 μm and a height of about 9-15 μm;

menstruum;

viscosity modifiers; and

A plurality of substantially optically transparent and chemically inert particles having a size range of about 15 to about 25 μm.

A composition comprising a.

Diode Ink Example 20:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

a first solvent comprising an alcohol;

a second solvent comprising glycol;

a viscosity modifier comprising about 0.10% to 2.5% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof; and

A plurality of substantially optically transparent and chemically inert particles having a size range of about 10 to about 50 μm.

A composition comprising a.

Diode Ink Example 21:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

a mixture of at least a first solvent and a second solvent different from the first solvent (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol; comprising about 15% to 99.99% of at least two solvents selected from the group consisting of tetrahydrofurfuryl alcohol, cyclohexanol, and mixtures thereof); and

A viscosity modifier comprising about 0.10% to 2.5% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof.

A composition comprising a.

Diode Ink Example 22:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

a mixture of at least a first solvent and a second solvent different from the first solvent (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol; comprising about 15% to 99.99% of at least two solvents selected from the group consisting of tetrahydrofurfuryl alcohol, cyclohexanol, and mixtures thereof);

a viscosity modifier comprising about 0.10% to 2.5% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof;

About 0.01% to 2.5% of a plurality of substantially optically transparent and chemically inert particles having a size range of about 10 to about 50 μm

A composition comprising a.

Diode Ink Example 23:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

a mixture of at least a first solvent and a second solvent different from the first solvent (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol; comprising about 15% to 50.0% of at least two solvents selected from the group consisting of tetrahydrofurfuryl alcohol, cyclohexanol, and mixtures thereof);

a viscosity modifier comprising about 1.0% to 2.5% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof;

from about 0.01% to 2.5% of a plurality of substantially optically transparent and chemically inert particles having a size range of from about 10 to about 50 μm; and

remainder including a third solvent such as water

A composition comprising a.

Diode Ink Example 24:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

from the group consisting of N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclohexanol and mixtures thereof. a first solvent comprising about 15% to 40% of a solvent of choice;

A second solvent different from the first solvent (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclo about 2% to 10% of a solvent selected from the group consisting of hexanol and mixtures thereof);

A third solvent different from the first and second solvents (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl) containing about 0.01% to 2.5% of a solvent selected from the group consisting of alcohol, cyclohexanol and mixtures thereof);

a viscosity modifier comprising about 1.0% to 2.5% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof; and

remainder including a third solvent such as water

A composition comprising a.

Diode Ink Example 25:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

from the group consisting of N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclohexanol and mixtures thereof. a first solvent comprising about 15% to 30% of a solvent of choice;

A second solvent different from the first solvent (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclo about 3% to 8% of a solvent selected from the group consisting of hexanol and mixtures thereof);

A third solvent different from the first and second solvents (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl) containing about 0.01% to 2.5% of a solvent selected from the group consisting of alcohol, cyclohexanol and mixtures thereof);

a viscosity modifier comprising about 1.25% to 2.5% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof;

from about 0.01% to 2.5% of a plurality of substantially optically transparent and chemically inert particles having a size range of from about 10 to about 50 μm; and

Residual amount of third solvent such as water

A composition comprising a.

Diode Ink Example 26:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

from the group consisting of N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclohexanol and mixtures thereof. a first solvent comprising about 40% to 60% of a solvent of choice;

A second solvent different from the first solvent (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclo comprising about 40% to 60% of a solvent selected from the group consisting of hexanol and mixtures thereof); and

A viscosity modifier comprising about 0.10% to 1.25% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof.

A composition comprising a.

Diode Ink Example 27:

a plurality of diodes 100-100L having a diameter (width and/or length) of about 10-50 μm and a height of 5-25 μm;

from the group consisting of N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclohexanol and mixtures thereof. a first solvent comprising about 40% to 60% of a solvent of choice;

A second solvent different from the first solvent (N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, 1-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclo comprising about 40% to 60% of a solvent selected from the group consisting of hexanol and mixtures thereof);

a viscosity modifier comprising about 0.10% to 1.25% of a methoxy propyl methylcellulose resin, or a hydroxy propyl methylcellulose resin, or other cellulose or methylcellulose resin, or mixtures thereof; and

About 0.01% to 2.5% of a plurality of substantially optically transparent and chemically inert particles having a size range of about 10-50 μm

A composition comprising a.

With reference to diode ink Examples 12-27, in an exemplary embodiment, as the first solvent another alcohol, N-propanol (“NPA”) (and/or N-octanol (eg, 1-octanol ( or any of a variety of secondary or tertiary octanol isomers), 1-methoxy-2-propanol, terpineol, diethylene glycol, dipropylene glycol, tetrahydrofurfuryl alcohol, or cyclohexanol) Replace all or most of the above IPA.In the case of diode 100-100L deposited on the bottom of the vessel generally or mostly, remove the IPA, add NPA and shake the mixture of IPA, NPA and diode 100-100L at room temperature After mixing or mixing, the diode 100-100 L is re-settled to the bottom of the vessel, a portion of the mixture of IPA and NPA is removed, and additional NPA (about 120-140 ml) is added.This NPA addition and IPA and NPA The mixture removal process of the mixture is generally repeated twice, mainly of NPA, diodes 100 to 100L, traces or otherwise small amounts of IPA, and also generally traces or otherwise small amounts of potentially residual wafer adhesive and wafer adhesion solvent 170. The mixture is produced.In an exemplary embodiment, the remaining residual or trace IPA is less than about 1%, more generally about 0.4%.Also, in an exemplary embodiment, the final proportion of NPA in the exemplary diode ink is: If present, depending on the type of printing to be used, from about 0.5% to 50%, or more specifically from about 1.0% to 10%, or more specifically from about 3% to 7%, or in other aspects, more specifically from about 15% to 40%, or more specifically from about 17.5% to 22.5%, or more specifically from about 25% to about 35% Terpineol and/or diethylene glycol in combination with or as a substitute for NPA When used as , the typical concentration of terpineol is about 0.5% to 2.0%, diethylene glycol A typical concentration of chol is about 15% to 25%. The IPA, NPA, re-wetting agent, deionized water (and other compounds and mixtures used to form the exemplary diode ink) can be applied down to about 25 μm or less to remove particle contaminants that are larger than or equal to the size of the diodes 100-100L. It may be filtered.

Substantially a mixture of NPA or other first solvent and 100 to 100 L of diodes is added and a viscosity modifier such as methoxy propyl methylcellulose resin, hydroxy propyl methylcellulose resin, or other cellulosic or methylcellulose resin and Simply mix or stir. In an exemplary embodiment, E available from The Dow Chemical Company (www.dow.com) and Hercules Chemical Company, Inc. (www.herchem.com) about 0.10% to 5.0%, or more specifically about 0.2% to 1.25%, or more specifically about 0.3% to 0.7%, or more specifically about 0.4% to 0.6%, or more specifically about 1.25% to 2.5%, or more specifically 1.5% to 2.0%, or more specifically 2.0% or less. In an exemplary embodiment, about 3.0% E-10 formulation is used and it is diluted with deionized, filtered water to produce the above final proportions in the finished composition. Other viscosity modifiers, including those discussed above and those discussed below with respect to dielectric inks, can equally be used. As the viscosity modifiers provide sufficient viscosity for the diodes 100-100L, they remain substantially dispersed in the suspension and do not precipitate out of the liquid or gel suspension, particularly under refrigeration.

Then, as mentioned above, a second solvent (or first solvent in the case of Examples 3 and 4), typically a non-polar resin solvent such as one or more dibasic esters, may be added. In an exemplary embodiment, a mixture of the two dibasic esters is added in an amount from about 0.0% to about 10%, or more specifically from about 0.5% to about 6.0%, or more specifically from about 1.0% to about 5.0%, or more specifically from about 2.0% to about 4.0%, or more specifically from about 2.5% to about 3.5%, such as dimethyl glutarate, or about 2/3 of dimethyl glutarate. and about one third of dimethyl succinate in a final ratio of about 3.73% (eg, DBE-5 or DBE available from Invista USA, Wilmington, Del., respectively). -9, they also have trace or otherwise minor impurities such as about 0.2% dimethyl adipate and 0.04% water). Where necessary or desired, a third solvent, such as deionized water, is used to control the relative proportions and reduce the viscosity. In addition to the dibasic esters, other second solvents that may equally be used include, but are not limited to, water; Alcohols such as methanol, ethanol, N-propanol (including 1-propanol, 2-propanol (isopropanol), 1-methoxy-2-propanol), isobutanol, butanol (1-butanol, 2-butanol) ), pentanol (including 1-pentanol, 2-pentanol, 3-pentanol), N-octanol (including 1-octanol, 2-octanol, 3-octanol), tetrahydrofur furyl alcohol, cyclohexanol; ethers such as methyl ethyl ether, diethyl ether, ethyl propyl ether, and polyethers; ethers such as ethyl acetate, dimethyl adipate, propylene glycol monomethyl ether acetate (and dimethyl glutarate and dimethyl succinate as mentioned above); glycols such as ethylene glycol, diethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol, glycol ethers, glycol ether acetates; carbonates such as propylene carbonate; glycerol such as glycerin; acetonitrile, tetrahydrofuran (THF), dimethyl formamide (DMF), N-methyl formamide (NMF), dimethyl sulfoxide (DMSO); and mixtures thereof. In an exemplary embodiment, the molar ratio of the amount of the first solvent to the amount of the second solvent is in the range of at least about 2 to 1, more specifically in the range of at least about 5 to 1, more specifically in the range of at least about 12 to 1 or thereof. more than; In other cases, the functionalities of the two solvents may be combined as a single component with one polar or non-polar solvent used in an exemplary embodiment. Also, in addition to the dibasic esters discussed above, exemplary solvating, wetting or solubilizing agents include, for example, but not limited to, with 1-propanol (or isopropanol) to form a suspending medium, as also noted below. propylene glycol monomethyl ether acetate (C ₆ H ₁₂ O ₃ ) (sold by Eastman under the trade name “PM Acetate”), used in an approximate 1:8 molar ratio (or 22:78 by weight), and Various dibasic esters, and mixtures thereof, such as dimethyl succinate, dimethyl adipate and dimethyl glutarate (these are from Invista under the trade names DBE, DBE-2, DBE-3, DBE-4, DBE-5, available as various mixtures under DBE-6, DBE-9 and DBE-IB). In an exemplary embodiment, DBE-9 is being used. The molar ratio of solvents will vary based on the solvents selected, with 1:8 and 1:12 being typical ratios.

With reference to diode ink examples 17 to 20, 22, 25 and 27, one or more mechanical stabilizers or spacers, for example chemically inert particles and/or optically transparent particles, for example usually silicate or borosilicate Glass beads consisting of are included, but are not limited to. In various exemplary embodiments, from about 0.01% to 2.5% of glass spheres or beads having an average size or size range of from about 10 to 30 μm, or more particularly from about 12 to 28 μm, or more particularly from about 15 to 25 μm, or more particularly from about 0.05% to 1.0%, or more particularly from about 0.1% to 0.3% by weight. These particles are formed because the diodes 100-100L are initially held in place only through a relatively thin film of dry or cured diode ink (FIGS. It provides mechanical stability and/or space during the printing process by acting as In general, the concentration of inert particles is sufficiently low such that the number of inert particles per unit area (after deposition, of the device area in question) is less than the density of the diodes 100 to 100 L per unit area. The inert particles provide mechanical stability and space, so that when a conductive layer 310 and/or a dielectric layer 315 is deposited, the diodes 100-100L may dislodge or Because they tend to be lost, they provide stability similar to ball bearings. After the conductive layer 310 and/or the dielectric layer 315 is deposited, the diodes 100-100L are effectively held or secured in place, and the likelihood of dislodging is significantly reduced. The inert particles are also held or fixed in place, but serve no additional function in the finished devices 300, 700, 720, 730, 740, 750, 760, 770, and are effectively electrically and chemically inert. A plurality of inert particles 292 are illustrated in cross-section in FIG. 94 and not separately illustrated in other drawings, but may be included in any of the other illustrated devices.

Diode Ink Examples 20-27 are illustrated to provide additional, more specific embodiments of diode ink compositions effective for making the various apparatus 300, 700, 720, 730, 740, 750, 760, 770 aspects. Diode ink Example 20 and other examples having a cellulosic or methylcellulose resin such as hydroxy propyl methylcellulose resin include, but are not limited to, additional solvents not specifically mentioned, such as water or 1-methoxy-2-propanol. can be included as

In general, the various diode inks are mixed in the order described above, but the various first solvent, viscosity modifier, second solvent, and third solvent (eg water) may be added in other orders or mixed together, of which It should be noted that any and all are within the scope of this disclosure. For example, deionized water (as a third solvent) is first added, followed by 1-propanol and DBE-9, followed by a viscosity modifier, and then, if desired, for example in order to control the relative proportions and viscosity, additional Water may also be added.

Substantially a mixture of a first solvent (eg NPA), a diode 100-100L, a viscosity modifier, a second solvent, and (if present) a third solvent (eg water) is added to the mixture, for example air Mix or shake using an impeller mixer for about 25-30 minutes at room temperature under atmospheric atmosphere at a relatively low speed to avoid entrainment. In an exemplary embodiment, the final volume of diode ink is typically about 1/2 to 1 L (per wafer) containing 9 to 10 million diodes 100 to 100 L, and the concentration of diodes 100 to 100 L is, for example, as described below Exemplary viscosity ranges for different types of printed or different types of diodes 100 to 100L are described above, which can be adjusted up or down as required, depending on the concentration required for the selected printed LED or photovoltaic device. A first solvent, such as NPA, also acts as a preservative and tends to inhibit bacterial and fungal growth for storage of the final diode ink. If other first solvents are to be used, a separate preservative, inhibitor or fungicide may also be added. In exemplary embodiments, additional surfactants or antifoam agents for printing may optionally be used, but are not required for proper functionalization and exemplary printing.

The concentration of diodes 100-100L can be adjusted according to device requirements. For example, for lighting applications, a low surface brightness lamp can use about 25 diodes 100 to 100 L per square centimeter using a diode ink of about 12,500 diodes/ml (cm 3 ) diodes at a concentration of 100 to 100 L of diodes. . In another exemplary embodiment, one wafer 150 may contain about 7.2 million diodes 100-100L for about 570 mL of diode ink. Each 1 ml of diode ink can be used to cover about 500 cm 2 in printing, and 570 ml of diode ink covers about 28.8 m 2 . Also, for example, for a very high surface brightness lamp, a 100-100L concentration of diodes of about 50,000/ml (cm 3 ) would be required to use about 100 diodes 100-100L per cm 2 .

75 is a flow chart illustrating an exemplary method embodiment of a diode ink, and provides a useful overview. The method starts from a starting step 200, wherein the diodes 100-100L are released from the wafers 150, 150A (step 205). As discussed above, this step attaches the wafer on the first diode side to the wafer holder with a wafer bond adhesive using laser lift-off, and grinds and/or polishes and/or the second, back side of the wafer. Etch to expose the singulation trenches, remove any additional substrate or GaN, if required or specified, and dissolve the wafer bond adhesive in a solvent such as IPA or another solvent such as NPA or any other solvents described above and releasing the diodes 100 to 100L. When using IPA, the method includes optional step 210 of transferring the diodes 100-100L to a (first) solvent such as NPA. The method then involves adding 100-100 L of the diode in a first solvent to a viscosity modifier such as methylcellulose (step 215) and one or more second solvents, such as one or two dibasic esters, such as For example, dimethyl glutarate and/or dimethyl succinate are added (step 220). A third solvent such as deionized water may be used to adjust any weight ratio (step 225). Then, at step 230, the method includes a plurality of diodes 100-100L, a first solvent, a viscosity modifier, a second solvent (and a plurality of chemically and electrically inert particles, eg, glass beads) and any further desorption Ionized water is mixed at room temperature (about 25° C.) for about 25 to 30 minutes under an atmospheric atmosphere, and the final viscosity is about 1,000 cps to about 25,000 cps. The method may then end (return step 235). It should also be noted that steps 215, 220, and 225 may occur in other orders as described above and may be repeated as needed and any additional mixing steps may be used.

76 is a perspective view of an exemplary apparatus 300 aspect. 77 is a top (or top) view of an exemplary electrode structure of a first conductive layer for an exemplary device embodiment. 78 is a first cross-sectional view (through the 30-30' plane of FIG. 76) of an exemplary device 300 embodiment. 79 is a second cross-sectional view (through the 31-31' plane of FIG. 76) of an exemplary device 300 embodiment. 80 is a perspective view of an exemplary second device 700 aspect. 81 is a first cross-sectional view (through the 88-88' plane of FIG. 80) of an exemplary second device 700 embodiment. 82 is a first cross-sectional view (through plane 87-87' in FIG. 80) of an exemplary second device 700 embodiment. 83 is a second cross-sectional view of exemplary diodes 100J, 100K, 100D and 100E coupled to a first conductor 310A. 87 is a cross-sectional view of an exemplary third device 300C embodiment for providing light emission from two sides. 88 is a cross-sectional view of an exemplary fourth device 300D embodiment for providing light emission from two sides. 89 is a more detailed partial cross-sectional view of an exemplary first device embodiment. 90 is a more detailed partial cross-sectional view of a second exemplary device embodiment. 91 is a perspective view of an exemplary fifth device 720 aspect. 92 is a cross-sectional view (through the 57-57' plane of FIG. 91 ) of a fifth exemplary embodiment of an apparatus 720; 93 is a perspective view of an exemplary sixth device 730 aspect. 94 is a cross-sectional view (through the 58-58' plane of FIG. 93) of a sixth exemplary embodiment of an apparatus 730; 95 is a perspective view of an exemplary seventh device 740 aspect. 96 is a cross-sectional view (through the 59-59' plane of FIG. 95) of a seventh exemplary device 740 embodiment. 97 is a perspective view of an eighth exemplary device 750 aspect. 98 is a cross-sectional view (through the 61-61' plane of FIG. 97) of an eighth exemplary device 750 embodiment. 99 is a top (or top) view of an exemplary second electrode structure of a first conductive layer for an exemplary device embodiment. FIG. 101 is a plan (or top) view of an exemplary ninth and tenth device 760, 770 aspect, typically used with the system 800, 810 aspect illustrated in FIG. 100 . 102 is a cross-sectional view (through the 63-63′ plane of FIG. 101 ) of a ninth exemplary device 760 embodiment. 103 is a cross-sectional view (through the 63-63' plane of FIG. 101) of a tenth exemplary device 770 embodiment. 109 is a photograph of an exemplary device 300A embodiment that is excited to emit light.

76-79, in device 300, one or more first conductors 310 are deposited over a substrate 305 on a first side, followed by a plurality of diodes 100-100K (connecting the second terminal 127 to the conductor 310) coupling), dielectric layer 315, second conductor(s) 320 (typically transparent conductors coupling to the first terminals), optionally followed by stabilization layer 335, light emitting (or light emitting) layer 325, and protection A layer or coating 330 is deposited. In this device 300 aspect, when an optically opaque substrate 305 and first conductor(s) 310 are used, light is primarily emitted or absorbed through the top first face of the device 300, the optically transmissive substrate 305 and the first conductor When(s) 310 is used, light is emitted or absorbed from both sides of the device 300, particularly if it is excited with an AC voltage to excite a diode 100-100K having a first or second orientation.

80-83 , in device 700 , a plurality of diodes 100L is deposited over a first side of a substrate 305 (which is optically transmissive and is therefore referred to herein as substrate 305A), followed by one or more first conductors. 310 (coupling the second terminal 127 to the conductor 310), a dielectric layer 315, a second conductor(s) 320 (coupling the first terminals), which may or may be optically transmissive not), and optionally subsequently a stabilizing layer 335 and a protective layer or coating 330 are deposited. an optional light emitting (or light emitting) layer 325, before or after any of the deposition steps on the first side of the substrate 305, along with any other protective layer or coating 330, the second side of the substrate 305 can be applied to In this device 700 aspect, when one or more optically opaque second conductors 320 are used, light is primarily emitted or absorbed through the substrate 305A of the device 700 on the second side, and the one or more optically transmissive second conductors 320 When used, light is emitted or absorbed at both sides of the device 700 .

Aspects of the various devices 300, 700, 720, 730, 740, 750, 760, 770 may be printed as flexible sheets of LED-based lights or other luminaires, for example, they may contain architectural shapes, etc. Curled, folded into any of a variety of shapes and designs of any kind including, but not limited to, folded and crimped origami shapes of artistic or fanciful designs, Edison bulb shapes, fluorescent bulb shapes, chandelier shapes, etc. ), twisted, spiraled, flattened, knotted, cresed, and otherwise shaped, one such curled and folded Edison bulb shape is a system 800 and 810 are illustrated in FIG. 100 . The various apparatus 300, 700 aspects may also be combined in various ways, for example back-to-back, to have light emitted or absorbed from both sides of the resulting device. . For example, and not by way of limitation, two devices 300 may be combined back-to-back on the second side of each substrate 305 to form the device 300C aspect, or the device 300 may be printed on both sides of the substrate 305. to form device 300D aspects, which are illustrated in cross-sectional views in FIGS. 87 and 88 , respectively. Also, for example, and not by way of limitation, although not separately illustrated, two devices 700 can also be combined back-to-back on a non-substrate 305, a first side, to provide light emission from both sides of the resulting device. You may.

91 and 92 , in device 720 , a first conductor 310 is deposited as one or more layers over a substrate 305 on a first side, followed by a carbon contact 322A for coupling to the conductor 310 is deposited, followed by a plurality of diodes 100 to 100K (coupling the second terminal 127 to the conductor 310), a dielectric layer 315, and also a second conductor 320 deposited as one or more layers (generally transparent to couple to the first terminals) conductors) are deposited, followed by a carbon contact 322B for coupling to the conductor 320, optionally followed by a stabilizing layer 335, a light emitting (or light emitting) layer 325, and a protective layer or coating 330. In this device 300 aspect, light is emitted or absorbed primarily through the top first face of the device 720, and when an optically transmissive substrate 305 and first conductor 310 are used, the light is emitted from the device, particularly if excited with an AC voltage. It is emitted or absorbed from both sides of 720 .

93 and 94 , in device 730 , a first substantially optically transmissive conductor 310 is deposited as one or more layers over an optically transmissive substrate 305A on a first side, followed by carbon contacts 322A for coupling to the conductor 310 . is deposited, followed by a plurality of diodes 100 to 100K having a plurality of inert particles 292 (coupling the second terminal 127 to the conductor 310), a dielectric layer 315, and a second conductor also deposited as one or more layers. 320 (typically transparent conductors coupling to the first terminals) is deposited, followed by a carbon contact 322B for coupling to the conductor 320, optionally followed by a stabilization layer 335, a first light emission (or light emission) ) layer 325, and a protective layer or coating 330 are deposited, followed by a second light emitting (or light emitting) layer 325, and a protective layer or coating 330 on the second side of the substrate 305A. In this device 730 aspect, light is emitted or absorbed through the top first side and bottom second side of the device 730. Additionally, use of the second light emitting (or light emitting) layer 325 may also shift the wavelength of light emitted through the second facet (additionally, the first light emitting (or light emitting) layer 325 may shifting the spectrum of light emitted through the first face).

95 and 96, in device 740, a plurality of diodes 100L are deposited over a first side of a substrate 305 (which is optically transmissive, also referred to herein as substrate 305A), followed by a first conductor 310 with one a second conductor 320 deposited as one or more layers (coupling the conductor 310 to the second terminal 127), followed by a carbon contact 322A for coupling to the conductor 310, a dielectric layer 315, and also as one or more layers coupling to the first terminals), followed by a carbon contact 322B for coupling to the conductor 320, optionally followed by a stabilizing layer 335 and a protective layer or coating 330. an optional light emitting (or light emitting) layer 325, before or after any of the deposition steps on the first side of the substrate 305, along with any other protective layer or coating 330, the second side of the substrate 305 can be applied to In this device 740 aspect, light is emitted or absorbed primarily through the substrate 305A of the device 740 on the second side (and has any shift in wavelength from the first light emitting (or light emitting) layer 325 ); When one or more optically transmissive second conductors 320 are used, light is emitted or absorbed at both sides of the device 740 .

97 and 98, in device 750, a plurality of diodes 100L are deposited over a first side of a substrate 305 (which is optically transmissive, also referred to herein as substrate 305A), followed by a first conductor 310 with one A substantially optically transmissive agent deposited as one or more layers (coupling the conductor 310 to the second terminal 127), followed by a carbon contact 322A for coupling to the conductor 310, a dielectric layer 315, and also as one or more layers. A second conductor 320 (which couples to the first terminals) is deposited, followed by a carbon contact 322B for coupling to the conductor 320, and optionally followed by a stabilization layer 335, optionally a first light emitting (or light emitting) layer 325 , and a protective layer or coating 330 are deposited. An optional second light emitting (or light emitting) layer 325 may be applied to the second light emitting (or light emitting) layer 325 of the first side of the substrate 305A, together with any other protective layer or coating 330, before or after any of the deposition steps on the first side of the substrate 305. It can be applied on two sides. In this device 750 aspect, light is emitted or absorbed through both the top first side and the bottom second side of the device 750, and also at any wavelength from the first and second light emitting (or light emitting) layers 325 . have a move

Devices 760 and 770 will be described in greater detail below with reference to Figures 100-103, which also differ from the other illustrated devices in that they also use a third conductor 312 that is typically deposited as one or more layers. Additionally, device 770 also illustrates the use of barrier layer 318, discussed in more detail below.

As noted above, the devices 300, 700, 720, 730, 740, 750, 760, 770 can be formed by depositing (eg, printing) a plurality of layers on a substrate 305, i.e., devices 300, 720, 730, For 750, one or more first conductors 310 are deposited over the substrate 305 as a layer or plurality of conductors 310, followed by a diode 100-100L (with a wet film thickness of about 18-20 μm or greater) liquid or gel suspension (i.e. diode ink), evaporating or dispersing the liquid/gel portion of the suspension; thickness) as a liquid or gel suspension on the first side of the optically transmissive substrate 305A (i.e. diode ink), evaporating or dispersing the liquid/gel portion of the suspension, followed by dispersing the one or more first conductors 310 formed by deposition.

When the liquid or gel suspension of the diodes 100-100L is dried or cured, the components of the diode ink (particularly the viscosity modifiers or adhesive viscosity modifiers as mentioned above) are distributed around the diodes 100-100L, FIGS. 89 and 90 A relatively thin membrane, coating, grid or mesh exemplified as membrane 295 in about 50-100 nm for the modifier, and about 200-300 nm for high concentrations of the viscosity modifier) to help hold them in place on the substrate 305 or the first conductor(s) 310 . The deposited film 295 may be continuous and surround the diodes 100-100L as illustrated in FIG. 89 or may be discontinuous as illustrated in FIG. 90 and only partially surround the diodes 100-100L leaving gaps. can rice Terminals 125, 127 are usually coated with a diode ink film 295, but generally sufficient surface roughness of terminals 125, 127 is present so that film 295 does not interfere with the manufacture of electrical connections to the first and second conductors 310, 320. does not Film 295 is typically in cured or dried form of a viscosity modifier, and potentially also in small or trace amounts of various solvents, eg, a first or agent as noted below with reference to cured or dried diode ink embodiments. 2 contains a solvent. Further, as discussed in more detail below, the viscosity modifier may also be used to form the barrier layer 318 discussed below with reference to FIG. 103 .

For device 300, a diode 100 to 100K is physically and electrically coupled to one or more first conductors 310A, and for device 700, a diode 100K is physically coupled to a substrate 305 and subsequently to one or more first conductors 310A. As coupled to conductors 310 and deposited suspended in any orientation in a liquid or gel, in both device 300 and 700 aspects, diodes 100 - 100L have a first orientation (first terminal 125 in top orientation). , in a second orientation (first terminal 125 in the bottom direction), or possibly in a third orientation (first terminal 125 being lateral). In addition, the diodes 100-100L are typically very irregularly spaced within the devices 300, 700, as they are deposited while suspended in a liquid or gel. Further, as noted above, in exemplary embodiments, the diode ink comprises a plurality of, having a size range of about 10 to 30 μm, or more particularly about 12 to 28 μm, or more particularly about 15 to 25 μm. Conventional optically transmissive particles that are chemically inert, for example glass beads.

In a first top orientation or orientation, as illustrated in FIG. 83 , first terminal 125 (metal layer 120B forming bumps or protrusions for diodes 100 - 100J or metal layer 122 of diode 100K) is oriented upwards and , diodes 100 to 100K have a second terminal 127 (which may be metal layer 120B for diode 100K), or back metal layer 122 as illustrated for diode 100J, or diode 100D (any back metal layer of diode 100J). coupled to the one or more first conductors 310A via a central via 131 as illustrated for 122 (implemented without 122), or a peripheral via 134 (not separately illustrated), or through a substrate 105 as illustrated for diode 100E. . In a second bottom orientation or orientation, as illustrated in FIGS. 78 and 79 , the first terminal 125 is oriented downward and the diodes 100 - 100K are connected to the first terminals 125 (eg, bumps for diodes 100 - 100J or It can be coupled or coupled to the one or more first conductors 310A via the metal layer 120B forming the protruding structure or the metal layer 122 of the diode 100K.

For diode 100L, diode 100L may be oriented in a first top orientation or orientation in which first terminal 125 and second terminal 127 are both oriented upward as illustrated in FIGS. 81 and 82 , or not otherwise illustrated, The first terminal 125 and the second terminal 127 may be oriented in a second bottom orientation or orientation in which both are oriented downward. For this bottom orientation, the first terminal 125 may be in electrical contact with the one or more first conductors 310, while the second terminal 127 is more likely to be in the dielectric layer 135 and not in contact with the second conductor 320; It should be noted that the diode 100L becomes electrically isolated and non-functional when it has the second orientation, which may be desirable in many aspects.

exactly where and in any orientation on the substrate 305A or the one or more first conductors 310 so long as the diodes 100-100L are deposited suspended in a liquid or gel in any 360 degree orientation with an intermediate spacing therebetween. It cannot be known with certainty in advance (eg, within an average non-defect rate of 4 to 6 sigma for highest quality manufacturing). More precisely, there will be statistical distributions for both the spacing of the diodes 100-100L from each other and the orientation of the diodes 100-100L (first top or second bottom). What can be said with great certainty is that at least one diode 100-100L out of a potentially millions of diodes 100-100L terminates in the second orientation because it is deposited as dispersed or suspended in a liquid or gel.

Thus, the distribution and orientation of diodes 100 to 100L in devices 300, 700, 720, 730, 740, 750, 760, 770 can be statistically described. For example, prior to deposition, it is unknown or impossible to estimate exactly where and in what orientation any particular diode 100 to 100L will be placed over the substrate 305A or one or more first conductors 310 and held in place, but, on average, A number of diodes 100-100L will be present in a particular orientation in a particular concentration of diodes 100-100L per unit area (eg, but not limited to, 25 diodes/cm 2 diodes 100-100L).

Thus, diodes 100 - 100L can be effectively considered to be irregularly spaced or deposited in a random or pseudo-random orientation, or they can be oriented upward in a first orientation (top of first terminal 125 ) or (which is typically (depending on the polarity of the applied voltage) is forward biased voltage direction for diode 100 to 100J and reverse biased direction for diode 100K), may face down in a second orientation (bottom first terminal 125) (this is typically is the reverse bias voltage direction for diodes 100 to 100J and forward bias direction for diode 100K (depending on the polarity of the applied voltage). Similarly, it can face up in a first orientation (top of first and second terminals 125, 127) (this is typically the forward bias voltage direction for diode 100L), or it can face down in a second orientation. (bottom first and second terminals 125, 127) (this is typically the reverse bias voltage direction for diode 100L (depending on the polarity of applied voltage)) For diode 100L, as mentioned above and in more detail below As described, the diode 100L in the second orientation is typically not sufficiently electrically coupled and non-functional. It is also possible to deposit diodes 100-100L in a third orientation (bottom diode side 121 and top another diode side 121) or terminate laterally.

Fluid dynamics, viscosity or rheology of diode ink, screen mesh count, screen mesh opening, screen mesh material (surface energy of the screen mesh material), printing speed, tines of the interdigitated or comb-like structures of the first conductor 310 ) (the branches are perpendicular to the direction of movement of the substrate 305 through the printing press), the surface air paper of the substrate 305 or the first conductor(s) 310 on which the diodes 100-100L are deposited, the shape of the diodes 100-100L and the size, printing or deposition density of diodes 100-100L, shape, size and/or thickness of diode side 121, and sonication or other mechanical vibration of liquid or gel suspension of diodes 100-100L prior to curing or drying of diode ink appears to affect the predominance of one first, second or third orientation over another first, second or third orientation. For example, diode side 121 is less than about 10 μm in height (or vertical thickness, perpendicular to the first or second orientation), and more particularly less than about 8 μm in height so that diodes 100-100L have relatively thin faces or edges. case, the proportion of diodes 100 to 100L with the third orientation is significantly reduced.

Similarly, hydrodynamics, higher viscosity, and lower mesh counts and other factors mentioned above provide some control over the orientation of diodes 100-100L, such that diodes 100-100L in either the first or second orientation. Allows for adjustment or adjustment of the ratio for a given field. For example, the factors listed above may be adjusted to increase the occupancy of the first orientation, such that 80% to 90% or more of the first orientation of the diodes 100-100L is obtained. Also, for example, the factors listed above may be adjusted to balance the occupancy of the first and second orientations, such that an approximately or substantially equivalent distribution of the first and second orientations of the diodes 100 - 100L; For example, 40% to 60% of diodes 100-100L in a first orientation and 60%-40% of diodes 100-100L in a second orientation can be obtained.

Although the proportion of diodes 100-100L coupled to a first conductor 310A or substrate 305 in a first top orientation or orientation is significantly high, it is statistically unlikely that at least one diode 100-100L has a second bottom orientation or orientation. It should be noted that significant, statistically, diodes 100-100L also exhibit irregular spacing, such that some diodes 100-100J will be relatively closer apart, and at least some diodes 100-100J will be much further apart.

Stated another way, depending on the polarity of the applied voltage, a significantly higher proportion of diodes 100-100L will or will couple in the first forward bias orientation or direction, but statistically at least one diode 100-100L will will have a second reverse bias orientation or orientation. Also, those skilled in the art will know that if the light emitting or light absorbing regions 140 are oriented differently, depending on the polarity of the applied voltage, the first orientation will have a reverse biased orientation and the second orientation will have a forward biased orientation. will recognize

Conventional electronics manufacturing, for example, in which electrical members, such as diodes, are placed within selected tolerance levels for surface mounting in a predetermined orientation in a predetermined location on a circuit board using a pick and place machine; Otherwise, in any particular case, there is no such pre-determined or specific position (in the x-y plane) and orientation (z-axis) for diodes 100 - 100L in devices 300 , 700 (ie, at least one diode 100 - 100L). 100L will be in the second orientation in devices 300 and 700).

This means that these diodes (eg LEDs) all have a single orientation with respect to the voltage rail, i.e. their corresponding anodes are coupled to a higher voltage and their cathodes are coupled to a lower voltage. There is a significant departure from the conventional ring structure of the device. As a result of the statistical orientation, depending on the proportion of the diodes 100 to 100L with either a first or a second orientation, and depending on various diode characteristics such as tolerance for reverse bias, the diodes 100-100L can be switched to AC without further switching of voltage or current. Alternatively, it can be excited using DC voltage or current.

77 and 99, a first plurality of conductors 310 may be used, such that an interdigitated or comb electrode structure of a first (first) conductor electrode or contact 310A and a second (first) conductor electrode or contact 310B At least two separate electrode structures illustrated as can be formed. As illustrated in FIG. 77, conductors 310A and 310B have the same width, and are illustrated in FIGS. 76 and 78 as having different widths, all such variations being within the scope of the present disclosure. For the exemplary device 300 embodiment, the diode ink or suspension (with diodes 100-100K) of interest is deposited over conductor 310A, as illustrated in FIG. 78 . A second transparent conductor 320 (optically transmissive, discussed below) is subsequently deposited (over the dielectric layer, as discussed below) to create a separate electrical contact with conductor 310B. Optionally, although not separately illustrated, exemplary device 700 aspects may have these 310A, 310B electrical connections: a diode ink or suspension of interest (with diode 100L) is deposited over the substrate 305A, and one or more conductors 310A and 310B (as a cross- or comb-like structure) may be deposited, and a dielectric layer 315 may be deposited over conductor 310A. A second conductor 320, which need not be optically transmissive, is subsequently deposited (over the dielectric layer 315 as discussed below), and may also have an interlocking or comb-like structure, as illustrated in FIG. 78 for device 300 . A separate electrical contact with conductor 310B can be created as shown. 80-82 for device 700, to illustrate yet another structural alternative, a second terminal 127 is coupled to one or more first conductors 310, and a first terminal 125 is coupled to one or more second conductors. coupled to s 320 . 81 and 91-98 also illustrate another structural option applicable to any of the device 300, 700, 720, 730, 740, 750, 760, 770 aspects, wherein the carbon electrodes 322A and 322B are Coupled to the first conductor 310 and the second conductor 320, respectively, and extending from the protective coating 330, to provide an electrical connection or coupling to the devices 300 and 700 in question.

It should be noted that if the first conductor 310 has the interlocking or comb-like structure illustrated in FIG. 77 , the second conductor 320 may be excited using the first conductor 310B. The interdigitated or comb-like structure of the first conductor provides electrical current balancing such that substantially all current paths through the first conductor 310A, the diodes 100-100L, the second conductor 320, and the first conductor 310B are within a predetermined range. This reduces resistance and heat generation by minimizing the distance the current must travel through the second transparent conductor, and generally acts to provide current to all or most of the diodes 100-100L in parallel within a range of current levels. do.

Additionally, a plurality of interdigitated or comb-like structures for the first conductor 310 may be sequentially configured to produce an overall device voltage having a desired number of diodes 100-100J forward voltage, such as, but not limited to, a typical household voltage. may be coupled. For example, as illustrated in FIG. 99 , for a first region 711 (with diodes 100-100L coupled in parallel), conductor 310B is connected to a second region 712 (which also has its diodes 100 coupled in parallel) may be coupled or deposited as an integral layer with conductor 310A of (having diodes 100-100L coupled in parallel), for a second region 712 (having diodes 100-100L coupled in parallel), conductor 310B is coupled to a third region 713 (which is also coupled or deposited as an integral layer with conductor 310A of its diodes 100-100L coupled in parallel, such that the first, second and third regions 711, 712, 713 are coupled in series and , these regions each have diodes 100 to 100L coupled in parallel. This cascading connection is also used in the system 800, 810 and device 760, 770 aspects illustrated in FIGS. 100-103.

Also, as illustrated in FIG. 99 , excitation of any of the interdigitated or comb electrode structures can be performed by applying a voltage level to the busbar 714 coupled to both of the respective branches 310A, 310B. have. The busbar 714 is typically sized to have a relatively low sheet resistance or impedance.

For relatively smaller areas or other fields such as graphic arts, such a current balancing and impedance matching (sheet resistance matching) structure is unnecessary, and a simpler structure such as the layer structure illustrated in Figs. The first and second conductors 310 and 320 may be used. For example, such a stack structure may be used when the sheet resistance of the first and second conductors 310, 320 combined with the diodes 100 to 100L is a relatively or relatively small proportion of the total resistance of the first and second conductors 310, 320. can Also, as illustrated in FIGS. 102 and 103 , the third conductive layer 312 provides parallel busbar connections, for example along relatively long strips of devices 300 , 700 , 720 , 730 , 740 , 750 , 760 , 770 . can also be used to

One or more dielectric layers 315 are then deposited over the diodes 100-100L, the first terminal 125 in the first orientation or the second, backside of the diodes 100-100K when in the second orientation (or the GaN of the diode 100L). heterostructure) to provide electrical insulation between one or more first conductors 310 (coupled to the diode 100-100L) and one or more second conductors 320 deposited over one or more dielectric layers 315 in such a way as to create corresponding physical and electrical contact with the first terminal 125 or the second, backside of the diode 100 to 100K, depending on the orientation. For device 300, an optional light emitting (or light emitting) layer 325 may then be deposited, followed by an optional stabilizing layer 335 and/or an optional lensing, dispersing or sealing layer 330 . For example, any such light emitting (or light emitting) layer 325 may include a stroke transition phosphor layer to produce a lamp or other device that emits a desired color or other selected wavelength range or spectrum. These various layers, conductors and other deposited compounds are discussed in more detail below. For device 700, a lancing, dispersing, or sealing layer 330 is generally deposited over one or more second conductors on a first side, followed by the optional light emitting (or light emitting) layer 325 over the substrate 305 on the second side. An optional stabilizing layer 335 and/or an optional lancing, dispersing or sealing layer 330 may be deposited thereon. Depending on the location of the first and second conductors 310, 320, the carbon electrodes 322A, 322B may be applied after deposition of the corresponding first and second conductors or after any deposition of the lancing, dispersing or sealing layer 330. These various layers, conductors and other deposited compounds are discussed in more detail below.

Substrate 305 may be formed from or comprise any suitable material, such as, but not limited to, plastic, paper, cardboard, or coated paper or cardboard. The substrate 305 may comprise any flexible material having strength to withstand the conditions of its intended use. In an exemplary embodiment, substrates 305, 305A are substantially optically transmissive polyester or plastic sheets, such as print receptiveness treated and MacDermid Autotype, Inc. of Denver, Colorado (USA). CT-5 or CT-7 5 or 7 wheat polyester (Mylar) sheet commercially available from Autotype, Inc., or Coveme acid treated Mylar. In another exemplary embodiment, the substrate 305 also comprises a polyimide film, such as Kapton commercially available from DuPont, Inc. of Wilmington, Del. Further, in an exemplary aspect, the substrate 305 comprises a material having a dielectric constant suitable for or capable of providing sufficient electrical insulation for a selectable excitation voltage. Substrate 305 may also be, for example, any one or more of the following: paper, coated paper, plastic coated paper, fiber paper, cardboard, poster paper, poster board, book, magazine, newspaper, woodblock, plywood, and any other paper or wood products in the selected form; plastic or polymeric material in any selected form (sheet, film, board, etc.); natural or synthetic rubber materials and products in any selected form; natural and synthetic fabrics (carded, meltblown and spunbond nonwovens) of any selected type, including polymeric nonwovens; extruded polyolefin films, including LDPE films; glass, ceramic, and other silicon or silica-derived materials and articles in any selected form; concrete (hardened), masonry, and other building materials and products; or any other products that exist or will be created in the future. In a first exemplary aspect, electrical insulation of one or more first conductors 310 (with respect to each other or other devices or Substrates 305, 305A (having a dielectric constant or insulating properties sufficient to provide electrical insulation to system members) may be selected. For example, a glass sheet or silicon wafer may also be used as the substrate 305, although a relatively expensive option. However, in other exemplary embodiments, a plastic sheet or plastic-coated paper product such as the aforementioned polyester or patent stock available from Sappi, Ltd. and 100 lb. Cover stock or similar coated paper from other papermakers such as Mitsubishi Paper Mills, Mead, and other paper products are used to form the substrate 305 . In another exemplary embodiment, an embossed plastic sheet or plastic-coated paper product having a plurality of grooves, also available from Safi, Ltd., is used, wherein the grooves are used to form the conductor 310 . In further exemplary aspects, any type of substrate 305 may be used, including, but not limited to, those having an additional sealing or encapsulation layer (eg, plastic, lacquer, and vinyl) deposited on one or more surfaces of the substrate 305 can Substrates 305, 305A may also include laminates or other combinations of any of the above materials.

In an exemplary aspect, relatively small sized diodes 100-100L distributed over substrates 305, 305A provide relatively fast heat dissipation without the need for a heat sink, and a substrate comprising materials having a relatively low flash-fire temperature. Offers the availability of a wide range of materials suitable for the 305 and 305A. These temperatures may include, but are not limited to, for example, 50° C. or higher, or 75° C. or higher, or 100° C., or 125° C., or 150° C., or 200° C., or 300° C. For example, but not limited to, it can be measured using the ISO 871:2006 standard. The devices 300, 700 also generally exhibit relatively lower operating temperatures, such as average operating temperatures of less than about 150°C, or less than about 125°C, or less than about 100°C or less than about 75°C, or less than about 50°C. have This average operating temperature should generally be measured after turning on and warming up the device 300, 700 to provide its maximum light output for at least about 10 minutes, for example, but not limited to, at the outermost surface of the device 300, 700. It can be measured incrementally (and can also be averaged arithmetic) using a commercially available infrared thermometer under typical ambient conditions, such as an ambient temperature of about 20-30°C.

Exemplary substrates 305, 305A, as shown in the various figures, have a substantially flat form factor in the generic sense, such as, but not limited to, can be supplied via a printing press and have surface roughness, cavities, channels or grooves. comprising a sheet of a selected material (e.g., paper or plastic) that may have a topology over a first surface (or face) comprising, or substantially smooth (and also cavities, channels, or grooves) within certain tolerances. not including) a first surface. Those skilled in the art will recognize that myriad additional shapes and surface topologies are available, are considered equivalent, and are within the scope of this disclosure.

One or more first conductors 310 are then, for example via a printing process, to a thickness of, for example, about 0.1 to 15 μm (for example conventional silver or nanoparticle silver, depending on the type of conductive ink or polymer) applied (on the first side or surface of substrate 305) for device 300, 720, 730 embodiments, at about 10-12 μm wet film thickness, dry or cured film thickness of about 0.2 or 0.3-1.0 μm for ink or deposited or applied over the diode 100L in the case of device 700, 740, 750 embodiments. In other exemplary aspects, depending on the applied thickness, the first conductor 310 may be sanded to smooth the surface and may also be calendered to compress conductive particles such as silver. In the exemplary methods of making this exemplary device 300, 700, 720, 730, 740, 750, 760, 770, a conductive ink, polymer, or other conductive liquid or gel (eg, silver (Ag) ink or polymer, nano A silver/carbon mixture such as a particle or nanofiber silver ink composition, carbon nanotube ink or polymer, or amorphous nanocarbon (having a particle size of about 75 to 100 nm) is applied to a substrate, for example through a printing or other deposition process. 305 or diode 100L, followed by curing or partial curing (eg, via an ultraviolet (uv) curing process) to form the one or more first conductors 310. In another exemplary embodiment, the one or more first conductors 310 1 The conductors 310 may be formed by sputtering, spin casting (or spin coating), vapor deposition, or electroplating of a conductive compound or element such as a metal (eg, aluminum, copper, silver, gold, nickel). Blends of different types of conductors and/or conductive compounds or materials (eg, inks, polymers, elemental metals, etc.) may also be used to create the one or more composite first conductors 310. Multiple layers and/or types of Metals or other conductive materials may be blended to form one or more first conductors 310, such as, but not limited to, first conductor 310 including, but not limited to, a gold over nickel plate. For example, deposited aluminum or Silver or mixed carbon-silver ink may be used In various exemplary embodiments, a first plurality of conductors 310 may be deposited, and in other aspects, a first conductor 310 may be deposited as a single conductive sheet. (e.g., an aluminum sheet coupled to a substrate 305) (not separately illustrated) Conductive inks that may also be used to form the one or more first conductors 310 in various aspects or the polymer is not cured or only partially cured prior to the deposition of the plurality of diodes 100 to 100K and , can then be fully cured during contact with the plurality of diodes 100 - 100K, for example to create an ohmic contact with the plurality of diodes 100 - 100K. In an exemplary embodiment, the one or more first conductors 310 are completely cured prior to deposition of the plurality of diodes 100-100K, and other compounds of the diode ink that provide slight dissolution of the one or more first conductors 310 are subsequently In general, upon contact with the plurality of diodes 100 to 100K it is cured again, and for the device 700 aspect, the one or more first conductors 310 are fully cured after deposition. Further, for the device 700 aspect, a conductive ink having a low concentration of conductive particles may also be used to form the one or more first conductors 310 to facilitate dewetting from the first terminal 125 . According to a selected aspect, an optically transmissive conductive material may also be used to form the one or more first conductors 310 .

other conductive inks or materials, such as copper, tin, aluminum, gold, precious metals, carbon, carbon black, carbon nanotubes (“CNTs”), single or double or multi-walled CNTs, graphene, graphene plates; Nanographene plates, nanocarbon and nanocarbon and silver compositions, nanoparticle and nanofiber compositions having good or acceptable light transmittance, or other organic or inorganic conductive polymers, inks, gels or other liquid or semi-solid materials may also include one or more It may be used to form the first conductors 310, the second conductor(s) 320, the third conductor (not separately illustrated), and any other conductors discussed below. In an exemplary embodiment, to enhance the ohmic contact and adhesion between the diodes 100-100L and the first conductor 310, carbon black (having a particle diameter of about 100 nm) is added to a final carbon concentration in the range of about 0.025% to 0.5%. is added to the ink. Additionally, any other printable or coatable conductive materials may equally be used to form the first conductor(s) 310, the second conductor(s) 320 and/or the third conductor, and exemplary conductive compounds include: ; AG-500, AG-800 and AG-510 are conductive inks; (2) 7102 carbon conductor from DuPont (if overprinting 5000 Ag), 7105 carbon conductor, 5000 silver conductor, 7144 carbon conductor (with UV encapsulant), 7152 carbon conductor), and 9145 silver conductor; (3) 128A silver conductive ink, 129A silver and carbon conductive ink, 140A conductive ink, and 150A silver conductive ink from SunPoly, Inc.; (4) PI-2000 series high conductivity silver inks from Dow Corning, Inc.; (5) Electrodag 725A from Henkel/Emerson &Cumings; (6) Monarch M120, available from Cabot Corporation of Boston, Massachusetts, for use as a carbon black additive to silver ink to form carbon and silver ink mixtures; (7) Acheson 725A conductive silver ink (available from Henkel) alone or in combination with additional silver nanofibers; and (8) Inktek PA-010 or PA-030 nanoparticles or nanofiber silver screen-printable conductive inks available from Inktec., Gyeonggi-do, Korea. As discussed below, these compounds may also be used to form the second conductor(s) 320 and other conductors including any other conductive traces or connections. Additionally, conductive inks and compounds are available from a wide variety of other sources.

Conductive polymers that are substantially optically transmissive may also be used to form one or more of the first conductors 310, and also the second conductor(s) 320 and/or the third conductor. Polyethylene-deoxythiophene, such as polyethylene-deoxythiophene, sold, for example, under the trade designation "Orgacon" from AGFA Corp. of Ridgefield Park, NJ, as well as other permeable conductors discussed below. and their equivalents may be used. Other conductive polymers that may equally be used include, but are not limited to, for example, polyaniline and polypyrrole polymers. In another exemplary embodiment, carbon nanotubes suspended or dispersed in a polymerizable ionic liquid or other fluid are used to form a variety of substantially optically transmissive or transparent conductors, such as one or more second conductors 320 . For device 300 aspect, the one or more second conductors 320 are generally substantially optically transmissive to provide greater light emission or absorption on the first side of the device, and for device 700 aspect, the one or more second conductors It should be noted that fields 320 are generally not appreciably optically transmissive to provide a relatively lower electrical impedance, unless light output on the first side is also desired. In some exemplary device 700 aspects, the one or more second conductors 320 are highly opaque and reflective to act as a mirror and increase light output from the second side of the device 700.

The optically transmissive conductive ink used to form the one or more second conductors 320 includes a transparent conductive ink commercially available from NH Degree Technologies Worldwide, Inc. of Tempe, Arizona, USA, which was manufactured on 2/2011 It is described in U.S. Provisional Patent Application No. 61/447,160 (Mark D. Lowenthal et al.) of the title "Metallic Nanofiber ink, Substantially Transparent Conductor, and Fabrication Method" filed on the 28th, and the entire content thereof is described in its entirety It is hereby incorporated by reference with the same effect as used herein. Another transparent conductor includes a mixture of solvents, such as 1-butanol, cyclohexanol, ice-cold acetic acid (about 1% by weight), and polyvinylpyrrolidone (about 1,000,000 MW) (about 2% to 4% by weight). , or more particularly about 3% by weight) of silver nanofibers (about 3% to 50% by weight, or more particularly about 4% to 40% by weight, or more particularly about 5% to 30% by weight, or more particularly about 6% by weight) % to 20% by weight, or more particularly from about 5% to 15% by weight, or more particularly from about 7% to 13% by weight, or more particularly from about 9% to 11% by weight, or more particularly from about 10% by weight). . Another conductive ink may contain nanoparticles or particles, admixed with a plurality of other solvents, for example, from about 50% to 65% by weight of propylene glycol and from about 1% to 10% by weight of n-propanol or 1-methoxy-2-propanol. Nanofiber silver ink (eg, Inktek PA-010 or PA-030 nanoparticles or nanofiber silver screen printable conductive ink) from about 30% to 50% by weight. Another conductive ink is a nanoparticle or nanofiber silver ink (e.g., Inktek PA-010 or PA-030 nanoparticle or nanofiber silver screen printable conductive ink mixed with a plurality of other solvents as mentioned above. ) (a silver concentration of about 0.30% to 3.0% by weight).

Organic semiconductors, variously referred to as π-conjugated polymers, conducting polymers, or synthetic metals, are semiconducting in nature due to the π-conjugation between carbon atoms along the polymer backbone. Their structure contains a one-dimensional organic framework that enables electrical conduction after n- or p+ type doping. A well-studied class of organic conductive polymers includes poly(acetylene), poly(pyrrole), poly(thiophene), polyaniline, polythiophene, poly(p-phenylene sulfide), poly(para-phenylene vinylene) ( PPV) and PPV derivatives, poly(3-alkylthiophene), polyindole, polypyrene, polycarbazole, polyazulene, polyazepine, poly(fluorene) and polynaphthalene. Other examples include polyaniline, polyaniline derivative, polythiophene, polythiophene derivative, polypyrrole, polypyrrole derivative, polytianaphthene, polytianaphthane derivative, polyparaphenylene, polyparaphenylene derivative, polyacetylene, polyacetylene derivative , polydiacetylene, polydiacetylene derivatives, polyparaphenylenevinylene, polyparaphenylenevinylene derivatives, polynaphthalene, and polynaphthalene derivatives, polyisothianaphthene (PITN), polyheteroarylenevinylene (ParV) ) (wherein the heteroarylene group may be, for example, thiophene, furan or pyrrole), polyphenylene-sulfide (PPS), polyperinaphthalene (PPN), polyphthalocyanine (PPhc), etc., and their derivatives, copolymers thereof and mixtures thereof. The term derivative as used herein refers to a polymer prepared from monomers substituted with branched or groups.

The polymerization method of the conductive polymers is not particularly limited, and the usable methods include, but are not limited to, for example, uv or other electromagnetic polymerization, thermal polymerization, electrolytic oxidation polymerization, chemical oxidation polymerization, and catalytic polymerization. The polymer obtained by this polymerization process is often neutral and not conductive until doped. Thus, the polymer is converted to a conductive polymer by p-doping or n-doping. The semiconducting polymer may be doped chemically or electrochemically. The material used for doping is not particularly limited, and a material capable of accepting an electron pair, for example, a Lewis acid, is generally used. Examples thereof include hydrochloric acid, sulfuric acid, organic sulfonic acid derivatives such as parasulfonic acid, polystyrenesulfonic acid, alkylbenzenesulfonic acid, camphorsulfonic acid, alkylsulfonic acid, sulfosalicylic acid and the like, ferric chloride, copper chloride, and iron sulfate is included.

For a “reverse” fabrication of device 300, substrate 305 and one or more first conductors 310 are selected to be optically transmissive such that light is introduced through and/or emitted through the second side of substrate 305. Additionally, if the second conductor(s) 320 are also transparent, light may be emitted or absorbed from both sides of the device 300 .

For the one or more first conductors 310, for example, various textures having a relatively smooth surface, or, conversely, a rough or pointed surface, or a machined micro-embossed structure (eg, available from Safi, Ltd.) may be provided, potentially promoting adhesion of other layers (eg, dielectric layer 315) and/or facilitating subsequent formation of ohmic contacts with diodes 100-100L. The one or more first conductors 310 may be provided with a corona treatment prior to deposition of the diode 100-100L, which removes any formable oxides and facilitates subsequent formation of ohmic contact with the plurality of diodes 100-100L. may have a tendency to Those skilled in the electronic or printing arts will recognize that numerous variations in the methods of forming the one or more first conductors 310 and all such variations are considered equivalent and are within the scope of this disclosure. For example, the one or more first conductors 310 may also be deposited via sputtering or vapor deposition without limitation. Additionally, for various other aspects, the one or more first conductors 310 may be deposited as a single or continuous layer, for example, via coating, printing, sputtering, or vapor deposition.

Consequently, "deposit" as used herein means any and all printing, coating, rolling, spraying, layering, sputtering, plating, spin casting, impact or non-impact type known in the art ( or spin coating), deposition, lamination, affixing and/or other deposition processes. "Printing" includes any and all printing, coating, rolling, spraying, laminating, spin coating, laminating and/or affixing processes known in the art, impact or non-impact, specifically, e.g. For example, screen printing, inkjet printing, electro-optic printing, electronic ink printing, photoresist and other resist printing, thermal printing, laser jet printing, magnetic printing, pad printing, flexographic printing, hybrid offset lithography, gravure and other intaglio printing including but not limited to printing. All such processes can be considered and used herein as deposition processes. The above exemplary deposition or printing processes do not require significant manufacturing controls or constraints. No specific temperature or pressure is required. Some cleanroom or filtered air may be useful, but potentially at a level consistent with the standards of known printing or other deposition processes. However, relatively constant temperature (with possible exceptions discussed below) and humidity may be desirable, for example, for consistency with respect to proper alignment (registration) of the various layers deposited in series to form the various aspects. Additionally, the various compounds used may be contained in various polymers, binders or other dispersants that may be thermally cured or dried, air dried at ambient conditions, or IR or uv cured.

In addition, in the present specification, when various compounds are generally applied through printing or other deposition, for example, a resist coating is used, or otherwise, for example, the surface of the substrate 305, various first or second conductors (each By modifying the hydrophilic, hydrophobic or electrical (positive or negatively charged) properties of surfaces, such as the surfaces of 310, 320 and/or the surfaces of diodes 100-100L, thereby modifying the "wettability" of these surfaces, the surface properties or surface energy It should be noted that it can also be controlled. The properties of the compound, suspension, polymer or ink to be deposited, such as surface tension, can cause the deposited compounds to adhere to a desired or selected location and to be effectively repelled from other areas or areas.

For example, the plurality of diodes 100-100L may include any evaporative or volatile organic material such as water, alcohol, ether, etc., which may also include, but is not limited to, a resin and/or a tacky component such as a surfactant or other flow aid. or an inorganic compound is used to be suspended in a liquid, semi-liquid or gel carrier. In an exemplary aspect, for example and not by way of limitation, a plurality of diodes 100 - 100L are suspended as described above in the Examples. Surfactants or flow aids such as octanol, methanol, isopropanol, or deionized water may also be used, and substantially or relatively small nickel beads (e.g., 1 μm) (which provide conduction after compression and curing, e.g. for example, which may act to promote or enhance the creation of ohmic contacts), or any other uv, heat or air curable binder or polymer, including those discussed in more detail below (which may also be used with dielectric compounds, lenses, etc.) Binders such as anisotropic conductive binders containing

Additionally, the various diodes 100 to 100L may be configured as light emitting diodes having various colors such as, for example, red, green, blue, yellow, amber, and the like. Light emitting diodes 100-100L having different colors can then be mixed in the exemplary diode ink to generate a selected color temperature when energized in devices 300, 300A.

Dried or Cured Diode Ink Example 1:

a plurality of diodes 100 to 100L; and

Cured or polymerized resins or polymers

A composition comprising a.

Dried or Cured Diode Ink Example 2:

a plurality of diodes 100 to 100L; and

A cured or polymerized resin or polymer having a thickness of about 10 nm to 300 nm and forming a film at least partially surrounding each diode.

A composition comprising a.

Dried or Cured Diode Ink Example 3:

a plurality of diodes 100 to 100L; and

At least trace amounts of cured or polymerized resin or polymer

A composition comprising a.

Dried or Cured Diode Ink Example 4:

a plurality of diodes 100 to 100L;

cured or polymerized resins or polymers; and

at least trace amounts of solvent

A composition comprising a.

Dried or Cured Diode Ink Example 5:

a plurality of diodes 100 to 100L;

at least trace amounts of a cured or polymerized resin or polymer; and

at least trace amounts of solvent

A composition comprising a.

Dried or Cured Diode Ink Example 6:

a plurality of diodes 100 to 100L;

cured or polymerized resins or polymers;

at least trace amounts of solvent; and

At least trace amounts of surfactant

A composition comprising a.

Dried or Cured Diode Ink Example 7:

a plurality of diodes 100 to 100L;

at least trace amounts of a cured or polymerized resin or polymer;

at least trace amounts of solvent; and

At least trace amounts of surfactant

A composition comprising a.

The diode ink (100-100 L of suspended diode and optional inert particles) is then applied using, for example, a 280 mesh polyester or PTFE-coated screen, onto the substrate 305A for the device 700 aspect, or the device 300 aspect. Deposited over one or more first conductors 310 in the case of , and dissipating volatile or evaporative components via, for example, heating, uv curing or any drying process, the diode 100 - 100L can be substantially or at least partially converted to the substrate 305A or The one or more first conductors 310 are contacted and left attached. In an exemplary embodiment, the deposited diode ink is cured at about 110° C., typically for up to 5 minutes. Dried or Cured Diode Ink As in Examples 1 and 2, the remaining dried or cured diode ink is generally composed of a plurality of diodes 100 to 100L and a cured or polymerized resin or polymer (at least traces), which may generally hold or hold the diodes 100-100L in place) as discussed above, and form the film 295 as discussed above. As illustrated in dried or cured diode ink Examples 3 to 6, volatile or evaporative components (eg, first and/or second solvent and/or surfactant) are substantially dissipated, but traces or their The above amount may remain. A “trace” component as used herein is to be understood as an amount greater than 0% and no more than 5% of the component originally present in the diode ink when initially deposited over the first conductor 310 and/or substrates 305, 305A.

In the finished device 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770, for example, diode 100 as the number of diodes 100 to 100 L per cm 2 The final density or concentration of 100 L to 100 L will depend on the concentration of diode 100 to 100 L in the diode ink. When the diodes 100-100L are in the size range of 20-30 μm, very high densities are available, which still cover only a small percentage of the surface area (one of the above advantages is without the need for a separate heat sink). that allows for greater heat dissipation). For example, if diodes 100-100L in the size range of 20-30 μm are used, 10,000 diodes in one square inch cover only about 1% of the surface area. Also, for example, for use in devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770, from 2 to 10,000/ 100-100L of diodes in cm2; or more specifically, 100 to 100L of 5 to 10,000 diodes/cm 2 ; or more specifically, 5 to 1,000 diodes/cm 2 of 100 to 100L; or more specifically, 5 to 100 diodes/cm 2 of 100 to 100L; or more specifically, 100 to 100L of 5 to 50 diodes/cm 2 ; or more specifically, 5 to 25 diodes/cm 2 of 100 to 100L; or more specifically, 10 to 8,000 diodes/cm 2 of 100 to 100L; or more specifically, 15 to 5,000/cm 2 of diodes 100 to 100L; or more specifically, 20 to 1,000 diodes/cm 2 of 100 to 100L; or more specifically, 25 to 100 diodes/cm 2 of 100 to 100L; Or more specifically, a wide range of diode densities are available and are within the scope of the present disclosure, including but not limited to 100-100L of 25-50 diodes/cm 2 .

Additional steps or multiple step processes may be used to deposit the diode 100 - 100L over the one or more first conductors 310 . Also, without limitation, a binder such as, but not limited to, a methoxylated glycol ether acrylate monomer (which may also include a water-soluble photoinitiator such as TPO (triphosphene oxide)) or an anisotropic conductive binder is first deposited, followed by 100-100 L of diodes suspended in the liquid or gel discussed above can be deposited.

In an exemplary embodiment, for device 300, 720, 730, 760 aspects, the suspending medium for the diodes 100 to 100K comprises one or more dibasic esters that initially dissolve or rewet a portion of the one or more first conductors 310 and The same dissolution solvent or other reactive reagent may also be included. When a suspension of the plurality of diodes 100 - 100K is deposited and then the surface of the one or more first conductors 310 is partially dissolved or uncured, the plurality of diodes 100 - 100K is slightly within the one or more first conductors 310 or partially buried, which also helps to form an ohmic contact and creates an adhesive bond or adhesive coupling between the plurality of diodes 100 - 100K and the one or more first conductors 310 . When the dissolving or reactive reagent is dissipated through evaporation or the like, the one or more first conductors 310 are re-solidified (or re-cured) in substantially contact with the plurality of diodes 100 to 100K. In addition to the dibasic esters discussed above, exemplary dissolving, wetting or solvating reagents include, for example, 1-propanol (or isopropanol) in a molar ratio of approximately 1:8 ( or 22:78 by weight propylene glycol monomethyl ether acetate (C ₆ H ₁₂ O ₃ ) (sold by Eastman under the trade name “PM Acetate”), and various dibasic esters, and mixtures thereof; For example, dimethyl succinate, dimethyl adipate and dimethyl glutarate (these are from Invista under the trade names DBE, DBE-2, DBE-3, DBE-4, DBE-5, DBE-6, DBE-9 and DBE- available as various mixtures under IB). In an exemplary embodiment, DBE-9 is used. The molar ratio of solvents will vary based on the solvents selected, with 1:8 and 1:12 being typical ratios. Various compounds or other reagents may also be used to control this reaction, for example, a combination or mixture of 1-propanol and water may cause the various compounds of the diode ink to evaporate or dissipate relatively later in the curing process so that the diode Dissolution or rewetting of the one or more first conductors 310 by DBE-9 can be explicitly suppressed by DBE-9 until the thickness of the ink becomes smaller than the height of the diode 100 to 100K, so that any dissolved dissolution of the first conductor 310 can be material (eg, silver ink resin and silver ink particles) may be prevented from being deposited over the top surface of the diodes 100 - 100K (which may then form electrical contact with the second conductor(s) 320 ) ).

Dielectric Ink Example 1:

a dielectric resin comprising from about 0.5% to about 30% methylcellulose resin;

a first solvent comprising an alcohol; and

Surfactants

A composition comprising a.

Dielectric Ink Example 2:

a dielectric resin comprising from about 4% to about 6% methylcellulose resin;

a first solvent comprising from about 0.5% to about 1.5% octanol;

a second solvent comprising from about 3% to about 5% IPA; and

Surfactants

A composition comprising a.

Dielectric Ink Example 3:

about 10% to about 30% dielectric resin;

a first solvent comprising glycol ether acetate;

a second solvent comprising a glycol ether; and

third solvent

A composition comprising a.

Dielectric Ink Example 4:

about 10% to about 30% dielectric resin;

a first solvent comprising about 35% to 50% ethylene glycol monobutyl ether acetate;

a second solvent comprising about 20% to 35% dipropylene glycol monomethyl ether; and

a third solvent comprising about 0.01% to 0.5% toluene

A composition comprising a.

Dielectric Ink Example 5:

about 15% to about 20% dielectric resin;

a first solvent comprising about 35% to 50% ethylene glycol monobutyl ether acetate;

a second solvent comprising about 20% to 35% dipropylene glycol monomethyl ether; and

a third solvent comprising about 0.01% to 0.5% toluene

A composition comprising a.

Dielectric Ink Example 6:

about 10% to about 30% dielectric resin;

a first solvent comprising about 50% to 85% dipropylene glycol monomethyl ether; and

a second solvent comprising about 0.01% to 0.5% toluene

A composition comprising a.

Dielectric Ink Example 7:

about 15% to about 20% dielectric resin;

a first solvent comprising about 50% to 90% ethylene glycol monobutyl ether acetate; and

a second solvent comprising about 0.01% to 0.5% toluene

A composition comprising a.

Dielectric Ink Example 8:

about 15% to about 20% dielectric resin;

a first solvent comprising about 50% to 85% dipropylene glycol monomethyl ether; and

the balance comprising a second solvent comprising about 0.01% to 8.0% propylene glycol or deionized water

A composition comprising a.

An insulating material (referred to as dielectric ink, such as those described as dielectric ink Examples 1-8) is then applied to the diode 100 prior to deposition of the second conductor(s) 320, for example through a printing or coating process. Deposited over peripheral or lateral portions of the 100-100L or diode 100-100L to form an insulating or dielectric layer 315. The dielectric layer 315 has a wet film thickness of about 30 to 40 μm, and a dried or cured film thickness of about 5 to 7 μm. The insulating or dielectric layer 315 may be comprised of any of insulating or dielectric compounds suspended in any of a variety of media as discussed above and below. In an exemplary embodiment, the insulating or dielectric layer 315 comprises from about 0.5% to 15%, or more specifically from about 1.0% to about 8.0%, or more specifically from about 3.0% to about 6.0%, or more specifically A methylcellulose resin in an amount ranging from about 4.5% to about 5.5%, for example E-3 "methocel" available from Dow Chemical, from about 0.1% to 1.5%, or more specifically from about 0.2% from about 0.01% to about 1.0%, or more specifically from about 0.01% to about 0.5% BYK 381 from BYK Chemie GmbH, in an amount ranging from about 0.4% to about 0.6%. 0.5%, or more specifically about 0.05% to about 0.25%, or more specifically about 0.08% to about 0.12% of a first solvent, such as about 0.1% octanol, and about 0.0% a second solvent in an amount ranging from about 8% to 8%, or more specifically from about 1.0% to about 7.0%, or more specifically from about 2.0% to about 6.0%, or more specifically from about 3.0% to about 5.0%, For example, about 4% IPA, and the balance in a suspension of a third solvent, such as deionized water. With the E-3 formulation, 4 to 5 coatings are deposited to produce an insulating or dielectric layer 315 having a total thickness of 6 to 10 μm, each coating cured at about 110° C. for about 5 minutes. In other exemplary embodiments, the dielectric layer 315 may be IR (infrared) cured, uv cured, or both. Also, in other exemplary embodiments, different dielectric formulations may be applied as different layers to form the insulating or dielectric layer 315, including, but not limited to, obtained from Henkel Corporation, Dusseldorf, Germany. After applying a first layer of a possible solvent-based transparent dielectric such as Henkel BIK-20181-40A, Henkel BIK-20181-40B, and/or Henkel BIK-20181-24B, the above-described water-based E-3 formulation is applied. applied to form a dielectric layer 315. In other exemplary embodiments, other dielectric compounds are commercially available from Henkel, and they may be equally used as in dielectric ink Example 8. The dielectric layer 315 may be transparent, but may contain relatively low concentrations of light diffusive, scattering or reflective particles, as well as thermally conductive particles such as, but not limited to, aluminum oxide. In various exemplary embodiments, the dielectric ink is also dewetted from the top surface of the diodes 100-100L to (depending on the orientation) first terminal 125 or at least a portion of the second, backside of the diodes 100-100K to a second conductor will be left exposed for subsequent contact with (s) 320.

Exemplary one or more solvents such as, but not limited to, water; Alcohols such as methanol, ethanol, N-propanol (including 1-propanol, 2-propanol (isopropanol), 1-methoxy-2-propanol), isobutanol, N-butanol (1-butanol, 2- butanol), N-pentanol (including 1-pentanol, 2-pentanol, 3-pentanol), N-octanol (including 1-octanol, 2-octanol, 3-octanol) ; ethers such as methyl ethyl ether, diethyl ether, ethyl propyl ether, and polyethers; esters such as ethyl acetate, dimethyl adipate, propylene glycol monomethyl ether acetate, dimethyl glutarate, dimethyl succinate, glycerin acetate, dibasic esters (eg Invista DBE-9); esters such as ethyl acetate; glycols such as ethylene glycol, diethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol, glycol ether, glycol ether acetate, PM acetate (propylene glycol monomethyl ether acetate), dipropylene glycol monomethyl ether, ethylene glycol monobutyl ether acetate; carbonates such as propylene carbonate; glycerol such as glycerin; acetonitrile, tetrahydrofuran (THF), dimethyl formamide (DMF), N-methyl formamide (NMF), dimethyl sulfoxide (DMSO); and mixtures thereof may be used in the exemplary dielectric inks. In addition to the water-soluble resin, other solvent-based resins may also be used. one or more thickening agents, for example clays such as hectorite clays, garamite clays, organo-modified clays; saccharides and polysaccharides such as guar gum, xanthan gum; Cellulose and modified celluloses such as hydroxy methylcellulose, methylcellulose, ethyl cellulose, propyl methylcellulose, methoxy cellulose, methoxy methylcellulose, methoxy propyl methylcellulose, hydroxy propyl methylcellulose, carboxymethylcellulose, hydroxy ethylcellulose, ethyl hydroxyl ethylcellulose, cellulose ether, cellulose ethyl ether, chitosan; polymers such as acrylate and (meth)acrylate polymers and copolymers, polyvinyl pyrrolidone, polyethylene glycol, polyvinyl acetate (PVA), polyvinyl alcohol, polyacrylic acid, polyethylene oxide, polyvinyl butyral (PVB); Diethylene glycol, propylene glycol, 2-ethyl oxazoline, fumed silica (eg Cabosil), silica powder and modified urea such as BYK® 420 (available from BYK Chemie) can be used Other viscosity modifiers, as described in US Patent Application Publication 2003/0091647 (Lewis et al.), as well as particle additives for viscosity control may be used. Flow aids or surfactants such as octanol and Emerald Performance Materials Foamblast 339 may also be used. In other exemplary embodiments, the at least one insulator 135 may be a polymer, such as typically comprising less than 12% PVA or PVB in deionized water.

After deposition of the insulating or dielectric layer 315, one or more second conductor(s) 320, which may be any type of conductor, conductive ink or polymer discussed above, or an optically transmissive (or transparent) conductor (eg exposed or uninsulated portions of the diodes 100-100L (typically a first for diodes 100-100L in a first orientation) by depositing (eg, via printing of a conductive ink, polymer, or other conductor such as a metal). It forms an ohmic contact with terminal 125). The one or more optically transmissive second conductor(s) 320 has a wet film thickness of about 6-18 μm and a dried or cured film thickness of about 0.1-0.4 μm, and the one or more optically opaque second conductor(s) 320 (eg, Acheson 725A conductive silver) generally has a wet film thickness of about 14 to 18 μm and a dried or cured film thickness of about 5 to 8 μm. For example, the optically transmissive second conductor may be deposited as a single continuous layer (forming a single electrode), for example for lighting or photovoltaic applications. In the case of the reverse fabrication mentioned above, in the device 700 aspect, the second conductor(s) 320 may be optically transmissive, although this is not required, which is the case for devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, Allow light to be introduced or emitted from both the top and bottom surfaces of the 730, 740, 750, 760, and 770. The optically transmissive second conductor(s) 320 may (1) have sufficient conductivity to excite or receive energy from the first or upper portions of the device 300 (and generally, power as may be necessary or desirable) have a sufficiently low resistance or impedance to reduce or minimize losses and heat generation); (2) for example, for portions of the visible spectrum, any compound having at least a predetermined or selected level of transparency or transmission to electromagnetic radiation of the selected wavelength(s). The selection of materials for forming the optically transmissive or opaque second conductor(s) 320 may depend on the selected application of the devices 300 and 700 and the utility of any one or more third conductors. One or more second conductor(s) 320 are known or may be known in the printing or coating art while providing appropriate control for any selected alignment or registration, for example as may be necessary or desirable. By using a printing or coating process, it is deposited over the exposed and/or non-insulated portions of the diodes 100-100L and/or over any of the insulating or dielectric layer 315.

For example, an exemplary transparent conductive ink used to form the one or more second conductors 320 is about 0.4-3.0% (or more in other aspects) silver nanofibers, polyvinyl pyrrolidone (1,000,000 MW) about 2-4%, 0.5-2% ice-cold acetic acid, the balance being 1-butanol and/or cyclohexanol.

In an exemplary embodiment, in addition to the conductors described above, carbon nanotubes (CNTs), nanoparticles or nanofibers silver, polyethylene-dioxythiophene (eg, AGFA Orgacon), poly-3,4-ethylenedioxythiophene and blends of polystyrenesulfonic acids (sold as Baytron P and available from Bayer AG, Leverkusen, Germany), polyaniline or polypyrrole polymers, indium tin oxide (ITO) and/or antimony tin oxide (ATO) ( Typically ITO or ATO suspended as particles in any of the various binders, polymers or carriers discussed above) may be used to form the optically transmissive second conductor(s) 320 . In an exemplary embodiment, carbon nanotubes are suspended in a volatile liquid with a surfactant, such as a carbon nanotube composition available from SouthWest NanoTechnologies, Inc. of Norman, Oklahoma, USA. . Additionally, one or more third conductors (not separately illustrated) having a relatively lower impedance or resistance are incorporated into or may be incorporated into the corresponding transparent second conductor(s) 320 . Conductive ink or polymer (e.g., silver ink, CNT or polyethylene-deoxythiophene) printed over the corresponding compartment or layer of the permeable second conductor(s) 320, for example to form one or more third conductors polymers) may be used to form one or more fine wires, or conductive inks or polymers printed over the larger integral transparent second conductor(s) 320 in large displays (e.g., grids) or has a ladder pattern).

Other compounds that may equally be used to form the substantially optically transmissive second conductor(s) 320 include indium tin oxide (ITO) as mentioned above, the conductive polymers discussed above, such as those obtained under the trade designation "Orgacon". Included are other transmissive conductors currently known or may be known in the art, including possible polyethylene-dioxythiophenes and various carbon and/or carbon nanotube based transparent conductors. Representative transparent conductive materials are available from DuPont, such as, for example, 7162 and 7164 ATO translucent conductors. The transmissive second conductor(s) 320 may also be used in combination with various binders, polymers or carriers, including those discussed above, for example, binders that can be cured under various conditions such as exposure to ultraviolet radiation (UV curable). have.

An optional stabilizing layer 335 may be deposited over the second conductor(s) 320 as may be necessary or desirable, for example a light emitting (or light emitting) layer 325 or any intervening conformal coatings may be applied to the second conductor ( s) is used to protect the second conductor(s) 320 from degrading the conductivity of the 320 . A relatively thin coating of one or more of the inks, compounds or coatings discussed below (with respect to protective coating 330), for example an infrared curable such as Nazdar 9727 transparent substrate or DuPont 5018 or about 7% polyvinylbutyral in cyclohexanol. Resins may be used. Additionally, heat dissipating and/or light scattering particles may optionally be included in the stabilization layer 335 . Exemplary stabilizing layers are typically about 10-40 μm in dried or cured form.

Optionally, carbon electrode 322 (illustrated as 322A and 322B) is sealed or sealed to one or more first conductors 310 and one or more second conductor(s) 320 as illustrated for various exemplary aspects. It can be used to form contacts outside the protective layer 330 and helps to protect the one or more first conductors 310 and the one or more second conductor(s) 320 from corrosion and wear. In an exemplary embodiment, a carbon ink such as Acheson 440A having a wet film thickness of about 18-20 μm and a dry or cured film thickness of about 7-10 μm is used.

Also, as an option illustrated in FIGS. 102 and 103 , any third conductive layer 312 may be used, which is described herein for one or more first conductors 310 and/or one or more second conductor(s) 320 . may include any of the conductive materials described in

One or more light emitting (or light emitting) layers 325 (including, for example, one or more phosphor layers or coatings) may be deposited over stabilizing layer 335 (or over second conductor(s) 320 if stabilizing layer 335 is not used). or it may be deposited directly on the second side of the substrate 305A for the device 700 aspect. A plurality of light emitting (or light emitting) layers 325 may also be used, such as on both sides of devices 300, 300A, 300C, 300D, 700, 700A, 720, 730, 740, 750, 760, 770, as illustrated. . In exemplary embodiments, such as the LED embodiment, the one or more light emitting layers 325 may be applied over the entire surface of the stabilization layer 335 (or stabilization layer 335 for the device 300 embodiment, for example, but not limited to, via the printing or coating process discussed above). may be deposited on the second conductor(s) 320 if not used, or directly on the second side of the substrate 305A for the device 700 aspect, or both. The one or more light emitting layers 325 are capable of or are adapted to emit light in the visible spectrum in response to light (or other electromagnetic radiation) emitted from diodes 100 - 100L, or emitted light (or other at any selected frequency). It may be formed of any material or compound capable of or tuned to shift (eg, stroke shift) the frequency of electromagnetic radiation). For example, a yellow phosphor-based light emitting layer 325 can be used with blue light emitting diodes 100 - 100L to produce substantially white light. These luminescent compounds include a variety of phosphors, which may be provided in any of a variety of forms with any of a variety of dopants. The luminescent compounds or particles forming the one or more luminescent layers 325 may be used or suspended in the form of a polymer having various binders, and also various binders (eg, DuPont or Conductive Compounds). may be used separately in combination with phosphor binders available from ) to aid in printing or other deposition processes and to provide adhesion of the phosphor to the base layer and subsequent top layers. The one or more light-emitting layers 325 may also be provided in uv-curable or heat-curable form.

(1) G1758, G2060, G2262, G3161, EG2762, EG 3261, EG3560, EG3759, Y3957, EY4156, EY4254, EY4453, EY4651, EY4750, O5446, available from Intematix, Fremont, CA. O5544, O5742, O6040, R630, R650, R6733, R660, R670, NYAG-1, NYAG-4, NYAG-2, NYAG-5, NYAG-3, NYAG-6, TAG-1, TAG-2, SY450- A, SY450-B, SY460-A, SY460-B, OG450-75, OG450-27, OG460-75, OG460-27, RG450-75, RG450-65, RG450-55, RG450-50, RG450-45, RG450-40, RG450-35, RG450-30, RG450-27, RG460-75, RG460-65, RG460-55, RG460-50, RG460-45, RG460-40, RG460-35, RG460-30, and RG460 -27; (2) 13C1380, 13D1380, 14C1220, and GG-84 available from Global Tungsten & Powders Corp. of Towanda, PA, USA; (3) FL63/S-D1, HPL63/F-F1, HL63/S-D1, QMK58/F-U1, QUMK58/F-D1 available from Phosphor Technology Ltd., Hertz, UK. , KEMK63/F-P1, CPK63/N-U1, ZMK58/N-D1, and UKL63/F-U1; (4) BYW01A/PTCW01AN, BYW01B/PTCW01BN, BUVOR02, BUVG01, BUVR02, BUVY02, BUVG02, BUVR03/PTCR03, and BUVY03 available from Phosphor Tech Corp., Lithia Springs, GA; and (5) Hawaii655, Maui535, Bermuda465, and Bahama560 available from Lightscape Materials, Inc. of Princeton, NJ, USA. Compounds are available and are within the scope of this disclosure. Additionally, colorants, dyes and/or dopants may be included in any such light emitting (or light emitting) layer 325 depending on the selected aspect. In an exemplary embodiment, a yttrium aluminum garnet ("YAG") phosphor available from Phosphor Technology Ltd and Global Tungsten & Powders Corporation, e.g., 40% YAG in a uv curable resin (about 40-100 μm wet and dry/ having a cured film thickness), or 70% YAG in an infrared curable resin-solvent system, such as about 5% polyvinylbutyral in about 95% cyclohexanol (wet film thickness of about 15-17 μm and about 13- has a dry/cured film thickness of 15 mu m) is used. Additionally, the phosphor or other compounds used to form the emissive layer 325 may include dopants that emit light in a particular spectrum, such as green or blue. In these cases, the emissive layer may be printed to define pixels for any given or selected color, such as RGB or CMYK, to provide a color display. Those of skill in the art will recognize that any of the device 300 aspects may also include a stabilizing layer 335 or one or more such light emitting layers 325 coupled to or deposited on the second conductor(s) 320 .

Depending on the solvents used to form the one or more second conductor(s) 320 , as illustrated in FIG. 103 , for example, compounds of one or more second conductor(s) 320 may pass through dielectric layer 315 . To prevent penetration through the one or more first conductors 310, any one or more barrier layers 318 may be used. In an exemplary embodiment, a viscosity modifier, such as an E-10 viscosity modifier or any of the other viscosity modifiers discussed above, is used, deposited to form a cured or dried film or membrane thickness of about 100-200 nm. Any of the materials used to form the protective or sealing coating 330 or the stabilizing layer 335 may also be used to form the one or more barrier layers 318 .

Device 300 may also include an optional protective or sealing coating 330 (which may be combined with any stabilizing layer 335), which may also include for protection from various factors such as weather, airborne corrosives, etc.; It may include any type of lanceting or light diffusing or dispersing structure or filter, such as a substantially transparent plastic or other polymer, or such sealing and/or protective function may include a polymer (resin or other binder) used with the light emitting layer 325 . can be provided by For ease of illustration, Figures 76, 78-82, 87, 88, 91-98, 102, and 103 show such polymers (resin or other binders) forming a protective or sealing coating 330 with dashed lines to indicate substantial transparency. shown using In an exemplary embodiment, the protective or sealing coating 330 uses a proprietary resin available as NAZDAR 9727 (www.nazdar.com) or a urethane-based material such as uv curable urethane acrylate PF 455 BC available from Henkel Corporation, Dusseldorf, Germany. and deposited as one or more conformal coatings to a thickness of about 10 to 40 μm. In another exemplary embodiment, the protective or sealing coating 330 is formed by laminating the device 300 . Although not specifically illustrated, related U.S. patent applications (U.S. Patent Application Serial No. 12/560,334, U.S. Patent Application No. 12/560,340, U.S. Patent Application No. 12/560,355, U.S. Patent Application No. 12/560,364, and U.S. Patents Suspended in a plurality of lenses (polymer (resin or other binder) as discussed in Application No. 12/560,371, the entire contents of which are incorporated herein by reference with the same effect as set forth in their entirety) ) may also be deposited directly over the one or more light emitting layers 325 and other features, creating any of a variety of light emitting device 300 aspects.

Those skilled in the art will recognize that any number of first conductors 310, insulators 315, second conductors 320, etc. may be used within the scope of the claimed invention. Additionally, in addition to the orientations illustrated, for any device 300, a first plurality of conductors 310, one or more insulator (or dielectric layer) 315, and a second plurality of conductor(s) 320 (any incorporation) There can be a wide variety of orientations and configurations (with corresponding optional one or more third conductors), for example substantially parallel orientations. For example, a first plurality of conductors 310 may all be substantially parallel to each other, and a second plurality of conductor(s) 320 may also be all substantially parallel to each other. Again, the first plurality of conductors 310 and the second plurality of conductor(s) 320 may be perpendicular to each other (defining a row and a column) such that their overlapping area is a pixel (" pixel"), and can be addressed separately and independently. If either or both of the first plurality of conductors 310 and the second plurality of conductor(s) 320 can be implemented as spaced apart and substantially parallel lines having a predetermined width (both forming a row or both define columns), they may also be addressed by row and/or column, such as, but not limited to, sequential addressing of consecutive rows. Additionally, either or both of the first plurality of conductors 310 and the second plurality of conductor(s) 320 may be implemented as a layer or sheet as mentioned above.

As will be apparent from the present disclosure, the exemplary devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 have a selection of composite materials, such as substrate 305. Thus, it can be designed and manufactured to be highly flexible and deformable, not rigid, and potentially even collapsible, stretchable and potentially wearable. For example, exemplary devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 are flexible, foldable and wearable garments, or flexible lamps, or wallpapers. It may include a lamp. Because of this flexibility, the example devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 can be rolled up like a poster, or folded like a piece of paper. and is fully functional when reopened. Also, for example, due to this flexibility, exemplary devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 can have a variety of shapes and sizes, and It can be configured for a wide range of styles and other aesthetic purposes. These exemplary apparatuses 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 are also significantly more resilient than prior art devices, such that, for example, Much less fragile and less fragile than screen televisions.

As noted above, the plurality of diodes 100 - 100L may be configured to be a photovoltaic (PV) diode or LED, for example and without limitation (via material selection and corresponding doping). 84 is a block diagram of an aspect of a first exemplary system 350 in which a plurality of diodes 100 - 100L are implemented as LEDs of any type or color. System 350 includes a light emitting device 300A, 300C, 300D, 300C, 300D, 700A (and any of devices 720, 730, 740, 750, 760, 770 in which the diode is an LED), a power source 340 (eg, an AC line or an interface circuit 355, which can be coupled to a DC battery), and optionally a controller 345 (with a control logic circuit 360 and optionally a memory 365). (Device 300A is otherwise generally the same as device 300, but with a plurality of diodes 100-100L implemented as LEDs, and for device 300C, 300D aspects, double-sided, similarly, device 700A is otherwise generally identical to device 700 but with a plurality of diodes 100 to 100L implemented as LEDs). When one or more first conductors 310 and one or more second conductor(s) 320 (or third conductor 312 ) are energized, for example via application of a corresponding voltage (eg, voltage from power source 340 ). , exclusively through devices 300A, 300C, 300D, 300C, 300D, 700A, 720, 730, 740, 750, 760, 770, or through an energized first conductor 310 and second conductor, if said conductor and insulator are each implemented as a single layer At the corresponding intersection (region of overlap) of the two conductor(s) 320, one or more of the plurality of LEDs (diodes 100 to 100L) will be energized, which, depending on their orientation and configuration, for example a pixel; Define sheets, or rows/columns. Accordingly, by selectively exciting the first conductor 310 and the second conductor(s) 320 , the device 300A (and/or the system 350 ) provides a pixel-addressable dynamic display or lighting device or signage or the like. For example, a first plurality of conductors 310 may include a corresponding plurality of rows, and a second plurality of transmissive conductor(s) 320 may include a corresponding plurality of columns, a corresponding row and a corresponding plurality of columns. Each pixel is defined by an intersection or overlap of columns. Also, for example, either or both of the first plurality of conductors 310 and the second plurality of conductor(s) 320 may be as illustrated in FIGS. 76-82, 87, 88, 91-98, 102, 103 When practicable together, the excitation of conductors 310, 320 is applied to substantially all (or most) a plurality of LEDs (diodes 100 to 100L) to provide light emission for a fixed display such as, for example, a lighting device or signage. will provide power. These pixel counts can be much higher than typical high definition levels.

With continued reference to FIG. 84 , devices 300A, 300C, 300D, 300C, 300D, 700A, 720, 730, 740, 750, 760, 770, via interface circuit 355, are connected to a DC power source (eg, battery or solar photovoltaic cell) or an AC power source (eg, household or building power), and optionally also to a controller 345 . The interface circuit 355 can be implemented in a wide variety of ways, such as, but not limited to, a full-wave or half-wave rectifier, an impedance matching circuit, a capacitor to reduce DC ripple, a switching power supply for coupling to an AC line, and the like, including, but not limited to, a diode. It may include a wide range of elements (not separately illustrated) for controlling the excitation of 100 to 100L. When controller 345 is implemented, as is the case with the addressable light emitting display system 350 aspect and/or the dynamic light emitting display system aspect 350 aspect, the controller 345 may be configured to include (a first plurality of may be used to control the excitation of the diode 100-100L (via conductors 310 and a plurality of transmissive second conductor(s) 320), typically a control logic circuit 360 (which may be a combinational logic circuit, a finite state machine, a processor, etc.) ) and memory 365. Other input/output (I/O) circuitry may also be used. When controller 345 is not running, as in the case of various lighting system 350 aspects (which are typically non-addressable and/or non-dynamic luminous display system 350 aspects), the system 350 turns on and/or turns on the lighting system, for example. For turning off and/or dimming, it is typically coupled to an electrical or electronic switch (not separately illustrated) which may include any suitable type of switching arrangement. Control logic circuit 360, memory 365, is discussed in more detail below, following the discussion of FIGS. 100-103, 85 and 86.

Interface circuit 355 is known or may be implemented as known in the art, and includes impedance matching capacitance, voltage rectification circuitry, eg voltage conversion for connecting a low voltage processor with a high voltage control bus, the control logic circuit 360 various switching mechanisms (eg, transistors) for turning various lines or connectors on or off in response to a signal from, and/or physical coupling mechanisms. Additionally, the interface circuitry 355 may also accept and/or transmit signals externally to the system 350 in question, for example via hard-wiring or RF signaling, accept information in real time, for example to control a dynamic display, or , can also be adjusted, for example, to control (dimming) the brightness of the light output. The interface circuit 355A may be a standalone device (e.g., modular) and may be reused, for example, with devices 760, 770 configured to be snapped, screwed, locked, or coupled to the interface circuit 355A, for example. The interface circuit 355A may be used repeatedly over time with a number of alternative devices 760 and 770 .

For example, as illustrated in FIG. 100 , exemplary system aspects 800 , 810 may be a device 760 (when implemented using diodes 100-100K) or device 770 (when implemented using diodes 100-100K) wherein the plurality of diodes 100-100L are light emitting diodes. when implemented using a diode 100L), and an interface circuit 355 for fitting any of a variety of standard Edison sockets for lighting bulbs. Continuing and without limitation in this embodiment, the interface circuit 355 may be configured with one or more of the standardized screw configurations, such as an E12, E14, E26, and/or E27 screw base standard, such as a medium screw base (E26). or candelabra screw base (E12), and/or sized and shaped to conform to various other standards promulgated by the American National Standards Institute (“ANSI”) and/or the Lighting Engineering Society. In other exemplary aspects, the interface circuit 355 may be sized and shaped to conform to a two plug base, such as, but not limited to, a standard fluorescent light bulb socket or a GU-10 base. This exemplary system aspect may be considered equivalent as another type of device, for example and without limitation, particularly if it has a form factor compatible for insertion into an Edison or fluorescent socket.

For example, an LED-based "light bulb" may include, but is not limited to, any power socket type, eg, L1, PL-2 pin, PL-4 pin, G9 halogen capsule; Portion of an interface circuit 355, such as ES, E27, SES, or E14, that can be adapted to connect with a G4 halogen capsule, GU10, GU5.3, bayonet, miniature bayonet, or any other connection known in the art. It can be formed to have a design similar to that of a conventional incandescent light bulb, with a screw-type connection.

Devices 300A, 300C, 300D, 700 and first system 350 include light bulbs and tubes, lamps, lighting fixtures, indoor and outdoor lighting, lamps configured to have a lampshade form factor, architectural lighting, work or craft lighting, decorative or mood A lighting, a ceiling light, a safety light, a dimmable light, a color light, a performance and/or variable color light, a display light, and a light having any of the various decorative or fantastic forms mentioned herein, comprising a plurality of It can be used to form a wide range of lighting devices or other lighting products for this purpose. Although not specifically illustrated, the first system 350 will generally also include various mechanical structures to provide sufficient physical support of the devices 300A, 300C, 300D in any desired shape or configuration in the system 350.

Referring to FIG. 100 , an exemplary system 800 includes a device 760 and an interface circuit 355A, and an exemplary system 810 includes a device 770 and an interface circuit 355A. The interface circuit 355A is configured to fit into a standard Edison light bulb screw-type socket for coupling to a standard AC power source, such as an AC mains (not separately illustrated). This interface circuit 355A will typically include a rectifying circuit for converting an AC voltage to a DC voltage, and also an impedance matching circuit and various may include capacitors and/or resistors (and switches often implemented using transistors). 102 and 103, device 760 is comprised of a plurality of diodes 100-100K, whereas device 770 is comprised of a plurality of diodes 100L, and as discussed above and discussed in more detail below, device There are corresponding differences in structure and materials. 100 also shows exemplary devices 300, 300A, 300B, 300C, 300D, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 bent and folded into a fantastic decorative form. provides an example of a very thin and flexible form factor of

101 is a plan view illustrating the printed layout of devices 760 and 770; As illustrated, devices 760, 770 are printed as flat sheets with very thin form factors and then die cut in region 716 to form relatively narrow lamp strips 717 (coupled in series, as described above). An electrode (illustrated as carbon electrodes 322A, 322B) is provided at each end. Then, as illustrated in FIG. 100 , the devices 760 and 770 are rolled up, the ends 718 of the lamp strips 717 are brought together to overlap each other in a circle, and the electrodes 322A and 322B is connected, and the lamp strips 717 are slightly separated from each other.

102 , a device 760 is similar to the other illustrated devices and has two layers, namely, one or more third conductors 312 (which may also include any of the transparent or non-transparent conductive inks and compounds discussed herein). 315A), and an additional dielectric layer between the one or more third conductors 312 and the one or more first conductors 310 (to distinguish it from other dielectric layers illustrated as 315B) ) is further added. One or more third conductors 312 are used to provide power (eg, voltage levels) along the edge of lamp strip 717, and one or more second conductors that may be deposited as a layer of transparent conductive material as discussed above. coupled to 320 and effectively functioning as parallel busbars along the length of each lamp strip 717, while providing a method of reducing the overall impedance, current level and power consumption of the device 760.

103, device 770 is similar to the other illustrated devices, and has three layers: (1) one or more third conductors 312 (which are also transparent or non-transparent conductive inks and compounds discussed herein) may be deposited as a single layer using any of these); (2) an additional dielectric layer between the one or more third conductors 312 and the one or more first conductors 310 (illustrated as 315A to distinguish it from other dielectric layers illustrated as 315B); and (3) one or more barrier layers 318 as mentioned above, deposited between the dielectric layer 315B and the one or more second conductors 320 . One or more third conductors 312 are used to provide power (eg, a voltage level) along the edge of the lamp strip 717, are coupled to the one or more first conductors 310, and further extend the length of each lamp strip 717 Accordingly, it provides a method of reducing the overall impedance, current level and power dissipation of the device 770 while effectively functioning as a parallel busbar.

Various levels of light output can be provided by the devices 300A, 300C, 300D, 300C, 300D, 700A, 720, 730, 740, 750, 760, 770, which are the concentrations of the diodes 100 to 100L used, the first system based on the number of devices 300A, 300C, 300D, 300C, 300D, 700A, 720, 730, 740, 750, 760, 770 used in the 350, the selected or permitted power consumption, and the applied voltage and/or current level It will be different. In an exemplary aspect, a device 300A, 300C, 300D, 300C, 300D, 700A, 720, 730, 740, 750, 760, 770 may include, but is not limited to, power consumption, a concentration or density of 100 to 100 L of diodes, a diode Depending on the current level of 100-100L (ie, the intensity at which the diode 100-100L is driven), the overall impedance level, etc., it may provide an optical output in the range of about 25-1300 lumens.

As noted above, the plurality of diodes 100 - 100L may be configured (via material selection and corresponding doping) to be photovoltaic (PV) diodes. 85 is a block diagram of an aspect of a second exemplary system 375 in which diodes 100-100L are implemented as photovoltaic (PV) diodes. System 375 is similar to device 300B, 700B (which is otherwise generally device 300, 700 (or any of the other illustrated devices), but includes a plurality of diodes 100-100L implemented as photovoltaic (PV) diodes. ), and either or both of an energy storage device 380 such as a battery or an interface circuit 385 (not separately illustrated) such as a battery for delivering power or energy to another system, for example, an electric device or an electric utility. do. (In other exemplary aspects that do not include interface circuitry 385, other circuit configurations may be used to provide energy or power directly to such an energy-using device or system or an energy-distributing device or system). coupling one or more first conductors 310 (or electrode 322A) of 300B, 700B to form a first terminal (eg, negative or positive terminal), and one or more second conductor(s) of device 300B, 700B ) 320 (or electrode 322B) to form a second terminal (eg, a corresponding positive or negative terminal) and then connect them to either or both of the energy storage device 380 or the interface circuit 385 can be coupled for When light (eg, sunlight) is incident on the devices 300B, 700B, the light may be focused on one or more photovoltaic (PV) diodes 100-100L, which in turn converts incident photons into electron-hole pairs. invert to produce an output voltage generated across the first and second terminals, and an output to either or both of the energy storage device 380 or the interface circuit 385.

Where the first conductor 310 has the interdigitated or comb-like structure illustrated in FIG. 77 , the second conductor 320 can be energized using the first conductor 310B, or similarly, the voltage generated is applied to the first conductors 310A and 310B. It should be noted that it can be accommodated across

86 is a flow chart illustrating exemplary method embodiments of devices 300, 300A, 300B, 300C, 300D, 700, 700A, 700B, 720, 730, 740, 750, 760, 770 and provides a useful overview. Starting from a starting step 400 , one or more first conductors 310 are deposited onto a substrate 305 , for example, depending on the implementation, by printing a conductive ink or polymer or by applying the substrate 305 to one or more substrates. After deposition, sputtering or coating with metal, the conductive ink or polymer is cured or partially cured, or the deposited metal is removed from potentially unwanted locations (step 405). A plurality of diodes 100 to 100L, which is then typically suspended in a liquid, gel or other compound or mixture (eg, suspended in diode ink), and which may also include a plurality of inert particles 292, is also typically Deposited over the one or more first conductors via printing or coating (step 410) to form an ohmic contact between the plurality of diodes 100-100L and the one or more first conductors (which may also be for example may include, but are not limited to, various chemical reactions, compression and/or heating). For the apparatus 700 aspect, steps 405 and 410 are performed in reverse order as discussed above.

Then, a dielectric or insulating material, such as a dielectric ink, is deposited (also cured or heated) over or around the plurality of diodes 100-100L, for example around the perimeter of the diodes 100-100L (step 415); One or more insulator or dielectric layers 315 are formed. For the device 760 aspect, although not separately illustrated, one or more third conductors 312 and dielectric layers 315A may be deposited in steps 405 and 415, followed by further steps 405 and 410 . For the device 770 aspect, although not separately illustrated, a barrier layer 318 may also be deposited. Next, one or more second conductors 320 (which may or may not be optically transmissive) are placed over the plurality of diodes 100 to 100L, for example over the dielectric layer 315 and on top of the diodes 100 to 100L. It is deposited around a surface to form a contact and hardened (or heated) (step 420 ) to also form an ohmic contact between the one or more second conductors 320 and the plurality of diodes 100 - 100L. In exemplary aspects, such as an addressable display, the second plurality of (transmissive) conductors 320 are oriented substantially perpendicular to the first plurality of conductors 310 . For the device 770 aspect, although not separately illustrated, the dielectric layer 315A may be deposited in step 415 followed by the deposition of one or more third conductors 312 in step 405 .

As another option, prior to or during step 420, a test may be performed to remove or disable non-functional or defective diodes 100-100L. For example, in the case of PV diodes, when the surface (first side) of a partially finished device is scanned with a laser or other light source, and the area (or individual diodes 100 to 100L) does not provide the expected electrical response, It can be removed using high-intensity lasers or other ablation techniques. Also, for example, in the case of a powered light-emitting diode, the surface (first side) is scanned with a photosensor, the area (or individual diodes 100-100L) not providing the expected light output and/or excessive current When drawing (ie, a current in excess of a predetermined amount), it can also be removed using high intensity lasers or other ablation techniques. Depending on the implementation, for example, depending on how the non-functioning or defective diodes 100-100L are removed, this test step may instead be performed after steps 425, 430 or 435 discussed below. A stabilizing layer 335 is then deposited over the one or more second conductors 320 or other layer as illustrated for the various devices (step 425), followed by a light emitting layer 325 over the stabilizing layer (step 430). In a device 700 aspect, the layer 325 is typically deposited over the second side of the substrate 305A, as noted above. A plurality of lenses (not separately illustrated), also typically suspended in a polymer, binder, or other compound or mixture, to form a lensing or lens particle ink or suspension, are then placed over said light emitting layer or A preformed lens panel comprising a plurality of lenses deposited or suspended in a polymer is attached (eg, via a lamination process) to the first side of the partially finished device, followed by a protective coating (and/or selected color) may optionally be deposited (step 355) (eg, via printing) and the method may be terminated (transfer step 440).

Referring again to FIG. 84, the control logic circuit 360 may be any type of controller, processor, or control logic circuit, and may be implemented as one or more processors to perform the functions discussed herein. As used herein, the term processor, processor 360 may include the use of a single integrated circuit (“IC”), or a plurality of integrated circuits or other elements connected, arranged or grouped together, such as a controller; Microprocessors, digital signal processors (“DSPs”), parallel processors, multi-core processors, application specific ICs, application specific integrated circuits (“ASICs”), field programmable gate arrays (“FPGAs”) "), adaptive computing ICs, associated memories (eg, RAM, DRAM and ROM), and other ICs and components. Consequently, the term processor as used herein refers to a single IC, or an application specific IC, ASIC, processor, microprocessor, controller, FPGA, adaptive computing IC, or integrated circuits and associated memory that perform the functions discussed below, e.g. It should be understood to mean and encompass an arrangement of microprocessor memory or some other group of additional RAM, DRAM, SDRAM, SRAM, MRAM, ROM, FLASH, EPROM or E ² PROM equivalently, for example. The processor, along with its associated memory, may be configured (via programming, FPGA interconnection, or hard-wiring) a method of the invention, for example selective pixel addressing in the case of a dynamic display aspect, or row/column in the case of a signage aspect. It can be adjusted or set to perform addressing. For example, the method may include an associated memory (and/or memory 365) and other equivalent elements may be programmed and stored within the processor. Equally, if the control logic circuit 360 may be implemented in whole or in part as an FPGA, application specific IC and/or ASIC, the FPGA, application specific IC or ASIC may also be designed, configured and/or hard-wired to implement the method of the present invention. can be ringed. For example, the control logic circuit 360 may be a processor, controller, microprocessor, DSP, collectively referred to as a “controller” or “processor,” each programmed, designed, adjusted, or configured to carry out the methods of the present invention together with the memory 365. and/or as an arrangement of ASICs.

The control logic circuit 360, together with its associated memory, provides a first plurality of conductors 310 and a second various (via programming, FPGA interconnection, or hard-wiring) for corresponding control over the displayed information. may be configured to control excitation of (applied voltage across) the plurality of conductor(s) 320 (and any one or more third conductors 312 ). For example, static or time-varying display information may be a series of program instructions (or equivalent setup or other programs) for subsequent execution when control logic circuitry 360 operates, including associated memory (and/or memory 365) and other It can be programmed, stored, configured and/or hard-wired in the control logic circuit 360 having equivalent members.

Memory 365, which may include a data store (or database), is, depending on the aspect selected, a memory integrated circuit (“IC”), now known or made available in the future, or RAM, FLASH, DRAM, SDRAM, SRAM , a volatile or non-volatile, removable or non-removable memory portion of an integrated circuit (eg, resident memory within a processor) including, but not limited to, MRAM, FeRAM, ROM, EPROM or E ² PROM, or any other memory device type, such as magnetic hard drive, optical drive, magnetic disk or tape drive, hard disk drive, other machine-readable storage or storage medium such as floppy disk, CDROM, CD-RW, digital versatile disk (DVD ) or other optical memory, or any other type of memory, storage medium, or data storage device or circuitry, any computer or other machine-readable data now known or made available in the future It may be implemented in any number of forms, including storage media, storage devices for information storage or communication, or other storage or communication devices. Additionally, such computer readable media includes any information delivery medium capable of encoding data or other information in a wired or wireless signal, including electromagnetic signals, optical signals, audio signals, RF signals or infrared signals, and the like. includes any form of communication medium embodying computer readable instructions, data structures, program modules or other data in a data signal or modular signal, such as an electromagnetic or optical carrier wave or other transport mechanism. Memory 365 may be adapted to store various look up tables (of the software of the present invention), parameters, coefficients, other information and data, programs or instructions, and other types of tables such as database tables.

As noted above, the processor 360 is programmed to perform the methods of the present invention, for example, using the software and data structures of the present invention. As a result, the systems and methods of the present invention may be implemented as software providing programming or other instructions such as metadata and/or a set of instructions embodied within the computer readable medium discussed above. Additionally, metadata can also be used to define lookup tables or various data structures in a database. Such software may be in the form of, for example, but not limited to, source code or object code. The source code may further be compiled into some form of instruction or object code (including assembler instructions or configuration information). The software, source code or metadata of the present invention may be any type of code, for example, C, C++, SystemC, LISA, XML, Java, Brew, SQL and its variants, or various hardware definitions or hardware modeling languages (eg It may be implemented as any other type of programming language that performs the functions discussed herein, including, for example, Verilog, VHDL, RTL) and final database files (eg, GDSII). Consequently, "construct", "program construct", "software construct" or "software", as used herein equivalently, provides or provides a specified related function or method. means and refers to any programming language of any kind, with any syntax or signature, that can be interpreted as when running).

The software, metadata, or other source code of the present invention and any final bit file (object code, database, or lookup table) may contain computer-readable instructions, data structures, program modules or As other data, any tangible storage medium, such as any of a computer or other machine-readable data storage medium, for example a floppy disk, CDROM, CD-RW, DVD, magnetic hard drive, optical drive, or the above It may be implemented in any other type of data storage device or medium as noted.

In addition to the controller 345 illustrated in FIG. 84, those skilled in the art will recognize that there are many equivalent settings, layouts, types and types of control circuitry known in the art that are within the scope of the present invention.

Although the invention has been described with respect to specific aspects thereof, these aspects are illustrative only and not limiting of the invention. In the description herein, numerous specific details are provided, such as examples of electronic components, electronic devices and structural connections, materials, and structural modifications, in order to provide a thorough understanding of aspects of the present invention. However, those skilled in the art will recognize that aspects of the present invention may be practiced without one or more of the specific details above, or with other devices, systems, assemblies, parts, materials, members, etc. will be. In other instances, well-known structures, materials, or operations have not been specifically shown or described in detail in order to avoid obscuring aspects of aspects of the invention. Those skilled in the art will also recognize that additional or equivalent method steps may be used, combined with other steps, or performed in different orders, all of which are within the scope of the claimed invention. In addition, the various drawings are not drawn to scale and should not be regarded as limiting.

Reference throughout this specification to “an aspect,” “an aspect,” or a particular “aspect” means that a particular feature, structure, or characteristic described in connection with that aspect is included in at least one aspect and necessarily in all aspects. They are not meant to be included and are not necessarily meant to refer to the same aspect. Moreover, a particular feature, structure, or characteristic of any particular aspect, including use of the selected feature without the corresponding use of the other feature, may be combined with one or more other aspects in any suitable manner and in any suitable combination. . In addition, many modifications may be made to adapt a particular field, situation, or material to the essential scope and spirit of the invention. It should be understood that other variations and modifications of the aspects of the invention described and illustrated herein are possible in light of the teachings herein and are considered part of the spirit and scope of the invention.

It will be appreciated that one or more of the members shown in the figures may be implemented in a more separate or integrated manner, or may even be removed or rendered inoperable in certain instances, as may be useful depending on the particular field. An integrally formed combination of parts is also within the scope of the present invention, particularly for aspects where the separation or combination of separate parts is unclear or not discernible. Also, the term “coupled” herein, including in various forms such as “coupled” or “coupled,” includes integrally formed parts, and parts coupled via or through another part. Any direct or indirect electrical, structural or magnetic coupling, connection or attachment, or adaptation or caper to such direct or indirect electrical, structural or magnetic coupling, connection or attachment, including means and includes capability.

As used herein for the purposes of the present invention, the term “LED” and its plural forms “LEDs” includes within the visible spectrum of any bandwidth or any color or color temperature or other spectrum such as ultraviolet or infrared. , any electroluminescent diode or other capable of generating radiation in response to an electrical signal, including, but not limited to, various semiconductor-based or carbon-based structures, light emitting polymers, organic LEDs, and the like that emit light in response to current or voltage. It should be understood to include any type of carrier injection-based or junction-based system. Also, as used for the purposes of the present invention, the term "photovoltaic diode" (or PV) and its plural forms "PVs" are encompassed within any bandwidth or spectrum of the visible spectrum or other spectrum such as ultraviolet or infrared. In response to incident energy (eg, light or other electromagnetic waves), including, but not limited to, various semiconductor-based or carbon-based structures that generate an electrical signal in response to light, an electrical signal (eg, a voltage ) should be understood to include any photovoltaic diode or other type of carrier injection-based or junction-based system capable of generating

The dimensions and values set forth herein are not to be construed as being strictly limited to the exact numbers recited. Rather, unless otherwise specified, each such dimension is intended to mean both the recited value and a functionally equivalent range enclosing it. For example, a dimension described as “40 mm” is intended to mean “about 40 mm”.

All documents cited in the Detailed Description of the Invention are, in relevant part, incorporated herein by reference; Citation of any document is not to be construed as an admission that it is prior art to the present invention. To the extent that any meaning or definition of a term in this document conflicts with any meaning or definition of the same term in a document incorporated by reference, the meaning or definition assigned to that term in this document shall control.

In addition, any signal arrows in the drawings are to be regarded as illustrative only and non-limiting, unless specifically noted. Combinations of step elements will also be considered within the scope of the present invention, particularly where the ability to separate or combine is unclear or foreseeable. As used throughout this specification and the claims that follow, the separate term "or" is intended to mean "and/or", which generally has both the meaning of linking and the meaning of separation, unless otherwise indicated. (Also, this is not limited to the meaning of "exclusive logicalization"). As used throughout the description of this specification and the claims that follow, terms in the singular include the plural, unless expressly indicated otherwise. Also, as used throughout the description of this specification and the claims that follow, the meaning of "on" includes "on" and "on." unless expressly indicated otherwise. .

The above description of illustrated aspects of the invention, including what is described in this Summary or Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. From the above, it will be appreciated that many changes, modifications and alternatives can be made and implemented without departing from the spirit and scope of the novel concept of the present invention. It should be understood that no limitations are intended or should be construed as to the specific methods and apparatus illustrated herein. Of course, it is intended that all such modifications fall within the scope of the claims be covered by the appended claims.

Claims (12)

A lighting device capable of being coupled to a power source, comprising:
Board;
a plurality of first conductors coupled to the substrate;
a plurality of light emitting diodes distributed in parallel on at least one of the plurality of first conductors;
at least one second conductor coupled to the plurality of light emitting diodes and coupled to a second conductor of the plurality of first conductors;
color structures, panels or layers; and
light dispersing or sealing structures, panels or layers;
at least some of the plurality of light emitting diodes have a first forward-bias orientation, and at least one of the plurality of light emitting diodes has a second reverse-bias orientation; wherein each light emitting diode of the plurality of light emitting diodes has a lateral dimension of 50 μm or less. The method of claim 1, wherein the plurality of first conductors have an interdigitated structure,
the lighting device further comprises a plurality of second conductors, wherein at least one second conductor is a first second conductor of the plurality of second conductors;
wherein the plurality of first conductors and the plurality of second conductors are arranged to provide a series coupled region of the plurality of light emitting diodes. The method of claim 1 , wherein the color structure, panel or layer comprises at least one color layer or region comprising a plurality of color tones, half tones, or color pixels, or combinations thereof. lighting device. The lighting device of claim 1 , wherein the color structure, panel or layer comprises at least one emissive or emissive layer or region comprising at least one phosphorescent or fluorescent emitter. The lighting device of claim 1 , wherein the color structure, panel or layer, or the light dispersing or sealing structure, panel or layer comprises a structure, coating, grating, panel or layer that is at least partially reflective or refractive. . The lighting device of claim 5 , wherein the at least partially reflective or refractive structure, coating, panel or layer comprises a plurality of reflective, dispersive, or refractive particles dispersed in a polymer. 7. The method of claim 6, wherein the plurality of reflective, dispersive, or refractive particles comprises a plurality of glass particles, silicate glass particles, borosilicate glass particles, metal particles, metallic particles, metal oxide particles, or A lighting device, further comprising a combination thereof. The lighting of claim 1 , wherein the color structure, panel or layer, or the light dispersing or sealing structure, panel or layer is offset from the plurality of light emitting diodes by a constant or variable predetermined distance. Device. The lighting device of claim 1 , wherein the light dispersing or sealing structure, panel or layer has a predetermined design and is coupled to encapsulate the substrate, light emitting diodes, and color structure, panel or layer. The lighting device of claim 1 , further comprising an offset or translucent insulating layer between the plurality of light emitting diodes and the color structure, panel or layer. The surface of claim 1 , wherein the light dispersing or sealing structure, panel or layer comprises at least one mirror or reflective structure, or at least one light extracting element, the at least one light extracting element comprising at least one lens, surface The lighting device is selected from the group consisting of textures, surface structures, mirrors, optical gratings, and combinations thereof. The method of claim 1, wherein each light emitting diode of the plurality of light emitting diodes has a lateral dimension of 50 μm or less, the plurality of light emitting diodes comprising:
a first plurality of light emitting diodes for emitting red light or light in a first spectral range;
a second plurality of light emitting diodes for emitting green light or light in a second spectral range; and
and a third plurality of light emitting diodes for emitting blue light or light in a third spectral range.

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