KR102400333B1 - Array substrate and liquid crystal display including the same - Google Patents

Abstract

The present invention relates to an array substrate capable of preventing distortion of a common voltage of a common voltage supply line by static electricity applied to an inspection line without an increase in cost, and a liquid crystal display including the same. Specifically, the present invention includes first and second ground electrodes spaced apart from each other, jumping electrodes electrically connecting the first and second ground electrodes, and a discharge circuit electrically connected to each of the jumping electrodes. As a result, the present invention provides discharge circuits connected to the jumping electrodes when static electricity from the outside is applied to the inspection lines or static electricity induced in the inspection lines is applied to the first and second ground electrodes. static electricity can be discharged. Accordingly, according to the present invention, it is possible to prevent the common voltage of the common voltage supply line disposed between the first and second ground electrodes from being distorted by static electricity.

Description

Array substrate and liquid crystal display including same

An embodiment of the present invention relates to an array substrate and a liquid crystal display including the same.

The liquid crystal display has a tendency to gradually expand its application range due to the characteristics of light weight, thin shape, and low power consumption driving. Liquid crystal display devices are widely used in portable computers such as notebook PCs, office automation devices, audio/video devices, indoor and outdoor advertisement display devices, and the like. A liquid crystal display displays an image by controlling an electric field applied to a liquid crystal layer to modulate light incident from a backlight unit.

The liquid crystal display includes an array substrate on which pixels are provided, a color filter substrate on which color filters and a black matrix are provided, and a liquid crystal layer interposed between the array substrate and the color filter substrate. Each of the pixels of the liquid crystal display modulates light incident from the backlight unit by driving the liquid crystal of the liquid crystal layer by an electric field between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

The manufacturing method of the liquid crystal display device is as follows. A plurality of array substrates are formed on the array mother substrate, and a plurality of color filter substrates are formed on the color filter mother substrate. Then, the array mother substrate and the color filter mother substrate are bonded to each other, and liquid crystal is injected between the array mother substrate and the color filter mother substrate. Then, by cutting the bonded array mother substrate and the color filter mother substrate through a scribing process, a plurality of liquid crystal display devices are provided.

Inspection lines may be formed on one side of each of the array substrates for defective inspection of thin film transistors or pixels provided on each of the array substrates of the array mother substrate. The defective inspection of the pixels may be performed by supplying driving signals and data voltages to the inspection lines.

On the other hand, the liquid crystal display device is manufactured in a borderless method in which a bezel is minimized by removing a top case in order to enhance the aesthetics of the appearance. The bezel is a border area of the liquid crystal display and refers to a non-display area in which an image is not displayed. In the borderless method, since the top case surrounding the upper portion of the liquid crystal display does not exist, there is a high probability that static electricity is applied to the inspection lines of each of the array substrates of the liquid crystal display. When static electricity is applied to the inspection lines, static electricity induced in the inspection lines 151 to 155 may be applied to a common voltage supply line disposed adjacent to the inspection lines. For this reason, a problem in that the common voltage of the common voltage supply line is distorted by static electricity may occur. When the common voltage of the common voltage supply line is distorted by static electricity, spots may be seen in an image displayed by the liquid crystal display device.

To solve this problem, a method of attaching a conductive tape to one side of an array substrate on which inspection lines are formed has been proposed. However, the method of attaching the conductive tape has a problem in that the cost increases due to the conductive tape.

An embodiment of the present invention provides an array substrate capable of preventing distortion of a common voltage of a common voltage supply line by static electricity applied to an inspection line without an increase in cost, and a liquid crystal display including the same.

The array substrate according to an embodiment of the present invention includes a first ground electrode to which a ground voltage is applied, a second ground electrode spaced apart from the first ground electrode, a jumping electrode electrically connecting the first and second ground electrodes, and a second ground electrode. A first driving voltage line to which one driving voltage is supplied, and a discharge circuit electrically connected between the jumping electrode and the first driving voltage line to discharge the voltage of the jumping electrode to the first driving voltage line.

A liquid crystal display device according to an embodiment of the present invention includes a display panel including an array substrate on which pixels are disposed and an upper substrate disposed on the array substrate. The array substrate includes a first ground electrode to which a ground voltage is applied, a second ground electrode spaced apart from the first ground electrode, a jumping electrode electrically connecting the first and second ground electrodes, and a first ground electrode to which a first driving voltage is supplied. and a first driving voltage line and a discharge circuit electrically connected between the jumping electrode and the first driving voltage line to discharge the voltage of the jumping electrode to the first driving voltage line.

An embodiment of the present invention includes first and second ground electrodes spaced apart from each other, jumping electrodes electrically connecting the first and second ground electrodes, and a discharge circuit electrically connected to each of the jumping electrodes. As a result, the embodiment of the present invention is connected to the jumping electrodes when static electricity from the outside is applied to the inspection lines or static electricity induced in the inspection lines is applied to the first and second ground electrodes. It is possible to discharge static electricity through the discharge circuits. Accordingly, the embodiment of the present invention can prevent the common voltage of the common voltage supply line disposed between the first and second ground electrodes from being distorted by static electricity.

In addition, according to the embodiment of the present invention, inspection lines are provided on one edge of each of the array substrates, and pads are provided on the opposite edge of one side of each of the array substrates. As a result, according to the embodiment of the present invention, the inspection lines of each of the array substrates may be connected to the inspection pads and the pads of the array substrate adjacent to the inspection lines. Accordingly, according to the embodiment of the present invention, a signal or voltage may be applied to each of the pads of the array substrate adjacent to the inspection lines by probing the jigs to the inspection pads and applying predetermined signals. Therefore, in the embodiment of the present invention, in order to increase the number of array substrates formed on the mother substrate, even when each of the plurality of array substrates is formed to contact the adjacent array substrates, the thin film transistors and pixels of the array substrate defects can be inspected.

Furthermore, in order to prevent the resistance of the first ground electrode from increasing, a second ground electrode is disposed between the common voltage supply line and the display area, and the first ground electrode and the second ground electrode are electrically connected through jumping electrodes. . As a result, in the embodiment of the present invention, the reduced area of the first ground electrode due to the common voltage supply line can be supplemented with the area of the second ground electrode. Accordingly, the embodiment of the present invention can prevent the resistance of the first ground electrode from being increased.

1 is an exemplary view showing an array mother substrate including a plurality of array substrates.
FIG. 2 is an exemplary view showing in detail the array substrates adjacent to each other of FIG. 1 .
3 is an exemplary view showing in detail an array substrate of a liquid crystal display according to an embodiment of the present invention.
4 is a circuit diagram illustrating the pixel of FIG. 3 .
FIG. 5 is a circuit diagram of the discharge circuit of FIG. 4 .
FIG. 6 is a plan view illustrating a region A of FIG. 3 in detail.
7 is a cross-sectional view taken along line II′ of FIG. 6 .
8 is a cross-sectional view taken along line II-II' of FIG. 5 .
9 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 10 is a cross-sectional view taken along line III-III' of FIG. 9 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than within the scope where the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of “at least one of the first, second, and third items” means that each of the first, second, or third items as well as two of the first, second and third items It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing an array mother substrate including a plurality of array substrates. Referring to FIG. 1 , in order to reduce the manufacturing cost of the liquid crystal display, a plurality of array substrates 100 may be formed on an array mother substrate 10 .

As the number of array substrates 100 formed on the mother substrate 10 increases, the manufacturing cost of the liquid crystal display device can be further reduced. In order to increase the number of array substrates 100 formed on the mother substrate 10 , each of the plurality of array substrates 100 may be formed to abut against the array substrates 100 adjacent thereto in the first direction as shown in FIG. 1 . can That is, upper and lower sides of one array substrate 100 may contact other array substrates 100 . Specifically, an upper side of one array substrate 100 contacts a lower side of another array substrate 100 adjacent in the y-axis direction, and a lower side of the array substrate 100 is adjacent to another array substrate 100 in the y-axis direction. ) may be in contact with the upper side of the

In addition, each of the array substrates 100 may be formed to be spaced apart from the array substrates 100 adjacent thereto by a predetermined distance s in the second direction as shown in FIG. 1 . The second direction may be a direction crossing the first direction and may be an x-axis direction. That is, left and right sides of one array substrate 100 may be formed to be spaced apart from other array substrates 100 by a predetermined distance s. In this case, inspection pads for inspecting defects of thin film transistors and pixels of each of the array substrates 100 may be provided at a predetermined interval s.

Meanwhile, in order to increase the number of array substrates 100 formed on the mother substrate 10 , each of the plurality of array substrates 100 may be in contact with the array substrates 100 adjacent thereto in the first direction as shown in FIG. 1 . When formed, inspection lines connecting the inspection pads and the respective pads of the array substrate 100 are formed on the array substrate 100 . Hereinafter, the inspection lines will be described in detail with reference to FIG. 2 .

FIG. 2 is an exemplary view showing in detail the array substrates adjacent to each other of FIG. 1 . In FIG. 2 , only three array substrates 100a , 100b , and 100c adjacent in the y-axis direction are illustrated for convenience of explanation. Specifically, in FIG. 2, the array substrate in contact with the upper side of the first array substrate 100a is exemplified as the second array substrate 100b, and the array substrate in contact with the lower side of the first array substrate 100a is the third array substrate ( 100c).

Each of the array substrates 100a, 100b, and 100c includes a display area DA, first and second gate drivers 110 and 120 , a common voltage supply line 130 , and inspection lines 151 to 155 . do. In addition, each of the array substrates 100a, 100b, and 100c includes data pads DP, common pads CP, gate pads GP, and ground pads GNDP. In FIG. 2 , only five inspection lines 151 to 155 are exemplified for convenience of description, but it should be noted that the number of inspection lines is not limited thereto.

The inspection lines 151 to 155 may be provided at one edge of each of the array substrates 100a, 100b, and 100c. Data pads DP, common pads CP, gate pads GP, and ground pads GNDP may be provided at opposite edges of one side of each of the array substrates 100a, 100b, and 100c. For example, as shown in FIG. 2 , inspection lines 151 to 155 are provided on upper edges of each of the array substrates 100a, 100b, and 100c, and data pads DP and common pads CP are provided on lower edges of each of the array substrates 100a, 100b, and 100c. Fields, gate pads GP, and ground pads GNDP may be provided. The data pads DP may be connected to the data lines DL, and the common pads CP may be connected to the common voltage supply line 130 . The gate pads GP may be connected to the gate control signal lines GCL, and the ground pads GNDP may be connected to the ground lines GNDL. The gate control signal lines GCL connect the gate pads GP and the gate drivers 110 and 120 , and the ground lines GNDL connect the ground pads GNDP and the first ground electrode 160 . .

Inspection lines 151 to 155 of each of the array substrates 100a, 100b, and 100c include inspection pads IP, data pads DP of the array substrate adjacent to inspection lines 151 to 155, and a common pad. CPs, gate pads GP, and ground pads GNDP are connected. The test pads IP may be provided at a predetermined interval s between each of the array substrates 100a , 100b , and 100c and the array substrate adjacent in the second direction as shown in FIG. 1 . For example, the test lines 151 to 155 of the first array substrate 100a may include test pads IP, data pads DP, common pads CP of the second array substrate 100b, and the like. The gate pads GP and the ground pads GNDP are connected. That is, one end of each of the inspection lines 151 to 155 of the first array substrate 100a is connected to the inspection pad IP, and the other end is the data pad of the second array substrate 100b. DP, the common pad CP, the gate pad GP, or the ground pad GNDP. Specifically, the inspection lines 151 to 155 of the first array substrate 100a are connected to the outside of the second array substrate 100b from the inspection pads IP and the gate pad GP of the second array substrate 100b. ), data pads DP, common pads CP, gate pads GP, and ground of the second array substrate 100b via one edge of the first array substrate 100a. It may be connected to the pads GNDP.

As described above, in the embodiment of the present invention, the inspection lines 151 to 155 are provided on one edge of each of the array substrates 100a, 100b, and 100c, and the data pads DP and the common pad CP ), gate pads GP, and ground pads GNDP are provided at opposite edges of one side of each of the array substrates 100a, 100b, and 100c. As a result, in the embodiment of the present invention, the inspection lines 151 to 155 of each of the array substrates 100a, 100b, and 100c are applied to the inspection pads IP and the array substrate adjacent to the inspection lines 151 to 155. They may be connected to the data pads DP, common pads CP, gate pads GP, and ground pads GNDP. Therefore, according to the embodiment of the present invention, the data pads DP of the array substrate adjacent to the inspection lines 151 to 155, the common ones, by probing the jigs to the inspection pads IP and applying predetermined signals. A voltage or a signal may be supplied to each of the pads CP, the gate pads GP, and the ground pads GNDP. Therefore, in the embodiment of the present invention, in order to increase the number of array substrates 100 formed on the mother substrate 10 , each of the plurality of array substrates 100 is disposed adjacent thereto in the first direction as shown in FIG. 1 . 100), defects of thin film transistors and pixels of the array substrate may be inspected.

FIG. 3 is an exemplary view showing in detail the first array substrate of FIG. 2 . Referring to FIG. 3 , the first array substrate 100a includes a display area DA, first and second gate drivers 110 and 120 , a common voltage supply line 130 , discharge circuits 140 , and inspection. It includes lines 151 to 155 , a first ground electrode 160 , a second ground electrode 170 , and jumping electrodes 180 . Also, the first array substrate 100a includes data pads DP, common pads CP, gate pads GP, and ground pads GNDP. Also, the first array substrate 100a includes data lines DL, gate lines GL, common lines CL, gate control signal lines GCL, and ground lines GNDL.

Data lines DL, gate lines GL, common lines CL, and pixels P are provided in the display area DA. The data lines DL cross the gate lines GL and the common lines CL. The data lines DL may be disposed in the y-axis direction, and the gate lines GL and common lines CL may be disposed in the x-axis direction. Each of the pixels P may be connected to a data line DL, a gate line GL, and a common line CL.

As shown in FIG. 4 , the pixel P may include a transistor T, a pixel electrode 11 , a common electrode 12 , a liquid crystal cell 13 , and a storage capacitor Cst. The transistor T is turned on by the gate signal of the gate line GL to supply the data voltage of the data line DL to the pixel electrode 11 . The common electrode 12 receives a common voltage from the common line CL. For this reason, the pixel P drives the liquid crystal of the liquid crystal cell 13 by the electric field generated by the potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 to drive the backlight unit. It is possible to adjust the amount of transmitted light from the As a result, the pixels P can display an image. In addition, the storage capacitor Cst is provided between the pixel electrode 11 and the common electrode 12 to maintain a constant voltage difference between the pixel electrode 11 and the common electrode 12 .

The common electrode 12 is formed on the upper substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. It is formed on the lower substrate together with the pixel electrode in the horizontal electric field driving method. The liquid crystal mode of the display panel 110 may be implemented in any liquid crystal mode as well as the aforementioned TN mode, VA mode, IPS mode, and FFS mode.

First and second gate drivers 110 and 120 , common voltage supply line 130 , inspection lines 151 to 155 , first ground electrode 160 , second ground electrode 170 , gate control signal Lines GCL, data pads DP, common pads CP, gate pads GP, and ground pads GNDP are disposed in non-display area NDA provided around display area DA. are placed The non-display area NDA is an area in the first array substrate 100a excluding the display area DA, and is an area in which an image is not displayed.

The first and second gate drivers 110 and 120 are connected to the gate lines GL. The first and second gate drivers 110 and 120 receive gate control signals from gate control signal lines GCL connected to the gate pads GP. Each of the first and second gate drivers 110 and 120 outputs gate signals to the gate lines GL in a predetermined order according to the gate control signals. The predetermined order may be a sequential order. Also, the first and second gate drivers 110 and 120 simultaneously output gate signals to the gate lines GL.

The first gate driver 110 may be disposed outside one side of the display area DA, and the second gate driver 120 may be disposed outside the other side of the one side of the display area DA. For example, as shown in FIG. 3 , the first gate driver 110 may be disposed on the left outer side of the display area DA, and the second gate driver 120 may be disposed on the right outer side of the display area DA. there is. Also, although FIG. 3 illustrates that the first array substrate 110a includes two gate drivers, it should be noted that the present invention is not limited thereto. That is, the first array substrate 110a may include only one gate driver.

3 illustrates that the first and second gate drivers 110 and 120 are directly formed on the first array substrate 100a using a gate driver in panel (GIP) method including a plurality of transistors, but is not limited thereto. should pay attention to That is, when each of the first and second gate drivers 110 and 120 is implemented as a driving chip, they may be mounted on a flexible film. In this case, by attaching the flexible film on which the driving chip is mounted to the first array substrate 100a by a tape automated bonding (TAB) method, the first and second gate drivers 110 and 120 are connected to the gate line GL. can be connected to

The common voltage supply line 130 is connected to the common pads CP to receive a common voltage. The common voltage supply line 130 is connected to the common lines CL. Accordingly, the common voltage applied to the common pads CP may be supplied to the common lines CL through the common voltage supply line 130 .

The common voltage supply line 130 is connected between the display area DA and the first gate driver 110 , between the display area DA and the second gate driver 120 , and between the display area DA and the first ground electrode ( ). 160) may be disposed between. That is, the common voltage supply line 130 may be disposed to surround the outer three sides of the display area DA, for example, the upper outer side, the left outer side, and the right outer side.

The discharge circuits 140 may be disposed between the first ground electrode 160 and the first driving voltage line of each of the first and second gate drivers 110 and 120 . Each of the discharge circuits 140 is connected to a jumping electrode 180 electrically connecting the first ground electrode 160 and the second ground electrode 170 and a first driving voltage line to the first ground electrode 160 or The static electricity applied to the second ground electrode 170 is discharged to the first driving voltage line. A detailed description of the discharging circuit 140 will be described later with reference to FIGS. 5 and 6 .

The inspection lines 151 to 155 are disposed at one edge of the first array substrate 100a. For example, as shown in FIG. 3 , the inspection lines 151 to 155 may be provided on the upper edge of the first array substrate 100a.

When the first array substrate 100a is cut by a scribing process, the inspection lines 151 to 155 are connected to the inspection pads IP and the second array substrate adjacent to the first array substrate 100a. The data pads DP, the common pads CP, the gate pads GP, and the ground pads GNDP of 100b are not connected. That is, as shown in FIG. 2 , the inspection lines 151 to 155 of the first array substrate 100a transmit voltages or signals from the inspection pads IP to the second array substrate 100b adjacent to the first array substrate 100a. ) of the data pads DP, common pads CP, gate pads GP, and ground pads GNDP, so that the first array substrate 100a is subjected to a scribing process. When cut by , no voltage is applied to the inspection lines 151 to 155 . That is, when the first array substrate 100a is cut by a scribing process, the inspection lines 151 to 155 are floated.

The first ground electrode 160 is connected to the ground pads GNDP through the ground lines GNDL to receive a ground voltage. The ground voltage may be a voltage of 0V or less. The first ground electrode 160 is disposed between the test lines 151 to 155 and the common voltage supply line 130 .

The second ground electrode 170 is spaced apart from the first ground electrode 160 and is disposed between the common voltage supply line 130 and the display area DA. The first ground electrode 160 and the second ground electrode 170 are electrically connected through the jumping electrodes 180 . Specifically, since both the first and second ground electrodes 160 and 170 and the common voltage supply line 130 are formed in the first metal pattern, the first and second ground electrodes 160 and 170 are electrically connected to each other. In order to connect, jumping electrodes 180 formed on a layer different from that of the first metal pattern are required.

Specifically, since the common voltage supply line 130 is disposed between the display area DA and the inspection lines 151 to 155 , the first ground electrode is disposed between the display area DA and the inspection lines 151 to 155 . The thickness of 160 becomes thinner. Accordingly, there is a problem in that the resistance of the first ground electrode 160 is increased. In the embodiment of the present invention, in order to prevent the resistance of the first ground electrode 160 from increasing, the second ground electrode 170 is disposed between the common voltage supply line 130 and the display area DA, and the first The ground electrode 160 and the second ground electrode 170 are electrically connected through the jumping electrodes 180 . As a result, in the embodiment of the present invention, the reduced area of the first ground electrode 160 due to the common voltage supply line 130 can be supplemented with the area of the second ground electrode 170 . Accordingly, the embodiment of the present invention can prevent the resistance of the first ground electrode 160 from being increased.

The data pads DP, common pads CP, gate pads GP, and ground pads GNDP may be provided on an opposite edge of one side of the first array substrate 100a. In this case, inspection lines 151 to 155 are provided on one side of the first array substrate 100a. For example, when the inspection lines 151 to 155 are provided on the upper edge of the first array substrate 100a as shown in FIG. 3 , the data pads DP, the common pads CP, and the gate pad GP ) and the ground pads GNDP may be provided at the lower edge of the first array substrate 100a. The data pads DP are connected to the data lines DL, the common pads CP are connected to the common voltage supply line 130 , and the gate pads GP are connected to the gate control signal lines GCL. , ground pads GNDP may be connected to ground lines GNDL.

As described above, in the embodiment of the present invention, the first ground electrode 160 is disposed between the common voltage supply line 130 and the inspection lines 151 to 155 , and the display area DA and the common voltage are supplied. The second ground electrode 170 is disposed between the lines 130 , the first and second ground electrodes 160 and 170 are electrically connected using the jumping electrodes 180 , and the discharge circuits 140 are formed. Each is electrically connected to each of the jumping electrodes 180 . As a result, in the embodiment of the present invention, static electricity from the outside is applied to the inspection lines 151 to 155 , and static electricity induced in the inspection lines 151 to 155 is applied to the first and second ground electrodes. When the voltages 160 and 170 are applied, static electricity may be discharged through the discharge circuits 140 connected to the jumping electrodes 180 . Accordingly, the embodiment of the present invention can prevent the common voltage of the common voltage supply line 130 disposed between the first and second ground electrodes 160 and 170 from being distorted by static electricity.

FIG. 5 is a circuit diagram of the discharge circuit of FIG. 4 . Referring to FIG. 5 , the discharging circuit 140 according to the embodiment of the present invention includes a discharging element and a resistor (R).

When the voltage difference between the first driving voltage of the first driving voltage line DVL1 and the ground voltage of the jumping electrode 180 is greater than a threshold voltage, the discharge device converts the voltage of the jumping electrode 180 to the first driving voltage line DVL1. discharge Hereinafter, for convenience of description, the discharge element will be mainly described as the transistor TR. However, the discharge device is not limited to the transistor TR, and may be a diode.

The transistor TR includes a gate electrode and a source electrode electrically connected to the first driving voltage line DVL1 , and a drain electrode electrically connected to the jumping electrode 180 . The transistor TR may be formed of a thin film transistor. The resistor R is disposed between the gate electrode and the drain electrode of the transistor TR.

When static electricity is not applied, since the gate electrode and the source electrode of the transistor TR are connected to the first driving voltage line DVL1, the gate-source voltage difference Vgs is the threshold voltage Vth of the transistor TR. smaller than (Vgs<Vth) For this reason, since the transistor TR is in a turned-off state, no current flows from the drain electrode to the source electrode.

However, when static electricity (10 kV) is applied, since the drain electrode of the transistor TR is connected to the jumping electrode 180 , the potential of the drain electrode greatly increases. In this case, since the voltage difference Vds between the drain and the source of the transistor TR is greater than the voltage Vgs-Vth obtained by subtracting the threshold voltage Vth from the voltage difference between the gate and source Vgs (Vds>Vgs-) Vth), the transistor TR is turned on. Accordingly, the static electricity 10kV applied to the jumping electrode 180 may be discharged to the first driving voltage line DVL1 .

As described above, in the embodiment of the present invention, when static electricity is applied to the first and second ground electrodes 160 and 170 using the discharge circuit 140 , the first and second ground electrodes 160 . , 170 , static electricity may be discharged through the discharge circuits 140 connected to the jumping electrodes 180 . Accordingly, the embodiment of the present invention can prevent the common voltage of the common voltage supply line 130 disposed between the first and second ground electrodes 160 and 170 from being distorted by static electricity.

FIG. 6 is a plan view illustrating a region A of FIG. 3 in detail. 6 , for convenience of explanation, a common voltage supply circuit 130 , a discharge circuit 140 , a first ground electrode 160 , a second ground electrode 170 , a jumping electrode 180 , and a first driving voltage line Only (DVL1) is shown.

Referring to FIG. 6 , the discharge circuit 140 includes a transistor TR and a resistor R. The transistor TR includes a gate electrode GE connected to the first driving voltage line DVL1 through the first contact hole CNT1 , a source electrode SE extending from the first driving voltage line DVL1 , and a second transistor TR. A drain electrode DE connected to the jumping electrode 180 through the second contact hole CNT2 is included. The resistor R extends from the jumping electrode 180 and is connected to the gate electrode GE of the transistor TR through the third contact hole CNT3 . The size of the resistor R may be set according to the thickness and length of the wiring.

The jumping electrode 180 electrically connects the first and second ground electrodes 160 and 170 across the common voltage supply line 130 . The jumping electrode 180 is connected to the second ground electrode 170 through the fourth contact hole CNT4 , and is connected to the first ground electrode 180 through the fifth contact hole CNT5 .

A first driving voltage corresponding to a gate low voltage and a second driving voltage corresponding to a gate high voltage are supplied to the gate drivers 110 and 120 , and the first driving voltage line DVL1 is connected to the gate drivers 110 and 120 ) is a line for supplying the first driving voltage to each. The gate low voltage is a voltage capable of turning off the transistors of the display area DA and the gate drivers 110 and 120 and may be a voltage of 0V or less. The gate high voltage is a voltage capable of turning on the transistors of the display area DA and the gate drivers 110 and 120 and may be a voltage of 10V or more.

7 is a cross-sectional view taken along line II′ of FIG. 6 . 8 is a cross-sectional view taken along line II-II' of FIG. 5 . Hereinafter, in conjunction with FIGS. 6 to 8 , the transistor TR and the resistor R of the discharge circuit 140 , and the jumping electrode 180 electrically connecting the first and second ground electrodes 160 and 170 . ) will be described in detail.

6 to 8, on the first array substrate 100a, the gate electrode GE of the transistor TR, the common voltage supply line 130, the first ground electrode 160, and the second ground electrode ( 170) may be formed as the first metal pattern. The first metal pattern is a gate metal pattern, for example, a single layer or molybdenum (Mo), titanium using molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu) as a material. It may be formed in a multi-layer structure including at least two metals among a material of (Ti), aluminum (Al), or copper (Cu).

A gate insulating layer GI is formed on the first metal pattern. The gate insulating layer GI may be an inorganic layer such as silicon nitride (SiNx) and silicon oxide (SiOx).

An active layer ACT is formed on the gate insulating layer GI. A source electrode SE and a drain electrode DE of the transistor TR, and a first driving voltage line DVL1 may be formed in a second metal pattern on the gate insulating layer GI. The second metal pattern is a source-drain metal pattern using molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu) as a material to form a single layer or molybdenum (Mo), titanium (Ti). , may be formed in a multi-layer structure including at least two metals of a material of aluminum (Al) or copper (Cu).

The source electrode SE and the drain electrode DE of the transistor TR may be formed to overlap a portion of the active layer ACT. Accordingly, each of the source electrode SE and the drain electrode DE of the transistor TR may be connected to the active layer ACT on the active layer ACT. Since the first driving voltage line DLV1 is formed in the second metal pattern while the gate electrode GE of the transistor TR is formed in the first metal pattern, the gate electrode GE of the transistor TR and the first The driving voltage line DVL1 may be connected to each other through the first contact hole CNT1 passing through the gate insulating layer GI.

A passivation layer PAS is formed on the active layer ACT and the second metal pattern. The passivation layer PAS may be an organic layer such as photo acrylic (PAC).

The jumping electrode 180 may be formed in a third metal pattern on the passivation layer PAS. The third metal pattern is a transparent electrode pattern, and may be formed of, for example, transparent conducting oxide (TCO) such as induim tin oxide (ITO) and induim zinc oxide (IZO).

The drain electrode DE of the transistor TR and the jumping electrode 180 may be connected to each other through the second contact hole CNT2 penetrating the passivation layer PAS. In addition, the gate electrode GE of the transistor TR and the resistor R extending from the jumping electrode 180 are connected to each other through the third contact hole CNT3 penetrating the gate insulating layer GI and the passivation layer PAS. can be Also, the second ground electrode 170 and the jumping electrode 180 may be connected to each other through the fourth contact hole CNT4 penetrating the gate insulating layer GI and the passivation layer PAS. Furthermore, the first ground electrode 160 and the jumping electrode 180 may be connected to each other through the fifth contact hole CNT5 penetrating the gate insulating layer GI and the passivation layer PAS.

9 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 9 , the liquid crystal display according to the embodiment of the present invention includes a display panel 1000 , a flexible film 1300 , a source drive integrated circuit (hereinafter referred to as “IC”) 1400 , and a circuit Includes a board 1500 .

The display panel 1000 includes a first substrate 1100 , a second substrate 1200 , and a liquid crystal layer interposed between the first substrate 1100 and the second substrate 1200 . The first substrate 1100 may be an array substrate on which pixels are provided. Since the first substrate 1100 has already been described in detail with reference to FIG. 3 , a detailed description thereof will be omitted.

The second substrate 1200 may be a color filter substrate on which a color filter and a black matrix are provided. However, when the display panel 1000 is formed using a color filter on TFT array (COT) method, the color filter may be formed on the array substrate.

The flexible film 1400 must be attached to the data pads DP, common pads CP, gate pads GP, and ground pads GNDP formed on the first substrate 1100 . Accordingly, in order to expose the data pads DP, common pads CP, gate pads GP, and ground pads GNDP, the size of the second substrate 1200 is that of the first substrate 1100 . may be smaller than the size.

10 , a first polarizing plate 1110 may be attached to the first substrate 1100 , and a second polarizing plate 1210 may be attached to the second substrate 1200 . In addition, an alignment layer for setting a pretilt angle of the liquid crystal may be formed on an inner surface in contact with the liquid crystal layer on each of the first substrate 1100 and the second substrate 1200 .

When the source drive IC 1400 is implemented as a driving chip, it is mounted on the flexible film 1300 in a chip on film (COF) or chip on plastic (COP) manner as shown in FIG. 9 . A plurality of pads connected to the data pads DP, common pads CP, gate pads GP, and ground pads GNDP of FIG. 3 may be provided on the flexible film 1300 . Also, the flexible film 1300 may be provided with wires connecting the data pads DP and the source drive IC 1400 and wires connected to the wires of the circuit board 1500 . The flexible film 1300 is attached on data pads (DP), common pads (CP), gate pads (GP), and ground pads (GNDP) using an anisotropic conducting film, Accordingly, the data pads DP, the common pads CP, the gate pads GP, and the ground pads GNDP may be connected to the pads of the flexible film 1300 .

The source drive IC 1400 supplies data voltages to the data lines D1 to Dm. Specifically, the source drive IC 1400 may supply data voltages to the data lines DL through wires, pads, and data pads DP of the flexible film 1300 .

The circuit board 1500 may be attached to the flexible film 1300 . A plurality of circuits implemented with driving chips may be mounted on the circuit board 1500 . For example, a common voltage supply circuit and a timing control circuit implemented by driving chips may be mounted on the circuit board 1500 . Also, a connector connected to a signal cable to which signals input from the outside are supplied may be provided on the circuit board 1500 . A plurality of wires connected to the driving chips and the connector may be provided on the circuit board 1500 , and the wires of the circuit board 1500 may be connected to wires of the flexible film 1300 .

The liquid crystal display device further includes a backlight unit. The backlight unit may be disposed under the display panel 1000 to irradiate light to the display panel 1000 . The backlight unit may be implemented as a direct type or an edge type.

FIG. 10 is a cross-sectional view taken along line III-III' of FIG. 9 . Referring to FIG. 10 , the description has been focused on that the first substrate 1100 is an array substrate and the second substrate 1200 is a color filter substrate. In FIG. 10 , the backlight unit is not shown for convenience of explanation, and the display area DA of the first substrate 1100 , the common voltage supply line 130 , and the first and second ground electrodes 160 and 170 . , and only the inspection lines 1700 are shown.

A transparent static electricity protection layer 1220 for preventing static electricity may be disposed on an upper surface of the second substrate 1200 , and a second polarizing plate 1210 may be disposed on an upper surface of the transparent static electricity protection layer 1220 . At this time, when the liquid crystal display device is implemented as borderless in order to enhance the aesthetics of the appearance, the top case is deleted, and the second polarizing plate 1210 includes the second substrate 1200 and the transparent static electricity protection layer. It includes an extension portion 1211 extending longer than 1220 , and an adhesive 1600 is applied to the extension portion 1211 of the second polarizing plate 1210 and the side surface of the display panel 1000 .

In the borderless liquid crystal display device, since the transparent static electricity protection layer 1220 for preventing static electricity is covered by the second polarizing plate 1210 and is not exposed to the outside, external static electricity is provided on the first substrate 1100. It is easy to be supplied to the inspection lines 1700 . However, in the embodiment of the present invention, the first ground electrode 160 is disposed between the inspection lines 1700 and the common voltage supply line 130 , and between the display area DA and the common voltage supply line 130 . The second ground electrode 170 is disposed, and the first and second ground electrodes 160 and 170 are electrically connected using the jumping electrodes 180 as shown in FIG. 3 , and each of the discharge circuits 140 is connected to each other. It is electrically connected to the jumping electrode 180 . As a result, in the embodiment of the present invention, external static electricity is applied to the inspection lines 1700 , and static electricity induced in the inspection lines 1700 is applied to the first and second ground lines 160 and 170 . In this case, it may be discharged through the discharging circuits 140 . Accordingly, the embodiment of the present invention can prevent the common voltage of the common voltage supply line 130 from being distorted by static electricity.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: mother substrate 100: array substrate
100a: first array substrate 100b: second array substrate
100c: third array substrate 110: first gate driver
120: second gate driver 130: common voltage supply line
140: discharge circuits 151 to 155, 1700: inspection lines
160: first ground electrode 170: second ground electrode
180: jumping dungeon 1000: display panel
1100: first substrate 1110: first polarizing plate
1200: second substrate 1210: second polarizing plate
1220: transparent electrostatic protective layer 1300: flexible film
1400: source drive IC 1500: circuit board
1600: adhesive

Claims (14)

a first ground electrode to which a ground voltage is applied;
a second ground electrode spaced apart from the first ground electrode;
a common voltage supply line disposed between the first ground electrode and the second ground electrode and to which a common voltage is applied;
inspection lines disposed outside the first ground electrode;
a jumping electrode electrically connecting the first and second ground electrodes;
a first driving voltage line to which a first driving voltage is supplied; and
and a discharge circuit electrically connected between the jumping electrode and the first driving voltage line and discharging the voltage of the jumping electrode to the first driving voltage line;
The discharging circuit includes a discharging element that is a transistor,
and the inspection lines, the common voltage supply line, the first ground electrode, and the second ground electrode are disposed on the same layer as a gate electrode of the transistor. The method of claim 1,
The discharge element is an array substrate for discharging the voltage of the jumping electrode to the first driving voltage line when a voltage difference between the first driving voltage and the ground voltage is greater than a threshold voltage. 3. The method of claim 2,
An array substrate in which a gate electrode and a source electrode of the transistor are connected to a first driving voltage line to which a first driving voltage is supplied, and a drain electrode is connected to the jumping electrode. 4. The method of claim 3,
The discharge circuit is
The array substrate further comprising a resistor connected between the gate electrode and the jumping electrode. delete 4. The method of claim 3,
The first driving voltage line is disposed on the same layer as the source electrode and the drain electrode of the transistor. 4. The method of claim 3,
The jumping electrode is an array substrate disposed on a transparent electrode layer disposed on the source electrode and the drain electrode. The method of claim 1,
The inspection lines are disposed on one edge of the array substrate. 9. The method of claim 8,
data lines and gate lines crossing each other;
data pads connected to the data lines;
common pads connected to the common voltage supply line; and
Further comprising ground pads connected to the first ground electrode,
The data pads, the common pads, and the ground pads are disposed on the opposite edge of the one side. The method of claim 1,
The inspection lines are floating lines to which no voltage is applied. A display panel comprising: an array substrate on which pixels are disposed; and an upper substrate disposed on the array substrate;
The array substrate is
a first ground electrode to which a ground voltage is applied;
a second ground electrode spaced apart from the first ground electrode;
a common voltage supply line disposed between the first ground electrode and the second ground electrode and to which a common voltage is applied;
inspection lines disposed outside the first ground electrode;
a jumping electrode electrically connecting the first and second ground electrodes;
a first driving voltage line to which a first driving voltage is supplied; and
and a discharge circuit electrically connected between the jumping electrode and the first driving voltage line and discharging the voltage of the first ground electrode to the first driving voltage line;
The discharging circuit includes a discharging element that is a transistor,
The inspection lines, the common voltage supply line, the first ground electrode, and the second ground electrode are disposed on the same layer as the gate electrode of the transistor. 12. The method of claim 11,
Further comprising a polarizing plate disposed on the upper surface of the upper substrate,
The polarizing plate includes an extension portion extending longer than one side of the upper substrate. 13. The method of claim 12,
The liquid crystal display device further comprising an adhesive applied to the extended portion of the polarizing plate and a side surface of the display panel. 13. The method of claim 12,
The array substrate further includes inspection lines disposed on one side of the array substrate corresponding to one side of the upper substrate.

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