KR102400275B1 - Gate driving method, gate driver, and display device - Google Patents

Abstract

The present embodiments relate to a gate driving method using a gate clock signal enabling reduction in power consumption, a gate driver, and a display device.

Description

Gate driving method, gate driver and display device {GATE DRIVING METHOD, GATE DRIVER, AND DISPLAY DEVICE}

The present embodiments relate to a gate driving method, a gate driver, and a display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device, a plasma display device, and an organic light emitting display device ( Various display devices such as Organic Light Emitting Display Device) are being used.

Such a display device includes a display panel in which data lines and gate lines are disposed and subpixels are disposed, a data driver driving the data lines, a gate driver sequentially driving the gate lines, and the like.

Meanwhile, the gate driver includes a pull-up transistor and a pull-down transistor to output a scan signal (gate signal), and a high-level voltage is passed through the pull-up transistor to turn on the corresponding gate line. (VGH) is output to the gate line, and a low level voltage (VGL) is outputted to the gate line through a pull-down transistor in order to turn off the corresponding gate line.

For such gate driving, the gate driver receives a clock signal in which a high-level section having a high-level voltage VGH corresponding to a constant voltage and a low-level section having a low-level voltage VGL corresponding to a constant voltage are repeated. , a gate signal is generated using the input clock signal and output to the corresponding gate line.

When driving the gate, the low-level voltage VGL in the low-level section of the clock signal significantly increases the current inside the gate driver, thereby increasing power consumption.

It is an object of the present embodiments to provide a gate driving method, a gate driver, and a display device capable of reducing power consumption.

Another object of the present embodiments is to provide a gate driving method, a gate driver, and a display device using a gate clock signal capable of reducing power consumption.

In one embodiment, a gate signal is generated based on a display panel on which a plurality of gate lines are disposed, and a gate clock signal in which a high level section having a high level voltage corresponding to a constant voltage and a low level section having a high impedance level are repeated. A display device including a gate driver outputting to a corresponding gate line may be provided.

The gate clock signal used in generating the gate signal in such a gate driver is a signal obtained by changing a clock signal in which a high-level section of a high-level voltage and a low-level section of a low-level voltage are repeated. The high-level section is a high-level voltage, , the low-level section may be a signal changed from the low-level voltage to the voltage-floating high-impedance level.

In another embodiment, a clock signal input unit receiving a clock signal in which a high level voltage (VGH) corresponding to a constant voltage and a low level voltage are repeated, and a low level section of the clock signal are changed from a low level voltage to a high impedance level, a clock signal changing unit generating a gate clock signal in which a high level section having a high level voltage and a low level section having a high impedance level are repeated; and a gate signal generating circuit section generating and outputting a gate signal based on the gate clock signal It is possible to provide a gate driver that

Another embodiment may provide a method of driving a gate of a display device including a display panel having a plurality of gate lines disposed thereon and a gate driver driving the plurality of gate lines.

The method of driving a gate of a display device includes: generating, by a gate driver, a gate signal based on a gate clock signal in which a high-level section having a high-level voltage corresponding to a constant voltage and a low-level section having a high impedance level are repeated; This may include, by the gate driver, outputting the gate signal to the corresponding gate line.

According to the present exemplary embodiments as described above, it is possible to provide a gate driving method, a gate driver, and a display device capable of reducing power consumption.

According to the present exemplary embodiments, it is possible to provide a gate driving method, a gate driver, and a display device using a gate clock signal capable of reducing power consumption.

According to the present exemplary embodiments, when a display panel with a built-in touch panel is included, it is possible to provide a display device capable of improving sensing accuracy by preventing the formation of a parasitic capacitor.

1 is a schematic system configuration diagram of a display device according to example embodiments.
2 is a diagram illustrating a gate driver integrated circuit of a GIP (Gate In Panel) type included in the gate driver of the display device according to the present exemplary embodiment.
3 is a schematic block diagram of a gate driver integrated circuit in the display device according to the present exemplary embodiment.
4 is an exemplary diagram of a gate signal generating circuit in the gate driver integrated circuit in the display device according to the present exemplary embodiment.
5 is another exemplary diagram of a gate signal generating circuit in the gate driver integrated circuit in the display device according to the present exemplary embodiment.
6 is a diagram illustrating an 8-phase clock signal when a gate driving based on an 8-phase clock is performed in the display device according to the present exemplary embodiment.
7 is a diagram illustrating an 8-phase gate clock signal in which a low-level section is a high-impedance level when the 8-phase clock-based gate driving is performed in the display device according to the present exemplary embodiment.
8 is a diagram illustrating an 8-phase gate clock signal obtained by adjusting a size of a pull-down transistor to have a low-level section similar to a constant voltage when the 8-phase clock-based gate driving is performed in the display device according to the present exemplary embodiment; the drawing shown.
9 and 10 are exemplary implementations of the gate signal generating circuit in the gate driver integrated circuit and signal timing diagrams according to the operation of the display device according to the present embodiments.
11 is an exemplary view illustrating touch electrodes and signal lines disposed on the display panel when the display device according to the present exemplary embodiment includes a display panel having a built-in touch panel.
12 is a diagram illustrating a signal applied to a touch electrode disposed on a display panel according to a driving mode (display mode, touch mode) in the display device according to the present exemplary embodiment.
13 is a diagram illustrating a capacitance component generated in a display panel during a touch mode time in the display device according to the present exemplary embodiment.
14 and 15 illustrate a load-free driving method for removing a parasitic capacitance component generated in the display panel when a touch driving signal is applied to the touch electrode during the touch mode time in the display device according to the present exemplary embodiments; It is a drawing.
16 to 19 are exemplary diagrams of a gate signal generating circuit in a gate driver integrated circuit for load-free driving in a display device according to example embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a schematic system configuration diagram of a display device 100 according to the present exemplary embodiment.

Referring to FIG. 1 , the display device 100 according to the present exemplary embodiment includes a display panel 110 , a data driver 120 , a gate driver 130 , a timing controller 140 , and the like.

The display panel 110 includes a plurality of data lines DL1, DL2, ... , DLm, and m is a natural number greater than or equal to 2), and a plurality of gate lines GL1, GL2, ..., GLn, n is a natural number greater than or equal to 2 ) is placed.

In addition, a plurality of sub-pixels (SP) are arranged in a matrix type on the display panel 110 .

The data driver 120 drives a plurality of data lines DL1, DL2, ..., DLm.

The gate driver 120 sequentially supplies a gate signal (also referred to as a “scan signal”) to the plurality of gate lines GL1, GL2, ... , GLn, and sequentially supplies the plurality of gate lines GL1, GL2, .. . , GLn) are driven sequentially.

The timing controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130 .

The timing controller 140 starts scanning according to the timing implemented in each frame, converts externally input image data to match the data signal format used by the data driver 120 , and outputs the converted image data, , to control the data drive at an appropriate time according to the scan.

The gate driver 130 sequentially drives the plurality of gate lines by sequentially supplying a scan signal of an on voltage or an off voltage to the plurality of gate lines under the control of the timing controller 140 . .

The gate driver 130 may be positioned on only one side of the display panel 110 as shown in FIG. 1 or, in some cases, on both sides, according to a driving method.

Also, the gate driver 130 may include a plurality of gate driver integrated circuits (GDICs).

In addition, the plurality of gate driver integrated circuits are connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or a gate (GIP) method. In Panel) type and may be disposed directly on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

Each of the plurality of gate driver integrated circuits included in the gate driver 130 may include a shift register, a level shifter, and the like.

When a specific gate line is opened, the data driver 120 converts the image data received from the timing controller 140 into an analog data voltage and supplies it to the data lines, thereby driving a plurality of data lines.

The data driver 120 may include one or more source driver integrated circuits (SDICs).

One or more source driver integrated circuits included in the data driver 120 are connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method. It may be connected or directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

Each of the one or more source driver integrated circuits included in the data driver 120 may include a shift register, a latch circuit, a digital analog converter (DAC), an output butter, and the like, and in some cases, sub-pixel compensation For this purpose, an analog-to-digital converter (ADC) for sensing an analog voltage value, converting it into a digital value, and generating and outputting sensed data may be further included.

In addition, each of the one or more source driver integrated circuits included in the data driver 120 may be implemented in a Chip On Film (COF) method. In each of the one or more source driver integrated circuits, one end is bonded to at least one source printed circuit board, and the other end is bonded to the display panel 110 .

Meanwhile, the timing controller 140 transmits a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, a clock signal (CLK), etc. together with input image data from the outside. Receive various timing signals including

The timing controller 140 converts input image data input from the outside to match the data signal format used by the data driver 120 and outputs the converted image data, as well as the data driver 120 and the gate driver 130 ), the data driver 120 and the gate driver 130 receive timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal to generate various control signals. ) is output.

For example, the timing controller 140 controls the gate driver 130 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable). The gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls shift timing of a scan signal (gate pulse). The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

The timing controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). ) and outputs various data control signals (DCS: Data Control Signals) including The source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120 .

Referring to FIG. 1 , the timing controller 140 may be disposed on a source printed circuit board to which a source driver integrated circuit is bonded, and a source printed circuit board to which the source driver integrated circuit is bonded and a flexible flat cable (FFC). Cable) or flexible printed circuit (FPC) may be disposed on a control printed circuit board (Control Printed Circuit Board) connected through a connection medium such as.

In the source printed circuit board or the control printed circuit board, a power controller (not shown) that supplies various voltages or currents to the display panel 110 , the data driver 120 , and the gate driver 130 , or controls various voltages or currents to be supplied. ) may be further disposed. Such a power controller is also referred to as a power management integrated circuit (PMIC).

Meanwhile, in each subpixel SP disposed on the display panel 110 , circuit elements such as a transistor and a capacitor may be basically disposed.

On the other hand, the gate driver 130 provides a clock signal in which a high-level section having a “high-level voltage VGH corresponding to a constant voltage” and a low-level section having a “low-level voltage VGL corresponding to a constant voltage” are repeated. CLK) may be used to generate a gate signal and output it to a corresponding gate line.

In this case, the low-level voltage VGL in the low-level section of the clock signal CLK may increase the current in the gate driver 130 to increase power consumption.

Accordingly, in the present embodiments, in order to reduce power consumption, the gate driver 130 repeats a high-level section having a “high-level voltage VGH corresponding to a constant voltage” and a low-level section having a “high impedance level” repeatedly. The gate signal may be output to the corresponding gate line based on the “gate clock signal GCLK”.

Here, the gate clock signal GCLK is a clock signal obtained by changing the clock signal CLK in which the high-level section of the high-level voltage VGH and the low-level section of the low-level voltage VGL are repeated. The high level voltage VGH, and the low level section may be a clock signal changed from the low level voltage VGL to the voltage floating high impedance level Hi-Z.

As described above, instead of using the “clock signal CLK” in which a high-level section having a high-level voltage VGH corresponding to a constant voltage and a low-level section having a “low-level voltage VGL corresponding to a constant voltage” are repeated. , using the “gate clock signal GCLK” in which a high-level section having a high-level voltage VGH corresponding to a constant voltage and a low-level section of “high impedance level” are repeated, a gate signal is generated and transmitted to the corresponding gate line By outputting it, the current in the gate driver 130 can be reduced to reduce power consumption.

The display device 100 according to the present exemplary embodiment shown briefly in FIG. 1 is, for example, a liquid crystal display device, a plasma display device, and an organic light emitting display device. Display Device) and the like.

Also, the display device 100 according to the present exemplary embodiments may be a large display or a mobile display such as a smart phone or a tablet PC.

Hereinafter, the gate driver 130 that enables the aforementioned power consumption reduction will be described in more detail.

2 illustrates a plurality of gate driver integrated circuits (GDIC #1, ..., GDIC #n) of a GIP (Gate In Panel) type included in the gate driver 130 of the display device 100 according to the present exemplary embodiment. is a diagram showing

Referring to FIG. 2 , as described above, the gate driver 130 may include a plurality of gate driver integrated circuits GDIC #1, ..., GDIC #n.

The plurality of gate driver integrated circuits (GDIC #1, ..., GDIC #n) is a gate driver (GIP) disposed outside an active area (AA) corresponding to an image display area of the display panel 110 . In Panel) type.

Referring to FIG. 2 , as an example, the plurality of gate driver integrated circuits GDIC #1, ... , GDIC #n correspond to the plurality of gate lines GL1 , ... , GLn one-to-one to electrically A gate signal may be output through a connected and electrically connected gate line.

3 is a schematic block diagram of one gate driver integrated circuit (GDIC #k, k=1, 2, ..., n) in the display device 100 according to the present exemplary embodiments.

Referring to FIG. 3 , each gate driver integrated circuit GDIC #k included in the gate driver 130 includes a clock signal input unit 310 , a clock signal change unit 320 , and a gate signal generation circuit unit 330 . include

The clock signal input unit 310 transmits a clock signal (CLK, corresponding to a general clock signal) in which a high level voltage VGH corresponding to a constant voltage and a low level voltage VGL corresponding to a constant voltage are repeated to the clock signal wiring 340 . can be entered through

The clock signal changing unit 320 uses only the high-level voltage VGH in the high-level section of the received clock signal CLK to convert the low-level section of the clock signal CLK from the low-level voltage VGL to the high impedance. By changing to the level Hi-Z, the gate clock signal GCLK in which the high-level section having the high-level voltage VGH and the low-level section having the high impedance level are repeated may be generated.

The gate signal generation circuit unit 330 may generate and output a gate signal Vgate (also referred to as a “scan signal”) based on the gate clock signal GCLK.

As described above, the clock signal CLK in which the high level voltage VGH corresponding to the constant voltage and the low level voltage VGL corresponding to the constant voltage are repeated is not directly used to generate the gate signal, but the received clock signal CLK ) to generate a gate clock signal GCLK in which a high-level section having a high-level voltage VGH corresponding to a constant voltage and a low-level section having a high impedance level are repeated using only the high-level voltage VGH in the high-level section and by using the generated gate clock signal GCLK to generate a gate signal Vgate and output it to the corresponding gate line GLk, the current in the gate driver integrated circuit GDIC #k is reduced to reduce power consumption. can be reduced

In FIG. 3 , the clock signal input unit 310 and the clock signal change unit 320 are illustrated as being included in the gate driver integrated circuit GDIC #k, but this is only an example for convenience of description, and in some cases Accordingly, it may be included outside the gate driver integrated circuit GDIC #k.

Referring to FIG. 3 , in the gate driver 130 , the clock signal input unit 310 receives a clock signal CLK in which a high level voltage VGH and a low level voltage VGL are repeated through the clock signal line 340 . When , the clock signal changing unit 320 uses only the high level voltage VGH of the input clock signal CLK, a high level section having a high level voltage VGH, and a voltage floating Thus, a gate clock signal GCLK in which a low-level section having a high-impedance (Hi-Z) level is repeated may be generated.

As described above, using only the high level voltage VGH of the high level section of the received clock signal CLK, the high level section having the high level voltage VGH corresponding to the constant voltage and the low level section of the high impedance level In generating the repeated gate clock signal GCLK, the high impedance level of the low-level section of the gate clock signal GCLK is implemented through voltage floating, so that the gate driver integrated circuit GDIC #k Power consumption can be greatly reduced by reducing a current generated by a voltage in the low-level section of the gate clock signal GCLK inside.

As described above, even when the low-level section of the gate clock signal is set to the high impedance level, the Q node, QB node, and the output voltage of the gate signal are not affected, and a normal gate driving is possible.

In this case, power consumption can be reduced, but since inefficiencies may occur in timing control of gate driving, etc., in order to solve this disadvantage,

Meanwhile, referring to FIG. 3 , the gate signal generating circuit unit 330 includes a pull-up transistor (Tup: Pull-Up Transistor), a pull-down transistor (Tdown: Pull-Down Transistor), and a control circuit unit (C/C: Control Circuit) and the like.

The pull-up transistor Tup is electrically connected between the gate clock signal application node and the gate signal output node, is turned on by the voltage of the Q node, and has a high level voltage VGH. The gate clock signal GCLK in the level section may be output to the gate signal output node as the high level gate signal Vgate.

The pull-down transistor Tdown is electrically connected between the gate signal output node and the base voltage node Nvss, and is turned on by the voltage of the QB node to output a low-level gate signal to the gate signal output node. can

The control circuit unit C/C may control charging and discharging of the Q node and the QB node.

When the gate signal generating circuit unit 330 is used, the gate signal (GCLK) is used in which a high level section having a high level voltage VGH corresponding to a constant voltage and a low level section having a high impedance level are repeated. Vgate) and output, it is possible to significantly reduce power consumption by reducing the current (DC current) generated by the voltage in the low-level section of the gate clock signal GCLK inside the gate driver integrated circuit (GDIC #k). there is.

Meanwhile, referring to FIG. 3 , two or more clock signal wires 340 may be disposed next to each gate driver integrated circuit GDIC #k.

Here, the number of clock signal wirings is the number of phases of the clock signal CLK used by the gate driver 130 and the arrangement of the plurality of gate driver integrated circuits GDIC #1, ..., GDIC #n. It may vary depending on a method (one-side arrangement or both-side arrangement), a gate signal feeding method, or a gate driving method.

4 and 5 are exemplary views of the gate signal generating circuit unit 330 in each gate driver integrated circuit GDIC #k in the display device 100 according to the present exemplary embodiments.

As shown in FIG. 4 , the gate signal generation circuit 330 in each gate driver integrated circuit GDIC #k uses one pull-down transistor Tdown to provide a low-level gate signal ( Vgate_low) may be applied.

Unlike this, as shown in FIG. 5 , the gate signal generating circuit unit 330 in each gate driver integrated circuit GDIC #k uses two pull-down transistors Tdown1 and Tdown2 to obtain a low-level gate. A signal Vgate_low may be applied.

Referring to FIG. 4 , the gate signal generating circuit unit 330 of each of the plurality of gate driver integrated circuits GDIC included in the gate driver 130 includes one pull-up transistor Tup and one pull-down transistor. (Tdown) and may be configured to include a control circuit (C/C).

The pull-up transistor Tup is electrically connected between the gate clock signal application node Ngclk and the gate signal output node Nout, and is turned on or off by the voltage of the Q node.

Here, the gate node of the pull-up transistor Tup is electrically connected to the Q node, and the drain node or the source node of the pull-up transistor Tup is electrically connected to the gate clock signal application node Ngclk to have a constant voltage The gate clock signal GCLK in which a high-level section having a high-level voltage VGH corresponding to , and a low-level section having a high impedance level are repeated is applied. In addition, a source node or a drain node of the pull-up transistor Tup is electrically connected to a gate signal output node Nout from which the gate signal Vgate is output.

The pull-up transistor Tup is turned on by the voltage of the Q node, and uses the high-level voltage VGH in the high-level section of the gate clock signal GCLK as the high-level gate signal Vgate_high. By outputting the output to the output node Nout, a high-level gate signal Vgate_high may be supplied to a gate line electrically connected to the gate signal output node Nout.

The pull-down transistor Tdown is electrically connected between the gate signal output node Nout and the base voltage node Nvss, and is turned on or off by the voltage of the QB node.

Here, a gate node of the pull-down transistor Tdown is electrically connected to the QB node, and a drain node or a source node of the pull-down transistor Tdown is electrically connected to the base voltage node Nvss and corresponds to a constant voltage. A base voltage VSS is applied. In addition, a source node or a drain node of the pull-down transistor Tdown is electrically connected to a gate signal output node Nout from which the gate signal Vgate is output.

This pull-down transistor Tdown is turned on by the voltage of the QB node and outputs a low-level gate signal Vgate_low to the gate signal output node Nout, and is electrically connected to the gate signal output node Nout. A low-level gate signal Vgate_low may be supplied to the connected gate line.

Here, the low-level gate signal Vgate_low may be, for example, a base voltage Vss.

On the other hand, the control circuit unit (C/C), an internal circuit including two or more transistors, etc. may be configured, and in the internal circuit, main nodes such as a Q node, a QB node, a set node (S, also referred to as a start node) there is In some cases, the internal circuit of the control circuit unit C/C may further include a reset node to which a reset signal is input, an input node to which various voltages such as the driving voltage VDD are input, and the like.

In the control circuit unit C/C, the Q node is electrically connected to the gate node of the pull-up transistor Tup, and charging and discharging are repeated.

In the control circuit unit C/C, the QB node is electrically connected to the gate node of the pull-down transistor Tdown, and charging and discharging are repeated.

In the control circuit unit C/C, the set node S receives a start signal VST instructing start of gate driving of the corresponding gate driver integrated circuit. Here, the start signal VST is the gate signal Vgate output from the gate driver integrated circuit 1, 2, or 4 stages ahead of the current stage, depending on the number of phases of the gate clock signal GCLK. it could be

As shown in FIG. 4 , when a low-level gate signal is applied to the corresponding gate line using only one pull-down transistor Tdown, there is an advantage in that the gate driver integrated circuit can be simply implemented.

Meanwhile, during one frame time, a high-level gate signal Vgate_high is applied to one gate line for a short time, and a low-level gate signal Vgate_low is applied for a long time.

As such, in order to apply the low-level gate signal Vgate_low to the gate line for a relatively long time, the pull-down transistor Tdown is turned on for a relatively long time compared to the pull-up transistor Tup. there should be Therefore, the pull-down transistor Tdown is highly likely to be deteriorated.

Accordingly, by providing two or more pull-down transistors and operating them alternately, it is possible to prevent deterioration of the transistors involved in outputting the low-level gate signal.

5 shows two pull-down transistors including a first pull-down transistor Tdown1 and a second pull-down transistor Tdown2 to alternately operate at odd frame times and even frame times, so that the low-level This is an example for preventing deterioration of a transistor involved in outputting a gate signal.

Referring to FIG. 5 , the gate signal generating circuit unit 330 of each of the plurality of gate driver integrated circuits GDIC included in the gate driver 130 includes one pull-up transistor Tup and two pull-down transistors. (a first pull-down transistor Tdown1, a second pull-down transistor Tdown2) and a control circuit unit C/C.

Referring to FIG. 5 , the pull-up transistor Tup is electrically connected between the gate clock signal application node Ngclk and the gate signal output node Nout, and is turned on by the voltage of the Q node, The high-level voltage VGH in the high-level section of the signal GCLK may be output as the high-level gate signal Vgate_high to the gate signal output node Nout.

The first pull-down transistor Tdown1 and the second pull-down transistor Tdown2 may alternately operate at odd frame times and even frame times.

That is, the first pull-down transistor Tdown1 may be turned on for an odd frame time to output a low-level gate signal, and the second pull-down transistor Tdown2 may be turned on for an even frame time to output a low-level gate signal. A gate signal can be output.

The first pull-down transistor Tdown1 is electrically connected between the gate signal output node Nout and the base voltage node Nvss, and is turned on by the voltage of the first QB node for an odd frame time, The level gate signal Vgate_low may be output to the gate signal output node Nout.

Here, the low-level gate signal Vgate_low may be, for example, a base voltage Vss.

The second pull-down transistor Tdown2 is electrically connected between the gate signal output node Nout and the base voltage node Nvss, and is turned on by the voltage of the second QB node during an even frame time to generate a low The level gate signal Vgate_low may be output to the gate signal output node Nout.

As shown in FIG. 5 , when the two pull-down transistors Tdown1 and Tdown2 are alternately used to apply a low-level gate signal to the corresponding gate line, deterioration of the pull-down transistor can be prevented. .

The clock signal CLK used in the gate driver 130 according to the present exemplary embodiment and the gate clock signal GCLK generated by the gate driver 130 using the clock signal GCLK are two-phase, four-phase, or eight-phase. (Phase) can have.

Hereinafter, an eight-phase clock signal CLK and an eight-phase gate clock signal GCLK will be described with reference to FIGS. 6 to 8 .

However, below, as an example, 1920 gate lines are disposed on the display panel 110 (ie, n=1920), and 1920 gate driver integrated circuits (GDIC #1, .. , GDIC #1920) is disposed, and a dummy gate driver is integrated on top of the topmost gate driver integrated circuit (GDIC #1) among 1920 gate driver integrated circuits (GDIC #1, ..., GDIC #1920). There are four circuits, and among the 1920 gate driver integrated circuits (GDIC #1, ... Assume that there are four.

6 exemplarily illustrates 8-phase clock signals CLK 1 , CLK 2 , ... , CLK 8 in the case of performing gate driving based on an 8-phase clock in the display device 100 according to the present exemplary embodiments. It is a drawing.

Referring to FIG. 6 , in each of the eight-phase clock signals CLK 1 , CLK 2 , ... , CLK 8 , a high level section and a low level section are repeated.

In each of the eight-phase clock signals CLK 1 , CLK 2 , ... , CLK 8 , the high-level section has a high-level voltage VGH of a constant voltage, and the low-level section has a low-level voltage VGL of a constant voltage. .

That is, in each of the eight-phase clock signals CLK 1 , CLK 2 , ... , CLK 8 , the high level voltage VGH and the low level voltage VGL are repeated.

7 illustrates an 8-phase gate clock signal GCLK in which a low-level section is a high-impedance level Hi-Z when the 8-phase clock-based gate driving is performed in the display device 100 according to the present exemplary embodiment. is a diagram showing

As described above, the gate driver 130 according to the present embodiments receives one (or two or more) of the eight-phase clock signals CLK 1 , ... , CLK 8 as shown in FIG. 6 . , by using this as it is, instead of generating and outputting a gate signal, an 8-phase gate clock signal (GCLK 1, ... , GCLK 8) as shown in FIG. 7 is newly generated and output to the gate line based on this. Generate a gate signal.

That is, each gate driver integrated circuit GDIC #k included in the gate driver 130 according to the present exemplary embodiment includes the eight-phase clock signals CLK 1 , ... , CLK 8 as shown in FIG. 6 . One (or two or more) of them is received, a corresponding gate clock signal as shown in FIG. 7 is generated, and based on this, a gate signal is generated and output.

Each gate driver integrated circuit GDIC #k uses only the high-level voltage VGH in the high-level section of the inputted clock signal when generating the corresponding gate clock signal.

Accordingly, the gate clock signal generated by each gate driver integrated circuit GDIC #k has a high level voltage VGH of a constant voltage in the high level section.

However, the gate clock signal generated by each gate driver integrated circuit (GDIC #k) is not captured as the low-level voltage VGL of the low-level section of the corresponding clock signal to which the low-level section voltage is input, but is floating (floating). ) to have a high impedance level.

Accordingly, as shown in FIG. 7 , the eight-phase gate clock signals GCLK 1 , ... , GCLK 8 have a high level section having a high level voltage VGH and a constant voltage (eg, VGL). A low-level section having an uncaught high-impedance level (Hi-Z) is repeated.

As shown in FIG. 7 , a low-level section of each of the eight-phase gate clock signals GCLK 1 , ... , GCLK 8 has a high impedance level. In other words, it is not held as a constant voltage, but in a floating state.

In this case, power consumption can be reduced, but inefficiencies may occur in timing control of gate driving. By adjusting, the low-level section of the gate clock signal GCLK can be efficiently held in a form similar to the constant voltage level.

Here, the size of the pull-down transistors Tdown, Tdwon1, Tdown2, ... may be determined by the size of W (channel width)/L (channel length), and corresponds to the current driving capability.

That is, by adjusting the size of the pull-down transistors Tdown, Tdwon1, Tdown2, ... to be larger, the voltage change from the high level section to the low level section in the gate clock signal GCLK is sharper. can make you change

The sizes of the pull-down transistors Tdown, Tdwon1, Tdown2, ... may be larger than sizes of other transistors in the gate driving integrated circuit GDIC.

The size of the pull-down transistors Tdown, Tdwon1, Tdown2, ... is designed to be larger than the size of other transistors in the gate driving integrated circuit (GDIC), but the bezel area (corresponding to the image display area) of the display panel 110 is The area outside the active area AA) can be enlarged within a range that does not increase.

8 is a diagram illustrating a low-level section similar to a constant voltage by adjusting the size of the pull-down transistor Tdown when the 8-phase clock-based gate driving is performed in the display device 100 according to the present exemplary embodiments. 8-phase gate clock signals (GCLK 1, ... , GCLK 8) are shown.

Referring to FIG. 8 , by adjusting the size of the pull-down transistor Tdown, the low-level section of each of the gate clock signals GCLK 1, ... , GCLK 8 of 8 phases is obtained in the form of a constant voltage at the high impedance level. it can be seen that

9 and 10 are exemplary implementations of the gate signal generating circuit 330 in the gate driver integrated circuit GDIC and signal timing diagrams according to the operation of the display device 100 according to the present exemplary embodiments.

9 is an example in which the gate signal generating circuit unit 330 of the gate driver integrated circuit that applies a low-level gate signal to the gate line is actually implemented using two pull-down transistors Tdown1 and Tdown2 as shown in FIG. 5 . It is also

Referring to FIG. 9 , the gate signal generating circuit unit 330 includes one pull-up transistor Tup and W2 , first pull-down transistors Tdown1 and W3 , and a second pull-down transistor Tdown2 , W3') and a control circuit unit C/C.

Referring to FIG. 9 , the control circuit unit C/C includes 12 transistors W1, W4, W5, W6, W7, W8, W9, W4', W5', W6', W7', W8', etc. Thus, it is possible to control charging and discharging of the Q node, the QB1 node, and the QB2 node.

An operation procedure of the gate driver integrated circuit (GDIC) illustrated in FIG. 9 will be described with reference to FIG. 10 . step,

S01: VST(k) is rising.

S02: In stage k (stage), W1 is turned on to charge the Q node (eg, the voltage of the Q node = +10V).

S03: VST(k) is polled.

S04: GCLK(k) becomes the high-level voltage VGH in the high-level section.

S05: In stage k, the pull-up transistor W2 is turned on, and the output voltage Vgate(k) of the gate signal output node Nout becomes the high-level voltage VGH.

S06: In stage k, the Q node is further charged by the Q node, GCLK(k), the output voltage Vgate(k) of the gate signal output node Nout, etc. (eg, the Q node voltage=+27V).

S07: GCLK(k) is not the low-level voltage VGL in the form of a constant voltage, but a high impedance level in the low-level section. Then, GCLK(k+4) becomes the high-level voltage VGH in the high-level section.

S08: In the k+4 stage, the pull-up transistor W2 is turned on, and the output voltage Vgate (k+4) of the gate signal output node Nout becomes the high level voltage VGH.

S09: At stage k, the Q node is discharged by W9.

S10: In stage k, the QB node is charged, and the Q node is completely discharged by W8.

S11: In the k stage, the output voltage Vgate(k) of the gate signal output node Nout falls.

As described above, by changing the low-level section of the gate clock signal GCLK from the low-level voltage VGL to the high-impedance level Hi-Z, the Q node, QB node, Vgate(k), Vgate(k+4) ), while allowing normal operation without affecting the

Meanwhile, the display device 100 according to the present exemplary embodiments may process a user's touch on the screen as an input. In this case, the display device 100 according to the present embodiments includes a touch panel.

The touch panel included in the display device 100 according to the present exemplary embodiment may be an external type included outside the display panel 110 or a built-in type included in the display panel 110 .

Hereinafter, the above-described gate driving method will be described again by taking as an example that the display panel 110 of the display device 100 according to the present exemplary embodiment has a built-in touch panel.

11 is an exemplary diagram illustrating touch electrodes and signal lines disposed on the display panel 110 when the display device 100 according to the present embodiments includes the display panel 110 having a built-in touch panel. .

Referring to FIG. 11 , the touch panel built-in display panel 110 functions as a display panel when the driving mode is the display mode, and functions as a touch panel when the driving mode is the touch mode.

Referring to FIG. 11 , in the touch panel built-in display panel 110 , a plurality of data lines DL and a plurality of gate lines GL are disposed, as well as a plurality of touch electrodes CE (common voltage) are disposed. .

Referring to FIG. 11 , the plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, and CE34, the display panel 110 serves as a display panel and serves as a touch screen. It is an electrode that allows you to do all of these things.

Therefore, the plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34, when the driving mode is the display mode, a common voltage (Vcom: Common Voltage) is applied, and when the driving mode is a touch mode, a touch driving signal (Vtm) is applied.

That is, the plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, and CE34 are common electrodes that can be used in both the display mode and the touch mode.

In other words, when the driving mode is the display mode, the same common voltage Vcom is common to the plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34. is authorized When the driving mode is the touch mode, one or more of the plurality of touch electrodes (CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34) has a touch, touch coordinates, etc. A touch driving signal Vtm for detection is applied. In this case, the plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, and CE34 serve as touch electrodes.

Referring to FIG. 11 , when the driving mode is the display mode, the common voltage Vcom is transmitted to the plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34. and, when the driving mode is the touch mode, transmitting the touch driving signal (Vtm) to at least one of the plurality of touch electrodes (CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34) For this purpose, signal lines SL11, SL12, SL13, SL14, SL21, SL22, SL23 , SL24 , SL31 , SL32 , SL33 , and SL34 are disposed on the display panel 110 .

As described above, by utilizing the common electrode to which a common voltage can be applied during the display mode time as a touch electrode to which a touch driving signal can be applied during the touch mode time, the structure of the touch panel-embedded display panel 110 is compact. and can be implemented efficiently.

12 is a diagram illustrating a signal applied to a touch electrode disposed on the display panel 110 according to a driving mode (display mode, touch mode) in the display device 100 according to the present exemplary embodiments.

Referring to FIG. 12 , the display mode and the touch mode are continuously performed for each frame section.

12 , in the display mode, the common voltage Vcom is applied to the touch electrode CE, and in the touch mode, the touch driving signal Vtm is applied to the touch electrode CE.

In the touch mode, the touch driving signal Vtm is applied to the touch electrode CE to perform touch sensing.

In this regard, the touch panel integrated display device 100 according to the embodiment is a touch method and detects the presence or absence of a touch and touch coordinates based on a change in capacitance (capacitance) through a plurality of touch electrodes disposed on the touch panel. A capacitive touch method is adopted.

The capacitive touch method may be divided into, for example, a mutual capacitance touch method and a self capacitance touch method.

First, in the mutual capacitance touch method, which is a type of the capacitance touch method, a touch driving signal is sequentially applied to first electrodes among first and second touch electrodes arranged in a direction crossing each other Thus, by measuring the voltage or capacitance of the second touch electrodes, the presence or absence of a touch and the touch coordinates are detected based on the change in capacitance between the first touch electrode and the second touch electrode according to the presence or absence of a pointer such as a finger or pen. touch method.

Next, in the self-capacitance touch method, which is another type of the capacitance touch method, a touch electrode is disposed to form capacitance (self-capacitance) with a pointer such as a finger or a pen, and the presence or absence of a pointer such as a finger or a pen This is a method of detecting the presence or absence of a touch and touch coordinates based on the capacitance value between the touch electrode and the point according to the measurement.

In this self-capacitance touch method, a driving voltage (touch driving signal) is applied and sensed simultaneously through each touch electrode, unlike the mutual capacitance touch method.

The touch panel integrated display device 100 according to the embodiment may employ one of the above-described two capacitive touch methods (a mutual capacitance touch method and a self-capacitance touch method). However, in the present specification, for convenience of description, it is assumed that the self-capacitance touch method is employed and the embodiment is described.

13 is a diagram illustrating a capacitance component generated in the display panel 110 during a touch mode time in the display device 100 according to the present exemplary embodiment.

Referring to FIG. 13 , a plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34 is used in a touch mode to detect the presence or absence of a touch and touch coordinates. For this purpose, a capacitance (Cself) is formed with a pointer such as a finger or a pen, but a parasitic capacitance (Cpara: Parasitic Capacitance, Cpara1, Cpara2) is unnecessary with the data line (DL) and the gate line (GL) for display purposes. can

Parasitic capacitances Cpara1 and Cpara2 generated in the touch mode act as a large load for touch driving, and may decrease touch sensing accuracy or make touch sensing itself impossible. The parasitic capacitance Cpara increases as the size of the display device 100 or the display panel 110 increases, which may cause a greater problem in touch sensing.

14 and 15 are diagrams illustrating a load-free driving method for removing a parasitic capacitance component generated in the display panel 110 during a touch mode time in the display device 100 according to the present exemplary embodiment.

14 and 15 are diagrams illustrating a load-free driving method for removing a parasitic capacitance component generated in the display panel 110 during a touch mode time in the display device 100 according to the present exemplary embodiment.

Referring to FIG. 14 , in the touch panel integrated display device 100 according to the embodiment, in order to remove the parasitic capacitance component, the touch integrated circuit 1400 performs a plurality of touch electrodes CE11, CE12, When the touch driving signal Vtm is sequentially applied to CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34, the load-free driving signal LFD_data corresponding to the touch driving signal Vtm, LFD_gate) may also be applied to the data line DL and the gate line GL. Here, the touch integrated circuit 1400 may be included outside or inside the data driver 120 .

Accordingly, the potential difference between the touch electrode CE and the gate line GL is eliminated, so that the parasitic capacitance Cpara1 is not formed between the touch electrode CE and the gate line GL. Also, the potential difference between the touch electrode CE and the data line DL is eliminated, so that the parasitic capacitance Cpara2 is not formed between the touch electrode CE and the data line DL.

When the display mode and the touch mode are repeated for each frame section, signal waveforms applied to the touch electrode CE, the data line DL, and the gate line GL in the display mode and the touch mode are shown in FIG. 15 . .

Referring to FIG. 15 , during the display mode time within one frame time, the data driver 120 outputs the data voltage Vdata through the data line DL.

During the display mode time within one frame time, the gate driver 130 has a short section (high level section) having the high level voltage (VGH) once, and the remaining long section having the high impedance (Hi-Z) level ( A gate signal (Vgate, also referred to as a scan signal) of the low level section) is output to the corresponding gate line GL.

During the display mode time within one frame time, the common voltage supply unit (not shown) supplies a plurality of signal lines SL11, SL12, SL13, SL14, SL21, SL22, SL23, SL24, SL31, SL32, SL33, SL34 through A common voltage Vcom is applied to the touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, and CE34.

At this time, the common voltage Vcom is transferred from the common voltage supply unit (not shown) to the data driver 120 , and is transmitted to the plurality of signal lines SL11 , SL12 , SL13 , SL14 , SL21 by the data driver 120 . SL22, SL23, SL24, SL31, SL32, SL33, SL34). In addition, in some cases, the common voltage Vcom does not pass through the data driver 120 , but a plurality of signal lines SL11, SL12, SL13, SL14, SL21, SL22, SL23, SL24 from the common voltage supply unit (not shown). , SL31, SL32, SL33, SL34) may be output directly.

On the other hand, during the touch mode time within one frame time, the touch integrated circuit 1400 through a plurality of signal lines (SL11, SL12, SL13, SL14, SL21, SL22, SL23, SL24, SL31, SL32, SL33, SL34) , the touch driving signal Vtm may be sequentially applied to the plurality of touch electrodes CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, and CE34.

In this case, as an example, the touch driving signal Vtm is generated in the touch integrated circuit 1400 , and through the data driver 120 , a plurality of signal lines SL11, SL12, SL13, SL14, SL21, SL22, SL23, SL24, SL31, SL32, SL33, SL34) can be sequentially output. In addition, in some cases, the touch driving signal Vtm is generated by the touch integrated circuit 1400 , and a plurality of signal lines SL11, SL12, SL13, SL14, SL21, SL22, SL23, SL24, SL31, SL32, SL33 , SL34) may be output directly.

In addition, during the touch mode time within one frame time, that is, the touch driving signal is sequentially applied to the plurality of touch electrodes (CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34) In the meantime, the data driver 120 may output the load-free driving signal LFD_data corresponding to the touch driving signal Vtm to the data line DL.

Here, the data driver 120 may receive the load-free driving signal LFD_data corresponding to the touch driving signal Vtm from the touch integrated circuit 1400 and output it to the data line DL, or the touch integrated circuit ( A predefined load-free driving signal LFD_data may be output to the data line DL without receiving a signal from the 1400 .

In addition, during the touch mode time within one frame time, that is, the touch driving signal is sequentially applied to the plurality of touch electrodes (CE11, CE12, CE13, CE14, CE21, CE22, CE23, CE24, CE31, CE32, CE33, CE34) In the meantime, the gate driver 130 may output the load-free driving signal LFD_gate corresponding to the touch driving signal Vtm to the gate line GL.

Here, the gate driver 130 may receive the load-free driving signal LFD_gate corresponding to the touch driving signal Vtm from the touch integrated circuit 1400 and output it to the gate line GL, or the touch integrated circuit ( A predefined load-free driving signal LFD_gate may be output to the data line DL without receiving a signal from the 1400 .

As described above, during the touch mode time, that is, while the touch driving signal is applied to the touch electrode, the load-free driving signals LFD_data and LFD_gate corresponding to the touch driving signal are applied to the data line and the gate line, so that unnecessary parasitics By preventing the formation of the capacitor, it is possible to increase the sensing accuracy.

Here, during the touch mode time, the load-free driving signal applied to the data line and the gate line may be the same signal as the touch driving signal applied to the touch electrode, or a signal having the same frequency, phase, etc. as the touch driving signal.

16 to 19 are exemplary diagrams of a gate signal generating circuit unit 330 in a gate driver integrated circuit (GDIC) for load free driving in the display device 100 according to example embodiments.

16 and 17, as in FIG. 4, during the display mode time, using one pull-down transistor Tdown, a low-level gate signal Vgate_low to be applied to the gate line is generated and outputted. With respect to the circuit part 330, there are two modified structural diagrams for applying the load-free driving.

Referring to FIG. 16 , the gate signal generating circuit unit 330 of each of the plurality of gate driver integrated circuits (GDIC) included in the gate driver 130 generates a high level signal through the corresponding gate line during the display mode time within one frame time. A pull-up transistor (Tup) for outputting a gate signal, a low-level gate signal (Vgate_low) is output to the corresponding gate line during a display mode time within one frame time, and a load during a touch mode time within one frame time It includes a pull-down transistor Tdown for outputting the pre-drive signal LFD_gate, and a control circuit unit C/C for controlling charging and discharging of the Q node and the QB node.

The pull-up transistor Tup is electrically connected between the gate clock signal application node Ngclk and the gate signal output node Nout during the display mode time within one frame time, and is turned on by the voltage of the Q node. , and output the high-level voltage VGH in the high-level section of the gate clock signal GCLK as the high-level gate signal Vgate_high to the gate signal output node.

The pull-down transistor Tdown is electrically connected between the gate signal output node Nout and the base voltage node Nvss, and is turned on by the voltage of the QB node, The gate signal Vgate_low of the level is output to the gate signal output node Nout. Here, the low-level gate signal Vgate_low may be, for example, the base voltage VSS.

The pull-down transistor Tdown outputs a low-level gate signal to the gate signal output node during the display mode time within one frame time, and gates the load-free driving signal LFD_gate during the touch mode time within one frame time. It outputs to the signal output node (Nout).

That is, the pull-down transistor Tdown is a transistor used for both the display mode and the touch mode.

17 , the gate signal generating circuit unit 330 of each of the plurality of gate driver integrated circuits (GDIC) included in the gate driver 130 includes each of the plurality of gate driver integrated circuits (GDIC) included in the gate driver 130 , respectively. The gate signal generation circuit unit 330 of the display mode time within one frame time includes a pull-up transistor Tup for outputting a high-level gate signal to the corresponding gate line during the display mode time within one frame time, and during the display mode time within one frame time, A pull-down transistor Tdown that outputs a low-level gate signal Vgate_low to the corresponding gate line, and a touch-only pull-down transistor that outputs a load-free driving signal LFD_gate during the touch mode time within one frame time (Tdown_touch), and a control circuit unit (C/C) for controlling the charging and discharging of the Q node and the QB node, and the like.

The pull-up transistor Tup is electrically connected between the gate clock signal application node Ngclk and the gate signal output node Nout during the display mode time within one frame time, and is turned on by the voltage of the Q node. , and output the high-level voltage VGH in the high-level section of the gate clock signal GCLK as the high-level gate signal Vgate_high to the gate signal output node.

The pull-down transistor Tdown is electrically connected between the gate signal output node Nout and the base voltage node Nvss, and is turned on by the voltage of the QB node, The gate signal Vgate_low of the level is output to the gate signal output node Nout. Here, the low-level gate signal Vgate_low may be, for example, the base voltage VSS.

Referring to FIG. 17 , the gate signal generating circuit unit 330 of each of the plurality of gate driver integrated circuits GDIC included in the gate driver 130 is disposed between the gate signal output node Nout and the base voltage node Nvss. A touch-only pull-down transistor ( Tdown_touch) may be further included.

Here, the control signal TSC applied to the gate node of the touch-only pull-down transistor Tdown is a signal that controls the timing at which the load-free driving signal LFD_gate should be applied to the gate line.

As described above, by implementing the load-free driving using the touch-only pull-down transistor Tdown, deterioration of the pull-down transistor Tdown due to the load-free driving can be prevented.

18 and 9, as in FIG. 5, during the display mode time, the two pull-down transistors Tdown1 and Tdown2 are used to generate and output a low-level gate signal Vgate_low to be applied to the gate line. There are two modified structural diagrams for applying the load-free driving to the signal generating circuit unit 330 .

Referring to FIG. 18 , the gate signal generation circuit unit 330 of each of the plurality of gate driver integrated circuits (GDIC) included in the gate driver 130 generates a high level signal through the corresponding gate line during the display mode time within one frame time. A pull-up transistor Tup for outputting a gate signal and a low-level gate signal (Vgate_low_odd) are output to the corresponding gate line during the display mode time within the i-th frame (eg, odd frame) time, and the i-th frame (Example: odd frame) During the touch mode time within time, the first pull-down transistor Tdown1 that outputs the load-free driving signal (LFD_gate_odd) to the corresponding gate line and the i+1th frame (eg even frame) time During the display mode time, a low-level gate signal (Vgate_low_even) is output to the corresponding gate line, and during the touch mode time within the i+14th frame (eg, even frame) time, the load-free driving signal (LFD_gate_even) to the corresponding gate line .

That is, the first pull-down transistor Tdown1 and the second pull-down transistor Tdown2 are transistors that can be used in both the display mode and the touch mode.

Referring to FIG. 18 , the pull-up transistor Tup is electrically connected between the gate clock signal application node Ngclk and the gate signal output node Nout, and is turned on by the voltage of the Q node, The high-level voltage VGH in the high-level section of the signal GCLK may be output as a high-level gate signal to the gate signal output node Nout.

Referring to FIG. 18 , the first pull-down transistor Tdown1 is electrically connected between the gate signal output node Nout and the base voltage node Nvss, and is displayed in an i-th frame (eg, odd frame time). During the mode time, it is turned on by the voltage of the first QB node (the QB1 node) to output the low-level gate signal Vgate_low_odd to the gate signal output node Nout.

Also, the first pull-down transistor Tdown1 may output the load-free driving signal LFD_gate_odd to the gate signal output node Nout during the touch mode time within the i-th frame (eg, odd frame time).

Referring to FIG. 18 , the second pull-down transistor Tdown2 is electrically connected between the gate signal output node Nout and the base voltage node Nvss, and the i+1th frame (eg, even frame time) During the display mode time, it is turned on by the voltage of the second QB node (the QB2 node) to output the low-level gate signal Vgate_low_even to the gate signal output node Nout.

In addition, the second pull-down transistor Tdown2 may output the load-free driving signal LFD_gate_even to the gate signal output node Nout during the touch mode time within the i+1th frame (eg, even frame time). there is.

As described above, during the display mode time and the touch mode time, the two pull-down transistors Tdown1 and Tdown2 are alternately used every frame, thereby distributing the deterioration degree of the transistors.

Meanwhile, in the case of FIG. 18, as in FIG. 18, during the touch mode time within the odd frame time, the first pull-down transistor Tdown1 that outputs the load-free driving signal LFD_gate_odd and the touch mode time within the even frame time , when the second pull-down transistor Tdown2 outputting the load-free driving signal LFD_gate_even is different from the load-free driving signal LFD_gate_odd output from the first pull-down transistor Tdown1 and the second pull-down A slight difference may occur between the load-free driving signal LFD_gate_even output from the transistor Tdown2, so that parasitic capacitance may not be completely removed.

Referring to FIG. 19 , the gate signal generating circuit unit 330 of each of the plurality of gate driver integrated circuits (GDIC) included in the gate driver 130 transmits a high level signal to the corresponding gate line during the display mode time within one frame time. A pull-up transistor Tup for outputting a gate signal, and a first pull-up transistor for outputting a low-level gate signal (Vgate_low_odd) to the corresponding gate line during the display mode time within the i-th frame (eg, odd frame) time a down transistor Tdown1 and a second pull-down transistor Tdown1 that outputs a low-level gate signal Vgate_low_even to the corresponding gate line during the display mode time within the i+1th frame (eg, even frame) time; , and a control circuit unit (C/C) for controlling charging and discharging of the Q node and the QB node.

That is, the first pull-down transistor Tdown1 and the second pull-down transistor Tdown2 are transistors that alternately operate for each frame only during the display mode time.

Referring to FIG. 19 , the gate signal generating circuit unit 330 of each of the plurality of gate driver integrated circuits GDIC included in the gate driver 130 is disposed between the gate signal output node Nout and the base voltage node Nvss. It may further include a touch-only pull-down transistor Tdown_touch that is electrically connected and outputs the load-free driving signal LFD_gate to the gate signal output node Nout during the touch mode time within each frame time.

As in FIG. 19, since the load-free driving signal LFD_gate is output using one touch-only pull-down transistor Tdown_touch during all frame times, as in FIG. 18, touch mode time within the odd frame time It is possible to solve the problem that parasitic capacitance is not completely eliminated due to the difference between the load-free driving signal LFD_gate that may be generated by using other pull-down transistors in the touch mode time within the even frame time.

According to the present exemplary embodiments as described above, it is possible to provide a gate driving method, the gate driver 130 , and the display device 100 capable of reducing power consumption.

According to the present exemplary embodiments, it is possible to provide a gate driving method using a gate clock signal, the gate driver 130 , and the display device 100 capable of reducing power consumption.

According to the present embodiments, when a display panel with a built-in touch panel is included, it is possible to provide the display device 100 capable of increasing sensing accuracy by preventing the formation of parasitic capacitors.

The above description and the accompanying drawings are merely illustrative of the technical spirit of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driver
130: gate driver
140: timing controller

Claims (12)

a display panel on which a plurality of gate lines are disposed; and
A gate driver generating a gate signal based on a gate clock signal in which a high-level section having a high-level voltage corresponding to a constant voltage and a low-level section having a high impedance level are repeated and outputting a gate signal to the corresponding gate line;
Each of the plurality of gate driver integrated circuits included in the gate driver,
Fully connected between the gate clock signal application node and the gate signal output node electrically connected to the gate line, turned on by the voltage of the Q node, and outputting a high-level gate signal to the gate signal output node up transistor,
a pull-down transistor electrically connected between the gate signal output node and a base voltage node and turned on by the voltage of the QB node to output a low-level gate signal to the gate signal output node;
The high-level gate signal has the high-level voltage corresponding to the constant voltage in the high-level section of the gate clock signal, and the low-level gate signal has the high level in the low-level section of the gate clock signal. having a base voltage different from the impedance level,
The size of the pull-down transistor outputting the low-level gate signal is larger than a size of the pull-up transistor outputting the high-level gate signal. According to claim 1,
The gate clock signal is
A signal obtained by changing a clock signal in which the high-level section of the high-level voltage and the low-level section of the low-level voltage are repeated,
The high-level section is the high-level voltage, and the low-level section is a signal changed from the low-level voltage to the voltage-floating high-impedance level. delete According to claim 1,
The pull-down transistor is
During the display mode time, output a low level gate signal to the gate signal output node,
A display device configured to output a load-free driving signal to the gate signal output node during a touch mode time. According to claim 1,
Each of the plurality of gate driver integrated circuits,
and a touch-only pull-down transistor electrically connected between the gate signal output node and a base voltage node and configured to output a load-free driving signal to the gate signal output node during a touch mode time. According to claim 1,
In each of the plurality of gate driver integrated circuits included in the gate driver, the pull-down transistor comprises:
A first pool electrically connected between the gate signal output node and a base voltage node and turned on by the voltage of the first QB node during an odd frame time to output a low-level gate signal to the gate signal output node - with a down transistor;
A second pool electrically connected between the gate signal output node and the base voltage node and turned on by the voltage of the second QB node during an even frame time to output a low-level gate signal to the gate signal output node - A display device including a down transistor. 7. The method of claim 6,
The first pull-down transistor,
outputting a low-level gate signal to the gate signal output node for a display mode time within the odd frame time, and outputting a load-free driving signal to the gate signal output node for a touch mode time within the odd frame time;
The second pull-down transistor,
A display device configured to output a low-level gate signal to the gate signal output node during a display mode time within the even frame time, and output a load-free driving signal to the gate signal output node during a touch mode time within the even frame time . 7. The method of claim 6,
Each of the plurality of gate driver integrated circuits,
and a touch-only pull-down transistor electrically connected between the gate signal output node and a base voltage node and configured to output a load-free driving signal to the gate signal output node during a touch mode time. According to claim 1,
Further comprising a plurality of touch electrodes disposed on the display panel and a plurality of signal lines connected to the plurality of touch electrodes,
In the touch mode, while a touch driving signal is applied to the plurality of touch electrodes,
The gate driver is
A display device for outputting a load-free driving signal corresponding to the touch driving signal to a corresponding gate line. 10. The method of claim 9,
Each of the plurality of touch electrodes,
During the display mode time, a common voltage is applied through the corresponding signal line,
A display device that is a common electrode to which a touch driving signal is applied through a corresponding signal line during a touch mode time. a clock signal input unit receiving a clock signal in which a high level voltage and a low level voltage corresponding to a constant voltage are repeated;
a clock signal changing unit changing a low level section of the clock signal from a low level voltage to a high impedance level to generate a gate clock signal in which a high level section having the high level voltage and a low level section having the high impedance level are repeated; and
a gate signal generating circuit unit for generating a gate signal based on the gate clock signal and outputting it to a gate line;
Each of the plurality of gate driver integrated circuits included in the gate signal generating circuit unit,
Fully connected between the gate clock signal application node and the gate signal output node electrically connected to the gate line, turned on by the voltage of the Q node, and outputting a high-level gate signal to the gate signal output node up transistor,
a pull-down transistor electrically connected between the gate signal output node and a base voltage node and turned on by the voltage of the QB node to output a low-level gate signal to the gate signal output node;
the high-level gate signal has the high-level voltage corresponding to the constant voltage in the high-level section of the gate clock signal;
The low-level gate signal has a base voltage different from the high impedance level in the low-level section of the gate clock signal,
The size of the pull-down transistor outputting the low-level gate signal is larger than a size of the pull-up transistor outputting the high-level gate signal. A method for driving a gate of a display device comprising: a display panel having a plurality of gate lines disposed thereon; and a gate driver driving the plurality of gate lines, the method comprising:
generating, by the gate driver, a gate signal based on a gate clock signal in which a high level section having a high level voltage corresponding to a constant voltage and a low level section having a high impedance level are repeated; and
outputting, by the gate driver, the gate signal to a corresponding gate line;
Each of the plurality of gate driver integrated circuits included in the gate driver,
Fully connected between the gate clock signal application node and the gate signal output node electrically connected to the gate line, turned on by the voltage of the Q node, and outputting a high-level gate signal to the gate signal output node up transistor,
a pull-down transistor electrically connected between the gate signal output node and a base voltage node and turned on by the voltage of the QB node to output a low-level gate signal to the gate signal output node;
the high-level gate signal has the high-level voltage corresponding to the constant voltage in the high-level section of the gate clock signal;
The low-level gate signal has a base voltage different from the high impedance level in the low-level section of the gate clock signal,
The size of the pull-down transistor outputting the low-level gate signal is larger than a size of the pull-up transistor outputting the high-level gate signal.

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