KR102396398B1 - Digital Low Dropout Voltage Regulator using Single-VCO based Edge-Racing Time Quantizer - Google Patents

Abstract

A digital low-dropout voltage regulator using a single VCO-based edge lacing time quantizer and a method of operation thereof are presented. The digital low-dropout voltage regulator using a single VCO-based edge lacing time quantizer proposed in the present invention includes an even number of a plurality of delay cells, of which half of the delay cells are controlled by a reference voltage, and the other half The delay cell of the SVER TQ (Single Voltage Controlled Oscillator based Edge-Racing Time Quantizer) is controlled by the output voltage and outputs racing result information by comparing the reference voltage and the output voltage. M _P -control logic outputting a value for controlling coarse switching and fine switching, M _P - a plurality of unary arrays performing coarse switching according to a control value of the control logic and MP _-a plurality of binary arrays performing fine switching according to the control value of the control logic.

Description

Digital Low Dropout Voltage Regulator using Single-VCO based Edge-Racing Time Quantizer

The present invention relates to the field of voltage regulators, and more particularly, to a voltage regulator having a digital low-dropout (LDO) characteristic.

Recent system on chip (SoC) needs to show high energy efficiency and to operate stably even when the input voltage is reduced to 0.5V. Digital LDO voltage regulators are widely used for these modern SoCs.

In designing a digital LDO voltage regulator, it is very important to determine how to quantize the error because the error included in the output voltage determines the transient response of the output voltage and the accuracy in steady state. Voltage quantizers play an important role in determining overall performance, such as fast calibration speed and accuracy. Voltage comparators are often used to improve transient response. For example, 1-bit voltage comparators are widely used as voltage quantizers. Since the 1-bit voltage comparator requires a clock signal with a high sampling frequency to improve the calibration speed, there is a disadvantage in that power consumption is greatly increased.

To solve this problem, a settling time may be reduced by employing a binary search engine using binary-weighted passtransistors. However, even if the change in load current slightly deviates from the threshold, the binary search engine must restart at the most significant bit (MSB). Because of this, digital voltage regulators employing binary search engines have large voltage spikes during calibration.

As another example, a multi-bit analog-to-digital converter (ADC) can be used as a voltage quantizer to expedite transient response by providing multi-bit information about the error in the output voltage. ADC-based LDO voltage regulators quantize the output voltage into a multi-bit code only when a change in the output voltage occurs. Therefore, it is possible to have a fast calibration speed while minimizing power consumption in a steady state.

However, since a large number of bits are required to achieve high accuracy of output voltage calibration, power and design complexity are increased. In addition, since performance of both voltage quantizers is highly dependent on the level of the supply voltage, it is difficult to reliably operate at a low supply voltage. Therefore, there is a limit to realizing fast calibration speed and high calibration accuracy with low power and low design complexity at a low supply voltage with the existing voltage quantizer.

The technical task of the present invention is to dynamically change the sampling frequency of a clock signal so that the LDO consumes power and quickly and accurately corrects the output voltage error in the standby state, thereby ensuring stable performance even at a low supply voltage. To provide a digital low-dropout voltage regulator using an edge-lacing time quantizer. In addition, by varying the sampling frequency according to the difference between the output voltage and the reference voltage, it is possible to quickly compare voltages with low power, and by sharing and using the same VCO for comparison of input and output voltages, physical local discrepancies ( To provide a digital LDO regulator that can improve accuracy by minimizing local mismatch).

In one aspect, the digital low-dropout voltage regulator using a single VCO-based edge lacing time quantizer proposed in the present invention includes an even number of a plurality of delay cells, and half of the delay cells among the plurality of delay cells are controlled by a reference voltage. Controlled, the other half of the delay cells are controlled by the output voltage, and the SVER TQ (Single Voltage Controlled Oscillator based Edge-Racing Time Quantizer) that compares the reference voltage and the output voltage and outputs the racing result information received input from SVER TQ M _P -control logic that outputs a value for controlling coarse switching and fine switching according to the racing result information, M _P - a plurality of unarys that perform coarse switching according to the control value of the control logic It includes an array (unary array) and a plurality of binary arrays that perform fine switching according to a control value of _MP -control logic.

In SVER TQ, each delay cell contains two inverters and three switches, and the three switches are controlled by RC (Racing Controller) according to the racing state, to reduce local mismatch between delay cells. The connection of each delay cell and the reference voltage and the output voltage rotates along the reference edge and the output edge so that the reference edge and the output edge pass through all delay cells equally. A reference edge according to an embodiment of the present invention means an edge controlled by a reference voltage, and an output edge means an edge controlled by an output voltage.

SVER TQ has a first lacing state in which all delay cells are initialized to ground (GND), a second lacing state in which a reference edge and an output edge are applied to two opposing output nodes among a plurality of delay cells, a reference edge and an output edge. A third racing state moving through the delay cell at different rates determined by the reference voltage and the output voltage, respectively, and the distance between the two edges decreases, closer than one delay cell from the initial value, the current race ends It operates with four states including the final racing state, and after the final racing state, the racing state returns to the first racing state, and the next race normalizes the delay of all delay cells, starting from the node where the previous race ended.

When the distance between two edges decreases, closer than one delay cell from the initial value, the final racing state where the current race ends is determined whether the current output voltage is greater or less than the reference voltage by detecting the earlier edge. In order to adjust the error of the output voltage using the judgment result, the sampling frequency automatically increases as the difference between the output voltage and the reference voltage increases. is decided,

f _SP|MAX = N/2 Max (f _REF , f _OUT )

Here, f _SP|MAX is the maximum sampling frequency, Max(f _REF , f _OUT ) is the moving frequency of the earliest edge among the two edges, and N is the number of delay cells.

RC (Racing Controller) controls the switch for delay cell connection, the switch for pull-up to VDD, and the switch for pull-down to GND according to the position of the two edges, and the connection of the delay cell to the reference voltage and the output voltage is the reference edge and control the control voltage switches of both inverters to rotate with the output edge, respectively, to determine whether to complete or continue the current race by checking the logic level of the delay cell input where the reference edge and the output edge are opposite. .

In another aspect, the method of operating a digital low voltage drop voltage regulator using a single VCO-based edge racing time quantizer proposed in the present invention is SVER TQ (Single Voltage Controlled Oscillator based Edge-Racing) including an even number of a plurality of delay cells. Time quantizer), half of the delay cells of the plurality of delay cells are controlled by the reference voltage, the other half of the delay cells are controlled by the output voltage, and outputting racing result information by comparing the reference voltage and the output voltage. , MP - Outputting values for controlling coarse switching and fine switching according to the racing result information input from _SVER TQ through the control logic, a plurality of unary arrays _MP - performing coarse switching according to the control value of the control logic and performing fine switching by a plurality of binary arrays according to the control value of the MP _-control logic.

Since the SVER time quantizer according to embodiments of the present invention uses only one VCO rather than comparing two voltages to generate a sampling frequency, a physical local mismatch according to the distance between semiconductor devices is completely eliminated. can be removed, so that the calibration accuracy of the output voltage can be improved, and the accuracy of the output voltage calibration of the digital LDO voltage regulator can be firmly maintained even for frequency pulling. In addition, since the proposed VCO operates stably at a low supply voltage, it is possible to prevent operation instability occurring in the existing structure. In the case of the LDO voltage regulator according to the embodiment of the present invention, since the error of the output voltage and the calibration speed are proportional, the calibration speed can be increased without consuming much power. In addition, since the SVER can distinguish one delay-cell difference, the maximum sampling frequency value may be greater than N/2 times the reference frequency of the reference voltage (where N is the number of delay-cells of the VCO).

1 is a diagram illustrating a single VCO-based edge lacing time quantizer (SVER TQ) according to an embodiment of the present invention.
2 is a diagram illustrating a delay cell having a switch of a VCO according to an embodiment of the present invention.
3 is a diagram for explaining the operation of the SVER according to an embodiment of the present invention.
4 shows the overall architecture of the proposed digital LDO using SVER TQ according to an embodiment of the present invention.
5 is a diagram showing the implementation of three functions of RC according to an embodiment of the present invention.
6 is a diagram for comparing the delay cell of the VCO in the SVER TQ according to an embodiment of the present invention and the TQ of the prior art.
7 is a diagram illustrating a simulation according to an embodiment of the present invention and Min[VDIFF] of Equation (1).
8 is a diagram illustrating a transient response measured according to an embodiment of the present invention.
9 is a diagram illustrating measured load adjustment and line adjustment, respectively, according to an embodiment of the present invention.

Digital Low-Dropout (LDO) voltage regulators using a Single Voltage Controlled Oscillator based Edge-Racing Time Quantizer (SVER TQ) provide fast transient response and high accuracy of the output voltage. designed to achieve The sampling frequency generated by the SVER TQ is dynamically scaled according to the magnitude of the error in the output voltage, thus improving transient response without increasing power consumption in steady state. In the case of SVER TQ, the two applied edges pass through all delay cells of a single VCO equally, so that mismatch between delay cells does not degrade the accuracy of regulation. The proposed digital LDO is fabricated in 65nm CMOS process and occupies a silicon area of 0.0488mm ² . In measurement, the proposed digital LDO achieves 0.29ps transient FOM and less than 2mV accuracy from a 0.5V supply. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In modern mobile systems on chips (SoCs), low-dropout (LDO) regulators are essential to provide optimal levels of supply voltages to each building component. Unlike conventional analog LDOs, digital LDOs can provide more stable operation when the V _IN value is low [1]-[11]. For these digital LDOs, voltage quantizers (VQ) play an important role in determining overall performance, such as transient response and accuracy of regulation. Although 1-bit voltage comparators (VC) are widely used [1]-[5], it is necessary to increase the sampling frequency f _SP to improve the transient response, which greatly increases the power consumption [1]-[3]. To solve this problem, [4] and [5] propose Binary Search Engines (BSE). However, since the BSE has to restart at the MSB, these digital LDOs have large voltage spikes even if the change in load current I _L slightly exceeds the threshold. The LDOs in [6]-[8] use an event-driven method with multi-bit analog-to-digital converters (ADC). The ADC quantizes the output voltage V _OUT into a multi-bit code only when V _OUT changes, allowing fast transient response while minimizing power consumption at steady state. However, high accuracy of V _OUT requires a large number of ADC bits, which creates another trade-off between accuracy and power/design complexity.

To solve the problem related to VQ, Voltage Controlled Oscillator (VCO)-based Time Quantizers (TQ) are presented in [9] and [10]. Because the frequency of the VCO is adjusted according to the magnitude of V _OUT , the inherent benefits of adaptive sampling are provided, which naturally eliminates the trade-off between transient response and power consumption. Another advantage is that the accuracy of V _OUT can be improved as the number of cycles of the VCO (N _CYCLE ) increases because the error of V _OUT is amplified in the time domain. Despite the obvious benefits identified above, the old VCO-based TQ still has serious problems. TQ in [9] uses the bit frequency of two duplicate VCOs controlled by the reference voltage, V _REF and V _OUT . However, the unavoidable difference between the frequencies of the two VCOs due to local mismatch limits the accuracy of voltage regulation. Also, using the bit frequency, the maximum f _SP of TQ in [9] was limited to f _REF /2, and no polarity information was available. Another VCO-based TQ is not for LDO, but is presented in [10]. This TQ has two rising edges, ED _REF and ED _OUT , controlled by different voltages V _REF and V _OUT on a single VCO. These two edges must meet because they are traveling at different speeds, resulting in a reduced pulse at the output. TQ uses a single VCO, but the accuracy of quantization is still limited due to local mismatch. This is because the delay cell's connection to the control voltage is fixed (i.e. odd inverters are connected to V _REF and even inverters are connected to V _OUT ), so the rising edge of ED _REF only passes through the odd inverter and the rising edge of ED _OUT is even Only the inverter passes through. Also, the maximum f _SP is limited by Max(f _REF , f _OUT ) since the decision must be delayed until the pulse is reduced.

In the present invention, we propose a single VCO-based edge lacing time quantizer (SVER TQ), which dynamically expands f _SP so that the digital LDO can achieve fast transients while consuming only a small amount of power [11].

1 is a diagram illustrating a single VCO-based edge lacing time quantizer (SVER TQ) according to an embodiment of the present invention.

As can be seen in the conceptual diagram of FIG. 1 , one half of the delay cell 110 is connected to V _REF and the other half 120 of the delay cell is connected to V _OUT , and the connections between the delay cell and V _REF and V _OUT are respectively ED _REF and V OUT . It rotates along ED _OUT . Therefore, ED _REF and ED _OUT pass through all delay cells of the VCO equally, so that SVER TQ can achieve high accuracy despite local mismatch between delay cells. When the distance between ED _REF and ED _OUT is reduced by two or more delay cells, the racing ends and the Racing Controller (RC) generates a new rising edge of the clock signal. Thus, the maximum sampling frequency f _SP reaches N/2·Max (f _REF , f _OUT ), where N is the number of delay cells in the VCO. SVER can also provide more information such as polarity and voltage error magnitude without additional circuitry.

The reference edge ED _REF according to an embodiment of the present invention means an edge controlled by the reference voltage V _REF , and the output edge ED _OUT means an edge controlled by the output voltage V _OUT .

2 is a diagram illustrating a delay cell having a switch of a VCO according to an embodiment of the present invention.

The proposed VCO of SVER TQ consists of 12 delay cells composed of two inverters 211 and 212 and switches SW _SE <k>, SW _PU <k> and SW _PD <k>, respectively, as shown in FIG. 2 . . The control voltage V _C <k> of the two inverters in the k-th delay cell (0 ≤ k ≤ 11) can be connected to either V _REF or V _OUT via SW _VC <k>. The output of the k-th delay cell has three switches controlled by RC depending on the racing state: SW _SE <k> for connecting the next delay cell, SW _PU <k> for pull-up to VDD, SW for pull-down to GND have _PD <k>.

3 is a diagram for explaining the operation of the SVER according to an embodiment of the present invention.

3 shows a four-step operation of SVER TQ according to an embodiment of the present invention.

The first racing state 310 is INIT, and all output nodes of the delay cell are initialized to GND by turning on all SW _SE <k> and all SW _PD <k>.

Then, in the second racing state 320, R-START, the two edges of ED _OUT and ED _REF are applied to opposite output nodes of the delay cell. In the case of FIG. 2 , the application nodes are D<0> and D<6>, and SW _PU <0> and SW _PU <6> are temporarily closed to apply ED _OUT and ED _REF , respectively. In this state, the three delay cells before and three delay cells after each application node are connected to the corresponding control voltage of V _OUT or V _REF . Also, SW _SE <5> and SW _SE <11> are open, SW _PU <5> and SW _PU <11> are closed, and SW _PD <0>, SW _PD <1>, SW _PD <6> and SW _PD <7> are open.

In the third racing state 330 RACING, ED _OUT and ED _REF travel through the delay cell at different rates determined by V _OUT and V _REF , respectively. During racing, SW _VC <k> continues to dynamically switch to the corresponding control voltage, V _REF or V _OUT , before either ED _OUT or ED _REF arrives. As the racing progresses, the distance between the two edges gets closer due to the difference between V _OUT and V _REF .

When the distance decreases by more than one delay cell from the initial value (the levels of all output nodes D<0> to D<11> are continuously monitored by the RC), the current race is stopped and the racing state returns to the final racing state ( 340) becomes R-STOP. The RC (Racing Controller) generates three types of information. 1) new rising edge of CK _SP ; 2) the number of delay cells passed by the faster edge N _TD ; and 3) polarity information P.

Thereafter, the racing state returns to the INIT 310 , and the next race starts from the node where the previous race has ended, and has the effect of normalizing the delay of all delay cells.

4 shows the overall architecture of the proposed digital LDO using SVER TQ according to an embodiment of the present invention.

Referring to FIG. 4( a ), the pass transistor M _P s consists of two arrays: 1) a 31-unary array 430 for coarse switching and 2) 8-binary array 440 for fine switching. The SVER TQ 410 compares V _OUT and _{V REF} and transmits the racing result information to the MP -control logic 420 .

FIG. 4( b ) is a diagram illustrating a state diagram of the _MP -control logic 420 according to coarse switching 450 and fine switching 460 .

When the rising edges of N _TD , _P , and CK _SP are transmitted by SVER TQ (410), the MP -control logic calculates K _GAIN (as in the table of Fig. 4(b)) and EN _FINE to calculate the _MP s control the switch of When I _L is changed, the error of V _OUT decreases N _TD and increases K _GAIN . If K _GAIN is greater than 1, SW _C <30 : 0> value is changed by P·K _GAIN . If f _SP is increased, the operating speed in the transient state can be increased.

When the error of V _OUT decreases, N _TD increases and the P·K _GAIN value changes back and forth between 1 and -1. After that, the MP _-control logic 420 returns to the Fine Switching state. In this state, after binary search, fine adjustment of S _WF <7: 0> is performed until _IL is changed.

4 (c) is a view showing a chip manufactured according to an embodiment of the present invention. The proposed digital LDO using SVER TQ was fabricated in 65nm CMOS technology as shown in Fig. 4(c). The chip was tested on a printed circuit board (PCB) after wire bonding. The digital LDO according to an embodiment of the present invention occupies an active area of 0.0488 mm ² .

5 is a diagram showing the implementation of three functions of RC according to an embodiment of the present invention.

FIG. 5(a) is a diagram for explaining SW _SE , SW _PU , and SW _PD control, FIG. 5(b) is SW _VC control, and FIG. 5(c) is a view for explaining the generation of a racing result.

The first function in Fig. 5(a) is to control the connection of the output node of the delay cell, SW _SE <k>s, SW _PU <k>s, and SW _PD <k depending on the position of the two lacing edges as follows: Switch >s. When one edge ED _X (ED _OUT or ED _REF ) moves from D<k-1> to D<k>, SW _SE <k-1> turns off and SW _PU <k-1> turns on. Then, SW _PD <k + 1> is turned off before ED _X reaches D<k + 1> so as not to impede the movement of ED _X. Figure 5(b) shows the SW _VC control logic that causes the connection of the delay cell to V _REF and V _OUT to rotate with ED _REF and ED _OUT respectively. The point to note here is that V _C <11: 0> should transition to the next control voltage much faster than the edge. In this logic, the timing margin is set to 3 delay cells, but if a higher f _SP is needed for stable operation, this margin should be increased. In the example of Fig. 5(b), when ED _REF and ED _OUT are at D <6> and D <0>, V _C <4 : 9> is connected to V _REF and V _C <0 : 3> and V _C < 10 : 11> is connected to V _OUT . When ED _REF and ED _OUT move to the next output, V _C <4> and V _C <10> switch to V _OUT and V _REF respectively. This feature is important to make the proposed SVER robust against local mismatch by allowing both edges to pass through all delay cells equally. A third function, shown in Figure 5(c), produces a racing result. Determines whether to complete or continue the current race by checking the logic level of the delay cell input encountered by ED _REF and ED _OUT . If V _OUT is higher than V _REF , ED _OUT moves faster than ED _REF . As the race progresses, as the time difference increases, ED _OUT has already reached D<6>, but ED _REF is still rising from D<11>, so D<11> is sampled to zero. This creates a new rising edge of CK _SP and the racing state moves to R-STOP, creating N _TD and P.

6 is a diagram for comparing the delay cell of the VCO in the SVER TQ according to an embodiment of the present invention and the TQ of the prior art.

Monte-Carlo (MC) simulations were performed to compare the mismatch effect between the delay cell of VCO and the proposed SVER TQ in the TQ of prior art [9] and [10]. For a fair comparison, each VCO of the three TQs was designed with the same number of identical inverters with the same control voltage applied. In [9], two rising edges were applied to the same node of the two VCOs for the TQ simulation using two duplicate VCOs. [10] and in the case of TQ using a single VCO of the present invention, two rising edges were applied to two opposing nodes of the VCO. Then, for each TQ, the travel time difference (τ _DIFF ) of the two edges after the same N _CYCLE was measured. 6 shows the τ _DIFF distribution of three TQs when N _CYCLE is fixed to 5. The 1-sigma (σ) of SVER TQ is 17ps, which is more than 83 times smaller than the other two TQs. This result means that SVER TQ can achieve much higher accuracy for local mismatch between delay cells. Fig. 6 also shows that 1σ is similar to the duplicate VCO-based TQ of [9], although [10] used a single VCO-based TQ. This is because the two edges of TQ in [10] have shifted a completely different set of delay cells of the VCO. In the present invention, the effect of mismatch between delay cells may limit the accuracy of the LDO, especially when the difference between V _REF and V _OUT is very small. However, if the difference becomes too small, the effects of mismatches between delay cells are normalized and canceled out, as the two edges have to go through all delay cells multiple times before the lacing is finished, and regulation accuracy is not compromised. One of the advantages of the proposed SVER TQ is that the ability to distinguish the difference (V _DIFF ) between V _OUT and V _REF is improved as N _CYCLE increases. SVER TQ can detect a time difference greater than one delay cell 1/(N·fVCO). where f _VCO is the frequency of the VCO controlled by the reference voltage. As N _CYCLE increases, SVER TQ can detect a smaller V _DIFF because the distance between ED _OUT and ED _REF due to the same V _DIFF is extended. The minimum V _DIFF , Min[V _DIFF ] according to N _CYCLE can be expressed as follows:

(1)

(One)

where f _SP|MAX is the maximum sampling frequency, Max(f _REF , f _OUT ) is the moving frequency of the earlier of the two edges, N is the number of delay cells, and K _VCO is the voltage versus frequency gain of the VCO.

7 is a diagram illustrating a simulation according to an embodiment of the present invention and Min[V _DIFF ] of Equation (1).

Here, f _VCO , N and K _VCO were set to 33 MHz, 12 and 265 MHz/V, respectively. 7 shows that Min[V _DIFF ] decreased as N _CYCLE increased, as expected. Even if Min[V _DIFF ] is small, if τ _DIFF due to mismatch between delay cells is too large, the resolution of SVER TQ is limited by τ _DIFF . However, as shown in Fig. 7, the boundary of V _DIFF set by 1σ of τ _DIFF in the MC simulation is about 70 μV. Therefore, when N _CYCLE is increased above 100, the resolution of SVER TQ can be safely lowered to less than 100 μV.

8 is a diagram illustrating a transient response measured according to an embodiment of the present invention.

V_OUT이 변경됨에 따라 적응적으로 스케일링되었다. 전환 순간에

V_OUT이 크면 f_SP가 증가하여 60MHz에 도달했다. 이러한 동적으로 스케일링된 f_SP로 인해 안정화 시간이 단축되어 V_OUT의 언더슈팅(undershooting) 및 오버슈팅(overshooting)을 각각 47mV 및 28mV 미만으로 제한 할 수 있다. 도 8(b)는 V_IN이 1.0V로 고정된 상태에서 I_L이 10mA에서 80mA로 변경되었을 때 측정된 과도 응답을 보여준다. V_OUT의 언더슈팅과 오버슈팅은 각각 30mV와 20mV였다. 도 8(b)의 오른쪽 부분은 동일한 설정으로 과도 상태에서의 시뮬레이션을 보여 주며, 피크 f_SP가 78MHz로 증가했음을 보여준다. The proposed digital LDO using SVER TQ in the present invention was fabricated in 65nm CMOS technology as shown in FIG. 4(c). The chip was tested on a printed circuit board (PCB) after wire bonding. The digital LDO occupies an active area of 0.0488mm ² . Fig. 8(a) shows the measured values of the load transient response when I _L is changed from 2.5 mA to 22.5 mA in a state where V _IN is fixed at 0.5 V. As shown on the right side of Fig. 8(a), the measured f _SP is

It scaled adaptively as V _OUT changed. at the moment of transition

When V _OUT was large, f _SP increased and reached 60 MHz. This dynamically scaled f _SP reduces settling time, limiting the undershooting and overshooting of V _OUT to less than 47mV and 28mV, respectively. 8(b) shows the measured transient response when I _L is changed from 10 mA to 80 mA while V _IN is fixed at 1.0 V. The undershooting and overshooting of V _OUT were 30mV and 20mV, respectively. The right part of Fig. 8(b) shows the simulation in the transient state with the same settings, showing that the peak f _SP increased to 78 MHz.

9 is a diagram illustrating measured load adjustment and line adjustment, respectively, according to an embodiment of the present invention.

Because the performance of SVER TQ was robust to local inconsistencies, the proposed LDO achieved very high accuracy. In FIG. 9(a) , when V _REF was 0.45V at a 50mV dropout voltage, the voltage error of _VOUT was less than 1.8mV at I _L of 0.1 to 100mA and V _REF of 0.45 to 0.95V. FIG. 9(b) shows that V _REF and I _L are fixed to 0.45V and 20mA, respectively, and the error of the output voltage is less than 1.9mV under the condition that _VIN is 0.5V to 0.75V. Table 1 compares the performance of the proposed digital LDO using SVER TQ with that of the state-of-the-art digital LDO using other quantizers.

The smallest DC load regulation and the highest FOM _TR were achieved in the proposed digital LDO using the SVER TQ according to the embodiment of the present invention.

The present invention proposes a high-speed transient and high-precision digital LDO using SVER TQ. Through the adaptive sampling property, the proposed SVER TQ can achieve fast transient response while using a small amount of power. Since the time difference of one delay cell can be distinguished, the peak f _SP is very high, and the transient response of the LDO is faster. Unlike the existing VCO-based TQ, the proposed SVER TQ can guarantee high accuracy because two lacing edges pass through all delay cells of a single VCO equally. The proposed SVER TQ can also provide information on the error magnitude and polarity of V _OUT without additional circuitry.

The device described above may be implemented as a hardware component, a software component, and/or a combination of the hardware component and the software component. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. A processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that can include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

Software may comprise a computer program, code, instructions, or a combination of one or more thereof, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or apparatus, to be interpreted by or to provide instructions or data to the processing device. may be embodied in The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

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Claims (10)

It includes an even number of a plurality of delay cells, among the plurality of delay cells, half of the delay cells are controlled by the reference voltage, the other half of the delay cells are controlled by the output voltage, and the race result is obtained by comparing the reference voltage and the output voltage SVER TQ (Single Voltage Controlled Oscillator based Edge-Racing Time Quantizer) that outputs information;
M _P -control logic that outputs values for controlling coarse switching and fine switching according to racing result information input from SVER TQ;
M _P - a plurality of unary arrays for performing coarse switching according to a control value of the control logic; and
M _P - A plurality of binary arrays that perform fine switching according to the control value of the control logic.
A digital low-dropout voltage regulator with a According to claim 1,
SVER TQ,
Each delay cell contains two inverters and three switches, and the three switches are controlled by RC (Racing Controller) according to the racing state,
To reduce local mismatch between delay cells, the connection of each delay cell to the reference voltage and output voltage is made to rotate along the reference edge and output edge so that the reference edge and output edge pass evenly through all delay cells.
Digital low-dropout voltage regulator. 3. The method of claim 2,
SVER TQ,
a first racing state in which all delay cells are initialized to ground (GND);
a second lacing state in which the reference edge and the output edge are applied to two opposing output nodes among the plurality of delay cells;
a third racing state in which the reference edge and the output edge travel through the delay cell at different rates determined by the reference voltage and the output voltage, respectively; and
When the distance between the two edges decreases, closer than one delay cell from the initial value, the final racing state where the current race ends
It operates in four states including
After the last racing state, the racing state goes back to the first racing state, and the next race normalizes the delays of all delay cells, starting at the node where the previous race ended.
Digital low-dropout voltage regulator. 4. The method of claim 3,
When the distance between the two edges decreases, closer than one delay cell from the initial value, the final racing state where the current race ends is,
By detecting the faster edge, it is determined whether the current output voltage is greater than or less than the reference voltage, and the sampling frequency is automatically increased as the difference between the output voltage and the reference voltage is greater, in order to use the judgment result to adjust the error of the output voltage, By detecting the distance between two edges in units of the number of delay cells, the maximum sampling frequency is determined according to the following formula,
f _SP|MAX = N/2 Max (f _REF , f _OUT )
where f _SP|MAX is the maximum sampling frequency, Max(f _REF , f _OUT ) is the moving frequency of the earliest edge among the two edges, and N is the number of delay cells.
Digital low-dropout voltage regulator. 3. The method of claim 2,
RC (Racing Controller) is,
Control the switch for delay cell connection, the switch for pull-up to VDD and the switch for pull-down to GND according to the position of the two edges,
controlling the control voltage switches of the two inverters so that the connection of the delay cell to the reference voltage and the output voltage rotates with the reference edge and the output edge respectively;
Control to determine whether to complete or continue the current race by checking the logic level of the input of the delay cell, where the reference edge and the output edge are opposite.
Digital low-dropout voltage regulator. Through SVER TQ (Single Voltage Controlled Oscillator based Edge-Racing Time Quantizer) including an even number of a plurality of delay cells, half of the delay cells among the plurality of delay cells are controlled by the reference voltage, and the other half delay cells are output voltage Controlled by, outputting the racing result information by comparing the reference voltage and the output voltage;
M _P - outputting a value for controlling coarse switching and fine switching according to the racing result information input from SVER TQ through the control logic;
performing, by a plurality of unary arrays, coarse switching according to a control value of MP _-control logic; and
A plurality of binary arrays performing fine switching according to the control value of M _P -control logic
A digital low-dropout voltage regulator operating method comprising a. 7. The method of claim 6,
With SVER TQ including a plurality of delay cells, half of the delay cells among the plurality of delay cells are controlled by the reference voltage, and the other half delay cells are controlled by the output voltage, and the reference voltage and the output voltage are compared to race The step of outputting the result information is,
The three switches of each delay cell, including two inverters and three switches, are controlled by the RC (Racing Controller) according to the racing state,
To reduce local mismatch between delay cells, the connection of each delay cell and reference voltage and output voltage is rotated along the reference edge and output edge so that the reference edge and output edge pass evenly through all delay cells.
How a digital low-dropout voltage regulator works. 8. The method of claim 7,
With SVER TQ including a plurality of delay cells, half of the delay cells among the plurality of delay cells are controlled by the reference voltage, and the other half delay cells are controlled by the output voltage, and the reference voltage and the output voltage are compared to race The step of outputting the result information is,
a first racing state in which all delay cells are initialized to ground (GND);
a second lacing state in which the reference edge and the output edge are applied to two opposing output nodes among the plurality of delay cells;
a third racing state in which the reference edge and the output edge travel through the delay cell at different rates determined by the reference voltage and the output voltage, respectively; and
When the distance between the two edges decreases, closer than one delay cell from the initial value, the final racing state where the current race ends
It operates in four states including
After the last racing state, the racing state goes back to the first racing state, and the next race normalizes the delays of all delay cells, starting at the node where the previous race ended.
How a digital low-dropout voltage regulator works. 9. The method of claim 8,
When the distance between the two edges decreases, closer than one delay cell from the initial value, the final racing state where the current race ends is,
By detecting the faster edge, it is determined whether the current output voltage is greater than or less than the reference voltage, and the sampling frequency is automatically increased as the difference between the output voltage and the reference voltage is greater, in order to use the judgment result to adjust the error of the output voltage, By detecting the distance between two edges in units of the number of delay cells, the maximum sampling frequency is determined according to the following formula,
f _SP|MAX = N/2 Max (f _REF , f _OUT )
where f _SP|MAX is the maximum sampling frequency, Max(f _REF , f _OUT ) is the moving frequency of the earliest edge among the two edges, and N is the number of delay cells.
How a digital low-dropout voltage regulator works. 8. The method of claim 7,
RC (Racing Controller) controls a switch for delay cell connection, a switch for pull-up to VDD, and a switch for pull-down to GND according to the positions of the two edges,
controlling the control voltage switches of the two inverters so that the connection of the delay cell to the reference voltage and the output voltage rotates with the reference edge and the output edge respectively;
Control to determine whether to complete or continue the current race by checking the logic level of the input of the delay cell, where the reference edge and the output edge are opposite.
How a digital low-dropout voltage regulator works.

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