KR102390963B1 - Display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a display device capable of improving bonding force between an encapsulation unit and a substrate, and a method for manufacturing the same, comprising: a substrate; a pixel circuit unit positioned on the substrate and having a first hole; a light blocking film positioned on the pixel circuit unit and having a second hole positioned to correspond to the first hole; a light emitting layer positioned on the pixel circuit unit to correspond to a light emitting area defined by the light blocking film; and a sealing portion on the light-shielding film; The substrate may include: a first layer having a groove corresponding to the first hole; and a second layer positioned between the first layer and the pixel circuit portion and having a third hole positioned between the groove and the second hole; The sealing part may include a cover part positioned on the light shielding film; and an extension part extending from the cover part and inserted into the first hole, the second hole, the third hole, and the groove; The groove has a greater width than the third hole.

Description

Display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device capable of improving a bonding force between an encapsulation unit and a substrate, and a method of manufacturing the same.

The flat panel display has advantages of reducing weight and volume, which are disadvantages of a cathode ray tube. As such a flat panel device, a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display device (Organic Light Emitting Display Device), etc. There is this.

Among flat panel displays, an organic light emitting diode display displays an image using an organic light emitting diode that generates light by recombination of electrons and holes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of improving a bonding force between an encapsulation unit and a substrate, and a method for manufacturing the same.

According to an aspect of the present invention, there is provided a display device comprising: a substrate; a pixel circuit unit positioned on the substrate and having a first hole; a light blocking layer disposed on the pixel circuit unit and having a second hole positioned to correspond to the first hole; a light emitting layer positioned on the pixel circuit unit to correspond to a light emitting area defined by the light blocking film; and a sealing portion on the light-shielding film; The substrate may include: a first layer having a groove corresponding to the first hole; and a second layer positioned between the first layer and the pixel circuit unit and having a third hole positioned between the groove and the second hole; The sealing part may include a cover part positioned on the light blocking film; and an extension part extending from the cover part and inserted into the first hole, the second hole, the third hole, and the groove; The groove has a greater width than the third hole.

The groove has a width that gradually increases in a direction from the first layer toward the second layer.

At least one of the opposite inner walls of the groove is inclined at an angle with respect to an interface between the first layer and the second layer.

An angle between at least one of the inner walls of the groove facing each other and the interface is an obtuse angle.

In plan view, the third hole is surrounded by the groove.

The third hole and the groove overlap.

The first hole, the second hole, the third hole, and the groove are located in at least one of a display area and a non-display area of the substrate.

The first hole, the second hole, the third hole, and the groove are located in the display area and are located between the high potential line and the data line adjacent to each other.

The display device further includes a driving circuit unit positioned in the non-display area and connected to a scan line or a light emission control line of the pixel circuit unit.

the display device may further include a plurality of clock lines disposed in the non-display area and connected to the driving circuit unit; The first hole, the second hole, the third hole and the groove are located between adjacent clock lines.

One of the inner walls facing each other of the groove and one of the inner walls facing each other of the first hole are positioned in a straight line.

One of the first and second layers includes an organic material, and the other includes an inorganic material.

*

* In addition, a display device according to the present invention for achieving the above object includes: a substrate; a pixel circuit unit on the substrate; a light blocking layer disposed on the pixel circuit unit and having a first hole; a light emitting layer positioned on the pixel circuit unit to correspond to a light emitting area defined by the light blocking film; and a sealing portion on the light-shielding film; The pixel circuit unit may include: a first layer having a groove positioned to correspond to the first hole; a second layer positioned on the first layer and having a second hole positioned between the groove and the first hole; and a third layer located on the second layer and having a third hole located between the second hole and the first hole; The sealing part may include a cover part positioned on the light blocking film; and an extension part extending from the cover part and inserted into the first hole, the second hole, the third hole, and the groove; The groove has a greater width than the second hole.

The groove has a width that gradually increases in a direction from the first layer toward the second layer.

At least one of the opposite inner walls of the groove is inclined at an angle with respect to an interface between the first layer and the second layer.

An angle between at least one of the inner walls of the groove facing each other and the interface is an obtuse angle.

The first hole, the second hole, the third hole, and the groove are located in at least one of a display area and a non-display area of the substrate.

According to an aspect of the present invention, there is provided a method of manufacturing a display device, comprising: preparing a carrier substrate; sequentially forming a first layer and a second layer on the carrier substrate; forming a pixel circuit unit on the second layer; forming a light blocking film defining a light emitting area on the pixel circuit unit; forming a first hole penetrating the light blocking film; forming a second hole passing through the insulating film of the pixel circuit part and positioned to correspond to the first hole; forming a third hole passing through the second layer and positioned to correspond to the second hole; forming a groove in the first layer corresponding to the third hole and having a greater width than the third hole; and forming a sealing portion including a cover portion positioned on the light blocking film and an extension portion extending from the cover portion and buried in the first hole, the second hole, the third hole, and the groove.

The grooves are formed by oxygen dry etching or laser light.

The first layer comprises an organic material and the second layer comprises an inorganic material.

When the third hole is formed by selectively removing the second layer, the insulating layer of the bending portion of the display device is also removed.

A display device and a method for manufacturing the same according to the present invention provide the following effects.

According to the display device of the present invention, the sealing portion is coupled to the groove of the substrate or the pixel circuit portion. Accordingly, the bonding force between the sealing part and the substrate may be improved.

Also, a dead space of the display device of the display device may be minimized due to the improvement of the coupling force.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating an equivalent circuit for any one pixel shown in FIG. 1 .
FIG. 3 is a diagram illustrating a detailed plan view of a display device including any one pixel shown in FIG. 1 and lines connected thereto.
4A to 4G are views separately showing only some of the components of FIG. 3 .
5 is a cross-sectional view taken along line I-I' of FIG. 3 .
6 is a cross-sectional view taken along the line II-II' of FIG. 3 .
7 is an enlarged view of part A of FIG. 6 .
FIG. 8 is a detailed plan view of a display device including a plurality of pixels shown in FIG. 1 and lines connected thereto.
9 is a detailed configuration diagram of the scan driver of FIG. 1 .
10A to 10M are cross-sectional views illustrating a method of manufacturing a display device according to the present invention.
11 is a view for explaining a method of forming a groove using a laser.
12 is a cross-sectional view of another embodiment taken along the line II-II' of FIG. 3 .
13 is an enlarged view of part A of FIG. 12 .
14 is a cross-sectional view of another embodiment taken along the line II-II' of FIG. 3 .
15 is a cross-sectional view of another embodiment taken along the line II-II′ of FIG. 3 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Accordingly, in some embodiments, well-known process steps, well-known device structures, and well-known techniques have not been specifically described in order to avoid obscuring the present invention. Like reference numerals refer to like elements throughout.

In order to clearly express various layers and regions in the drawings, the thicknesses are enlarged. Throughout the specification, like reference numerals are assigned to similar parts. When a part, such as a layer, film, region, plate, etc., is “on” another part, it includes not only cases where it is “directly on” another part, but also cases where there is another part in between. Conversely, when we say that a part is "just above" another part, we mean that there is no other part in the middle. Also, when a part of a layer, film, region, plate, etc. is said to be "under" another part, it includes not only the case where it is "directly under" another part, but also the case where there is another part in the middle. Conversely, when a part is said to be "just below" another part, it means that there is no other part in the middle.

Spatially relative terms "below", "beneath", "lower", "above", "upper", etc. It can be used to easily describe the correlation between an element or components and other elements or components. The spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. For example, when an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above. The device may also be oriented in other orientations, and thus spatially relative terms may be interpreted according to orientation.

In the present specification, when a part is said to be connected to another part, this includes not only a case in which it is directly connected, but also a case in which it is electrically connected with another element interposed therebetween. In addition, when it is said that a part includes a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated.

In this specification, terms such as first, second, third, etc. may be used to describe various components, but these components are not limited by the terms. The above terms are used for the purpose of distinguishing one component from other components. For example, without departing from the scope of the present invention, a first component may be referred to as a second or third component, and similarly, the second or third component may also be alternately named.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

Hereinafter, a display device according to the present invention will be described in detail with reference to FIGS. 1 to 15 .

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1 , the display device 1000 of the present invention includes a substrate 100 , a scan driver 102 , a light emission control driver 103 , a data driver 104 , and a power supply unit 105 . .

On the above-described substrate 100 , i+2 scan lines SL0 to SLi+1, i light emission control lines EL1 to ELk, j data lines DL1 to DLj, i*j The pixels PX, the scan driver 102 , the emission control driver 103 , and the data driver 104 are located. Here, i, j and k are each a natural number greater than 1.

The plurality of pixels PX are located in the display area 100a of the substrate 100 .

i+2 scan lines SL0 to SLi+1, i light emission control lines EL1 to ELk, and j data lines DL1 to DLj are located in the display area 100a of the substrate 100 . do. In this case, the i+2 scan lines SL0 to SLi+1 extend to the non-display area 100b and are connected to the scan driver 102 , and the i light emission control lines EL1 to ELk are connected to the non-display area 100b. It extends to 100b and is connected to the light emission control driver 103 , and j data lines DL1 to DLj extend to the non-display area 100b and are connected to the data driver 104 .

The scan driver 102 and the emission control driver 103 may be manufactured on the substrate 100 in the same process as the pixel PX. For example, the switching elements of the scan driver 102 , the switching elements of the emission control driver 103 , and the switching elements of the pixel PX may be formed on the substrate 100 through a photolithography process. can

The emission control driver 103 may be embedded in the scan driver 102 . For example, the scan driver 102 may further perform the function of the emission control driver 103 . In this case, the scan lines SL0 to SLi+1 and the emission control lines EL1 to ELk are driven together by the scan driver 102 .

The data driver 104 may be manufactured in the form of a chip. The data driver 104 may be attached to the substrate 100 by a chip bonding method. Meanwhile, the data driver 104 may be located on a separate printed circuit board (not shown) instead of the board 100 , and in this case, the data lines DL1 to DLj are connected to the data driver ( 104) is connected.

Meanwhile, each of the scan driver 102 and the emission control driver 103 may be manufactured in the form of a chip. The chip-type scan driver 102 may be located in the non-display area 100a of the substrate 100 or in another printed circuit board (not shown). The light emission control driver 103 in the form of a chip may be located in the non-display area 100a of the substrate 100 or in another printed circuit board (not shown).

The scan lines SL0 to SLi+1 are arranged along the Y-axis direction, and each scan line SL0 to SLi+1 extends along the X-axis direction. The light emission control lines EL1 to ELk are arranged along the Y-axis direction, and each light emission control line EL1 to ELk extends along the X-axis direction. The data lines DL1 to DLj are arranged along the X-axis direction, and each data line DL1 to DLj extends along the Y-axis direction.

Among the aforementioned scan lines SL0 to SLi+1 , the scan line SL0 closest to the data driver 104 is defined as the first dummy scan line SL0 , and the scan line SL0 located farthest from the data driver 104 . The line SLi+1 is defined as the second dummy scan line SLi+1. Also, the scan lines SL1 to SLi between the first dummy scan line SL0 and the second dummy scan line SLi+1 are sequentially the first to i-th scan lines from the scan line adjacent to the data driver 104 . are defined as SL1 to SLi.

The scan driver 102 generates scan signals according to a scan control signal provided from a timing controller (not shown), and sequentially supplies the scan signals to the plurality of scan lines SL0 to SLi+1. The scan driver 102 outputs first to i-th scan signals, a first dummy scan signal, and a second dummy scan signal. The first to i-th scan signals output from the scan driver 102 are respectively supplied to the first to i-th scan lines SL1 to SLi. For example, the nth scan signal is supplied to the nth scan line SLn. Here, n is a natural number greater than or equal to 1 and less than or equal to i. The first dummy scan signal output from the scan driver 102 is supplied to the first dummy scan line SL0, and the second dummy scan signal output from the scan driver 102 is applied to the second dummy scan line SL0. SLi+1).

During one frame period, the scan driver 102 sequentially outputs the first to i-th scan signals from the first scan signal. In this case, the scan driver 102 outputs the first dummy scan signal ahead of the first scan signal and outputs the second dummy scan signal later than the i-th scan signal. In other words, the scan driver 102 outputs the first dummy scan signal first in one frame period and outputs the second dummy scan signal last in the one frame period. Accordingly, during one frame period, all scan lines SL0 to SLi+1 including the dummy scan lines SL0 and SLi+1 are sequentially driven from the first dummy scan line SL0.

The light emission control driver 103 generates light emission control signals according to a control signal provided from a timing controller (not shown), and sequentially supplies the light emission control signals to the plurality of light emission control lines EL1 to ELk. The first to mth emission control signals output from the emission control driver 103 are respectively supplied to the first to mth emission control lines. For example, the mth light emission control signal is supplied to the mth light emission control line. where m is a natural number greater than or equal to 1 and less than or equal to k. During one frame period, the emission control driver 103 sequentially outputs the first to kth emission control signals starting with the first emission control signal. Accordingly, during one frame period, all of the light emission control lines EL1 to ELk are sequentially driven from the first light emission control line EL1.

The data driver 104 supplies first to j-th data voltages to the first to j-th data lines DL1 to DLj, respectively. For example, the data driver 104 receives image data signals and data control signals from a timing controller (not shown). After sampling the image data signals according to the data control signal, the data driver 104 sequentially latches the sampled image data signals corresponding to one horizontal line in every horizontal period and transfers the latched image data signals to the data line. are simultaneously supplied to the DL1 to DLj.

The pixels PX may be disposed on the display area 100a of the substrate 100 in the form of a matrix. The pixels PX emit light of different colors. For example, among the pixels PX in FIG. 1 , a pixel indicated by the symbol “R” is a red pixel emitting red light, a pixel indicated by “G” is a green pixel emitting green light, and “ The pixel indicated by B″ is a blue pixel emitting blue light.

Meanwhile, although not shown, the display device of the present invention may further include at least one white pixel emitting white light. The white pixel may be positioned on the display area 100a of the substrate 100 .

One pixel is connected to at least one scan line. For example, as shown in FIG. 1 , among the plurality of pixels PX connected to the first data line DL1 , a blue pixel located closest to the data driver 104 transmits scan signals having different output timings. It is connected to the supplied three scan lines, ie, a first dummy scan line SL0 , a first scan line SL1 , and a second scan line SL2 . As another example, among the plurality of pixels PX connected to the second data line DL2 , the green pixel located third farthest from the data driver 104 is three scan signals supplied with scan signals having different output timings. It is connected to the lines, that is, the fourth scan line SL4 , the fifth scan line SL5 , and the sixth scan line SL6 .

Pixels that are commonly connected to the same data line and located adjacent to each other are commonly connected to at least one scan line. In other words, two pixels adjacent to each other in the Y-axis direction among pixels connected to the same data line share at least one scan line. For example, a green pixel (hereinafter, a first green pixel) that is connected to the second data line DL2 and located closest to the data driver 104 and the data driver 104 is connected to the second data line DL2. ), a green pixel (hereinafter, a second green pixel) that is second farthest away from each other is located adjacent to each other, and the first green pixel and the second green pixel are commonly connected to the second scan line SL2 . As another example, when defining a green pixel that is connected to the second data line DL2 and that is the third furthest away from the data driver 104 as a third green pixel, the third green pixel and the above-described second green pixel is commonly connected to the fourth scan line SL4.

Pixels commonly connected to the same data line are independently connected to at least one different scan line. For example, the first green pixel described above is independently connected to the first scan line SL1 , the second green pixel described above is independently connected to the third scan line SL3 , and the third green pixel described above is independently connected to the third scan line SL3 . The pixels are independently connected to the fifth scan line SL5 .

In this way, pixels connected to the same data line are each independently connected to at least one scan line. In the future, the meaning that at least two pixels (eg, the first pixel PX1 and the second pixel PX2 ) are connected to different scan lines means at least one of the scan lines connected to the first pixel PX1 . This means that one is different from at least one of the scan lines connected to the second pixel PX2 . Accordingly, pixels connected to the same data line are respectively connected to different scan lines.

On the other hand, in the future, the meaning that at least two pixels (eg, the first pixel PX1 and the second pixel PX2 ) are connected to the same scan line means that the scan lines connected to the first pixel PX1 are It means the same as the scan lines connected to the second pixel PX2 . Accordingly, pixels connected to the same emission control line are respectively connected to the same scan lines. For example, pixels commonly connected to the second emission control line EL2 are commonly connected to the second scan line SL2 , the third scan line SL3 , and the fourth scan line SL4 .

The red pixel and the blue pixel are connected to the 2p-1 data line, and the green pixel is connected to the 2p data line. Here, p is a natural number. For example, the red pixel and the blue pixel are connected to the first data line DL1 , and the green pixel is connected to the second data line DL2 .

Any one pixel (hereinafter, a first specific pixel) connected to the 2p-1 data line (eg, the first data line DL1) is different from the 2p-1 data line (eg, the third data line) Any one pixel (hereinafter, a second specific pixel) connected to the line DL3 may be connected to the same scan line, wherein the first specific pixel emits light of a different color from that of the second specific pixel. For example, the first specific pixel is a blue pixel connected to the first dummy scan line SL0 , the first scan line SL1 , the second scan line SL2 , and the first data line DL1 , and the second The specific pixel may be a red pixel connected to the first dummy scan line SL0 , the first scan line SL1 , the second scan line SL2 , and the third data line DL3 .

Two adjacent pixels that are connected to the same data line (eg, the 2p-1 data line) and emit light of different colors, and at least one green pixel adjacent to any one of the two pixels are one included in one unit pixel for displaying a unit image of For example, a red pixel connected to the third data line DL3 and the first scan line SL1 , a blue pixel connected to the third data line DL3 and the third scan line SL3 , and a second data line The green pixel connected to the DL2 and the first scan line SL1 and the green pixel connected to the fourth data line DL4 and the first scan line SL1 may form one unit pixel.

Each pixel PX is commonly supplied with the high potential driving voltage ELVDD, the low potential driving voltage ELVSS, and the initialization voltage Vinit from the power supply unit 105 . In other words, one pixel receives all of the high potential driving voltage ELVDD, the low potential driving voltage ELVSS, and the initialization voltage Vinit.

FIG. 2 is a diagram illustrating an equivalent circuit for any one pixel shown in FIG. 1 .

The pixel PX includes a first switching element T1 , a second switching element T2 , a third switching element T3 , a fourth switching element T4 , a fifth switching element T5 , and a sixth switching element ( T6), a seventh switching element T7, a storage capacitor Cst, and a light emitting element LED may be included.

As shown in FIG. 2 , each of the first to seventh switching elements T1 to T7 may be a P-type transistor. Meanwhile, each of the first to seventh switching elements T1 to T7 may be an N-type transistor.

The first switching element T1 includes a gate electrode connected to the first node n1 , and is connected between the second node n2 and the third node n3 . One of the source electrode and the drain electrode of the first switching element T1 is connected to the second node n2 , and the other of the source electrode and the drain electrode is connected to the third node n3 .

The second switching element T2 includes a gate electrode connected to the nth scan line SLn and is connected between the data line DL and the second node n2 . One of the source electrode and the drain electrode of the second switching element T2 is connected to the data line DL, and the other of the source electrode and the drain electrode is connected to the second node n2. The nth scan signal SSn is applied to the nth scan line SLn.

The third switching element T3 includes a gate electrode connected to the nth scan line SLn and is connected between the first node n1 and the third node n3 . One of the source electrode and the drain electrode of the third switching element T3 is connected to the first node n1 , and the other of the source electrode and the drain electrode is connected to the third node n3 .

The fourth switching element T4 includes a gate electrode connected to the n-1 th scan line SLn - 1 and is connected between the first node n1 and the initialization line IL. One of the source electrode and the drain electrode of the fourth switching element T4 is connected to the first node n1 , and the other of the source electrode and the drain electrode is connected to the initialization line IL. The aforementioned initialization voltage Vinit is applied to the initialization line IL, and the n-1 th scan signal SSn-1 is applied to the n-1 th scan line SLn-1.

The fifth switching element T5 includes a gate electrode connected to the light emission control line EL, and is connected between the high potential line VDL, which is one of the power supply lines, and the second node n2 . One of the source electrode and the drain electrode of the fifth switching element T5 is connected to the high potential line VDL, and the other of the source electrode and the drain electrode is connected to the second node n2 . The above-described high potential driving voltage ELVDD is applied to the high potential line VDL.

The sixth switching element T6 includes a gate electrode connected to the light emission control line EL, and is connected between the third node n3 and the fourth node n4. One of the source electrode and the drain electrode of the sixth switching element T6 is connected to the third node n3 , and the other of the source electrode and the drain electrode is connected to the fourth node n4 . The light emission control signal ES is applied to the light emission control line EL.

The seventh switching element T7 includes a gate electrode connected to the n+1th scan line SLn+1, and is connected between the initialization line IL and the fourth node n4. One of the source electrode and the drain electrode of the seventh switching element T7 is connected to the initialization line IL, and the other of the source electrode and the drain electrode is connected to the fourth node n4 . The n+1th scan signal SSn+1 is applied to the n+1th scan line SLn+1.

The storage capacitor Cst is connected between the high potential line VDL and the first node n1. The storage capacitor Cst stores the signal applied to the gate electrode of the first switching element T1 for one frame period.

The light emitting element LED emits light according to a driving current supplied through the first switching element T1 . The light emitting element LED emits light with different brightness according to the magnitude of its driving current. The anode electrode of the light emitting element LED is connected to the fourth node n4, and the cathode electrode of the light emitting element LED is connected to the low potential line VSL, which is another one of the power supply lines. The above-described low potential driving voltage ELVSS is applied to the low potential line VSL. The light emitting device LED may be an organic light emitting diode. The anode electrode of the light emitting device LED corresponds to a pixel electrode to be described later, and the cathode electrode corresponds to a common electrode to be described later.

When the n-1 th scan signal SSn-1 is applied to the n-1 th scan line SLn-1, the fourth switching element T4 is turned on. The initialization voltage Vinit is applied to the first node n1 (ie, the gate electrode of the first switching element T1) through the turned-on fourth switching element T4. Accordingly, the voltage of the gate electrode of the first switching element T1 is initialized.

When the nth scan signal SSn is applied to the nth scan line SLn, the second switching element T2 and the third switching element T3 are turned on. The data voltage DA is applied to the first node n1 (that is, the gate electrode of the first switching element T1) through the turned-on second switching element T2, and accordingly, the first switching element T1 is turned on. Accordingly, the threshold voltage of the first switching element T1 is detected and the threshold voltage is stored in the storage capacitor Cst.

When the emission control signal ES is applied to the emission control line EL, the fifth switching element T5 and the sixth switching element T6 are turned on. A driving current is supplied to the light emitting element LED through the turned-on fifth switching element T5 , the first switching element T1 , and the sixth switching element T6 . Accordingly, the light emitting element LED emits light.

When the n+1th scan signal SSn+1 is applied to the n+1th scan line SLn+1, the seventh switching element T7 is turned on. An initialization voltage is applied to the fourth node n4 (ie, the anode electrode of the light emitting element LED) through the turned-on seventh switching element T7 . Accordingly, the light emitting element LED is biased in the reverse direction, so that the light emitting element LED is turned off.

3 is a detailed plan view of a display device including any one pixel shown in FIG. 1 and lines connected thereto, and FIGS. 4A to 4G are views showing only some of the components of FIG. 3 separately, and 5 is a cross-sectional view taken along line I-I' of FIG. 3 .

Specifically, FIG. 4A is a view showing the semiconductor layer 321 of FIG. 3 , and FIG. 4B is an n-1th scan line SLn-1, an nth scan line SLn, and an n+1th scan line of FIG. 3 . It is a view showing the line SLn+1 and the light emission control line EL, FIG. 4C is a view showing the initialization line IL and the capacitor electrode 201 of FIG. 3 , and FIG. 4D is the data line DL of FIG. 3 ) and the high potential line VDL, FIG. 4E is a diagram illustrating the pixel electrode PE of FIG. 3 , and FIG. 4F is the semiconductor layer 321 and the n−1th scan line SLn− 1), an nth scan line SLn, an n+1th scan line SLn+1, and a light emission control line EL are shown. FIG. 4G is the first connection electrode 701 and the second It is a diagram illustrating the connection electrode 702 , the third connection electrode 703 , the data line DL, the high potential line VDL, and the light blocking film 190 .

3 to 5 , a display device according to an exemplary embodiment includes a substrate 100 , a pixel circuit unit 200 , a light blocking film 190 , a spacer 422 , a light emitting element (LED), and a sealing part 750 .

3 and 4F , the first switching element T1 of the pixel circuit unit 200 includes a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. do.

3 and 4F , the second switching element T2 of the pixel circuit unit 200 includes a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. do.

3 and 4F , the third switching element T3 of the pixel circuit unit 200 includes a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3. do.

As shown in Figures 3 and 4f, The fourth switching element T4 of the pixel circuit unit 200 includes a fourth gate electrode GE4 , a fourth source electrode SE4 , and a fourth drain electrode DE4 .

3 and 4F , the fifth switching element T5 of the pixel circuit unit 200 includes a fifth gate electrode GE5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 . do.

3 and 4F , the sixth switching element T6 of the pixel circuit unit 200 includes a sixth gate electrode GE6, a sixth source electrode SE6, and a sixth drain electrode DE6. do.

3 and 4F , the seventh switching element T7 of the pixel circuit unit 200 includes a seventh gate electrode GE7, a seventh source electrode SE7, and a seventh drain electrode DE7. do.

The substrate 100 illustrated in FIG. 5 may include at least two layers. For example, the substrate 100 includes a base layer 110 , a first layer 111 , a second layer 112 , a third layer 113 , and a fourth layer 114 arranged along the Z-axis direction. can do. The first layer 111 is positioned between the base layer 110 and the second layer 112 , and the second layer 112 is positioned between the first layer 111 and the third layer 113 , and the third The layer 113 is positioned between the second layer 112 and the fourth layer 114 , and the fourth layer 114 is disposed between the third layer 113 and the buffer layer 120 of the pixel circuit unit 200 . Located.

The first layer 111 may have a greater thickness than the second layer 112 . The thickness means a size measured in the Z-axis direction.

The third layer 113 may have a greater thickness than the fourth layer 114 . The thickness means a size measured in the Z-axis direction.

The first layer 111 and the third layer 113 may have the same thickness. The thickness means a size measured in the Z-axis direction.

The second layer 112 and the fourth layer 114 may have the same thickness. The thickness means a size measured in the Z-axis direction.

The base layer 110 may be a glass substrate or a film.

The first layer 111 may be made of glass or transparent plastic. Also, the first layer 111 may include an organic material. For example, the first layer 111 may include kapton, polyethersulphone (PES), polycarbonate (PC), polyimide (PI), polyethyleneterephthalate (PET), It may include any one selected from the group consisting of polyethylene naphthalate (PEN), polyacrylate (PAR), and fiber reinforced plastic (FRP).

The second layer 112 may include an inorganic material. For example, the second layer 112 may be made of any one of a silicon nitride (SiNx) film, a silicon oxide (SiO2) film, and a silicon oxynitride (SiOxNy) film.

The third layer 113 may be made of the same material as the above-described first layer 111 .

The fourth layer 114 may be made of the same material as the above-described second layer 112 .

As shown in FIG. 5 , the pixel circuit unit 200 is positioned on the substrate 100 . For example, the pixel circuit unit 200 is located on the fourth layer 114 of the substrate 100 .

The pixel circuit unit 200 includes a buffer layer 120 , a semiconductor layer 321 , a gate insulating layer 140 , a first gate electrode GE1 , a second gate electrode GE2 , a third gate electrode GE3 , and a fourth gate. electrode GE4, fifth gate electrode GE5, sixth gate electrode GE6, seventh gate electrode GE7, n-1th scan line SLn-1, nth scan line SLn, n+1 scan line SLn+1, light emission control line EL, first interlayer insulating layer 150 , initialization line IL, capacitor electrode 201 , second interlayer insulating layer 160 , first connection electrode 701 , a second connection electrode 702 , a third connection electrode 703 , a data line DL, a high potential line VDL, and a planarization layer 180 may be included.

The buffer layer 120 is positioned on the fourth layer 114 of the substrate 100 . The buffer layer 120 may be disposed on the entire surface of the fourth layer 114 . For example, the buffer layer 120 may overlap the entire surface of the fourth layer 114 .

The buffer layer 120 prevents penetration of impurity elements and serves to planarize the surface, and may be formed of various materials capable of performing such a role. For example, the buffer layer 120 may be made of any one of a silicon nitride (SiNx) film, a silicon oxide (SiO ₂ ) film, and a silicon oxynitride (SiOxNy) film. However, the buffer layer 120 is not necessarily required, and may be omitted depending on the type of the substrate 100 and process conditions.

As shown in FIG. 5 , the semiconductor layer 321 is positioned on the buffer layer 120 .

As shown in FIG. 4A , the semiconductor layer 321 provides respective channel regions CH1 to CH7 of the first to seventh switching elements T1 to T7 . Also, the semiconductor layer 321 provides the source electrodes SE1 to SE7 and the drain electrodes DE1 to DE7 of the first to seventh switching elements T1 to T7 .

To this end, the semiconductor layer 321 includes a first channel region CH1, a second channel region CH2, a third channel region CH3, a fourth channel region CH4, a fifth channel region CH5, and a second channel region CH5. 6 channel region CH6 and seventh channel region CH7 , first source electrode SE1 , second source electrode SE2 , third source electrode SE3 , fourth source electrode SE4 , and fifth source Electrode SE5, sixth source electrode SE6, seventh source electrode SE7, first drain electrode DE1, second drain electrode DE2, third drain electrode DE3, fourth drain electrode ( DE4 ), a fifth drain electrode DE5 , a sixth drain electrode DE6 , and a seventh drain electrode DE7 .

The first source electrode SE1 , the second drain electrode DE2 , and the fifth drain electrode DE5 are connected to each other. For example, the first source electrode SE1 , the second drain electrode DE2 , and the fifth drain electrode DE5 may be integrally formed.

The first drain electrode DE1 , the third source electrode SE3 , and the sixth source electrode SE6 are connected to each other. For example, the first drain electrode DE1 , the third source electrode SE3 , and the sixth source electrode SE6 may be integrally formed.

The third drain electrode DE3 and the fourth drain electrode DE4 are connected to each other. For example, the third drain electrode DE3 and the fourth drain electrode DE4 may be integrally formed.

The sixth drain electrode DE6 and the seventh source electrode SE7 are connected to each other. For example, the sixth drain electrode DE6 and the seventh source electrode SE7 may be integrally formed.

The semiconductor layer 321 may include any one of a polycrystalline silicon film, an amorphous silicon film, and an oxide semiconductor such as indium-gallium-zinc oxide (IGZO) or indium zinc tin oxide (IZTO). For example, when the semiconductor layer 321 includes a polysilicon film, the semiconductor layer 321 includes a channel region not doped with impurities, and a source electrode and drain doped with impurity ions located on both sides of the channel region. including electrodes.

5 , the gate insulating layer 140 is disposed on the semiconductor layer 321 and the buffer layer 110 . The gate insulating layer 140 may include at least one of tetraethoxysilane (TetraEthylOrthoSilicate, TEOS), silicon nitride (SiNx), and silicon oxide (SiO ₂ ). For example, the gate insulating layer 140 may have a double layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethoxysilane layer having a thickness of 80 nm are sequentially stacked.

5 , the first gate electrode GE1 is disposed on the gate insulating layer 140 . Specifically, the first gate electrode GE1 is positioned between the gate insulating layer 140 and the first interlayer insulating layer 150 .

Although not shown in FIG. 5 , the second gate electrode GE2 , the third gate electrode GE3 , the fourth gate electrode GE4 , the fifth gate electrode GE5 , the sixth gate electrode GE6 , and the seventh gate The electrode GE7 is also located on the gate insulating layer 140 . Specifically, the second to seventh gate electrodes GE2 to GE7 are positioned between the gate insulating layer 140 and the first interlayer insulating layer 150 .

Although not shown in FIG. 5 , the scan line and the emission control line are also located on the gate insulating layer 140 . Specifically, the n-1th scan line SLn-1, the nth scan line SLn, the n+1th scan line SLn+1, and the light emission control line EL are connected to the gate insulating layer 140 and the first It is positioned between the interlayer insulating layers 150 .

3 and 4F , the first gate electrode GE1 overlaps the first channel region CH1 of the semiconductor layer 321 , and the second gate electrode GE2 is the semiconductor layer 321 . The second channel region CH2 overlaps, the third gate electrode GE3 overlaps the third channel region CH3 of the semiconductor layer 321 , and the fourth gate electrode GE4 overlaps the semiconductor layer 321 . The fourth channel region CH4 overlaps, the fifth gate electrode GE5 overlaps the fifth channel region CH5 of the semiconductor layer 321 , and the sixth gate electrode GE6 overlaps the semiconductor layer 321 . The sixth channel region CH6 overlaps, and the seventh gate electrode GE7 overlaps the seventh channel region CH7 of the semiconductor layer 321 .

4B and 4F , the fourth gate electrode GE4 is connected to the n−1th scan line SLn−1, and in this case, the fourth gate electrode GE4 is connected to the n−1th scan line SLn−1. It may be a part of the line SLn-1. For example, a portion of the n−1th scan line SLn−1 that overlaps the semiconductor layer 321 may be the fourth gate electrode GE4 .

4B and 4F , the third gate electrode GE3 is connected to the nth scan line SLn, and in this case, the third gate electrode GE3 is a part of the nth scan line SLn. can For example, a portion of the nth scan line SLn that overlaps the semiconductor layer 321 may be the third gate electrode GE3 .

4B and 4F , the seventh gate electrode GE7 is connected to the n+1th scan line SLn+1, and in this case, the seventh gate electrode GE7 is the n+1th scan line SLn+1. It may be a part of the line SLn+1. For example, a portion of the n+1th scan line SLn+1 that overlaps the semiconductor layer 321 may be the seventh gate electrode GE7.

4B and 4F , the fifth gate electrode GE5 and the sixth gate electrode GE6 are commonly connected to one light emission control line EL, and in this case, the fifth gate electrode GE5 and the sixth gate electrode GE6 may be a part of the emission control line EL. For example, two portions of the emission control line EL overlapping the semiconductor layer 321 may be the fifth gate electrode GE5 and the sixth gate electrode GE6 , respectively.

The scan line (eg, at least one of the n-1th scan line SLn-1, the nth scan line SLn, and the n+1th scan line SLn+1) may be formed of aluminum (Al) or an aluminum alloy. Aluminum-based metals such as, or silver-based metals such as silver (Ag) or silver alloys, or copper-based metals such as copper (Cu) or copper alloys, or molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys It can be made of metal. Alternatively, the gate line GL may be made of any one of chromium (Cr) and tantalum (Ta). Meanwhile, the scan line may have a multilayer structure including at least two conductive layers having different physical properties.

The first to seventh gate electrodes GE1 to GE7 may have the same material and structure (multi-layer structure) as the aforementioned scan line. Each of the gate electrodes GE1 to GE7 and the scan line may be simultaneously formed by the same process.

In addition, the light emission control line EL may have the same material and structure (multi-layer structure) as the aforementioned scan line (eg, SLn). The emission control line EL and the scan line may be simultaneously made by the same process.

5 , the first interlayer insulating layer 150 is disposed on the first gate electrode GE1 and the gate insulating layer 140 . The first interlayer insulating layer 150 may have a greater thickness than the gate insulating layer 140 . The first interlayer insulating layer 150 may be made of the same material as the above-described gate insulating layer 140 .

Although not shown in FIG. 5 , the first interlayer insulating layer 150 includes the second to seventh gate electrodes GE2 to GE7 , each scan line (eg, SLn-1 , SLn, SLn+1), and each emission control layer. It is also located on the line EL.

As shown in FIG. 5 , the capacitor electrode 201 is positioned on the first interlayer insulating layer 150 . For example, the capacitor electrode 201 is positioned between the first interlayer insulating layer 150 and the second interlayer insulating layer 160 . The capacitor electrode 201 together with the above-described first gate electrode GE1 forms a storage capacitor Cst. For example, the first gate electrode GE1 corresponds to a first electrode of the storage capacitor Cst, and the capacitor electrode 201 corresponds to a second electrode of the storage capacitor Cst. Specifically, a portion of the first gate electrode GE1 that overlaps the capacitor electrode 201 corresponds to the first electrode of the storage capacitor Cst, and overlaps the first gate electrode GE1 of the capacitor electrode 201 . The portion to correspond to the second electrode of the storage capacitor (Cst).

Although not shown in FIG. 5 , the initialization line (IL in FIGS. 3 and 4C ) is also located on the first interlayer insulating layer 150 . Specifically, the initialization line IL is positioned between the first interlayer insulating layer 150 and the second interlayer insulating layer 160 .

3 and 4C , the capacitor electrode 201 has a hole 30 . The hole 30 may have a rectangular shape. The shape of this hall is not limited to a square. For example, the hole 30 may have various shapes such as a circle and a triangle.

3 and 4C , capacitor electrodes 201 of pixels adjacent to each other may be connected to each other. In other words, the capacitor electrodes 201 of pixels adjacent in the X-axis direction may be integrally formed.

As shown in FIG. 5 , the second interlayer insulating layer 160 is positioned on the capacitor electrode 201 , the initialization line IL, and the first interlayer insulating layer 150 . The second interlayer insulating layer 160 may have a greater thickness than the gate insulating layer 140 . The second interlayer insulating layer 160 may be made of the same material as the above-described gate insulating layer 140 .

5 , the first connection electrode 701 , the second connection electrode 702 , the high potential line VDL, and the data line DL are positioned on the second interlayer insulating layer 160 . Specifically, the first connection electrode 701 , the second connection electrode 702 , the high potential line VDL and the data line DL are positioned between the second interlayer insulating layer 160 and the planarization layer 180 .

Although not shown in FIG. 5 , the third connection electrode ( 703 in FIGS. 3 and 4D ) is also located on the second interlayer insulating layer 160 . Specifically, the third connection electrode 703 is positioned between the second interlayer insulating layer 160 and the planarization layer 180 .

As shown in FIG. 5 , the first connection electrode 701 is connected through a first contact hole 11 penetrating the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 . 1 is connected to the source electrode SE1.

5 , the second connection electrode 702 is connected to the first gate electrode GE1 through the second contact hole 12 penetrating the second interlayer insulating layer 160 and the first interlayer insulating layer 150 . is connected to Also, the second connection electrode 702 is connected to the third drain electrode DE3 through the third contact hole 13 as shown in FIGS. 3 , 4A and 4D . The third contact hole 13 penetrates the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 to expose the third drain electrode DE3 .

3 , 4A and 4D , the third connection electrode 703 is connected to the fourth source electrode SE4 through the fourth contact hole 14 . The fourth contact hole 14 penetrates the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 to expose the fourth source electrode SE4 . Also, the third connection electrode 703 is connected to the initialization line IL through the fifth contact hole 15 as shown in FIGS. 3 , 4C and 4D . The fifth contact hole 15 penetrates the second interlayer insulating layer 160 to expose the initialization line IL.

5 , the high potential line VDL is connected to the capacitor electrode 201 through the sixth contact hole 16 penetrating the second interlayer insulating layer 160 . Also, the high potential line VDL is connected to the fifth source electrode SE5 through the seventh contact hole 17 as shown in FIGS. 3, 4A and 4D . The seventh contact hole 17 penetrates the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 to expose the fifth source electrode SE5 .

3 , 4A and 4D , the data line DL is connected to the second source electrode SE2 through the eighth contact hole 18 . The eighth contact hole 18 penetrates the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 to expose the second source electrode SE2 .

The data line DL may be made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof. The data line DL may have a multilayer structure including a refractory metal layer and a low resistance conductive layer. Examples of multi-film structures include a double film of a chromium or molybdenum (or molybdenum alloy) lower film and an aluminum (or aluminum alloy) upper film, a molybdenum (or molybdenum alloy) lower film and an aluminum (or aluminum alloy) interlayer and a molybdenum (or molybdenum alloy) upper film. ) a triple film of the upper film. Meanwhile, the data line DL may be made of various other metals or conductors.

The first connection electrode 701 , the second connection electrode 702 , the third connection electrode 703 , and the high potential line VDL may have the same material and structure (multi-layer structure) as the data line DL described above. can The first connection electrode 701 , the second connection electrode 702 , the third connection electrode 703 , the high potential line VDL, and the data line DL may be simultaneously formed through the same process.

5 , the planarization layer 180 includes a first connection electrode 701 , a second connection electrode 702 , a third connection electrode 703 , a high potential line VDL, and a data line DL. located on top

The planarization layer 180 removes a height difference between the layers below the planarization layer 180 in order to increase the luminous efficiency of the light emitting device (LED) to be formed thereon. The planarization film 180 is made of acrylic resin, epoxy resin, phenolicresin, polyamides resin, polyimides rein, unsaturated polyester resin ( unsaturated polyesters resin), polyphenyleneethers resin, polyphenylenesulfides resin, and benzocyclobutene (BCB).

The light emitting device LED may be an organic light emitting device. As shown in FIG. 5 , the light emitting element LED includes a light emitting layer 512 , an anode electrode PE (hereinafter, referred to as a pixel electrode), and a cathode electrode 613 (hereinafter referred to as a common electrode).

The light emitting layer 512 is made of a low molecular weight organic material or a high molecular weight organic material. Although not shown, at least one of a hole injection layer (HIL) and a hole transport layer (HTL) may be further positioned between the pixel electrode PE and the emission layer 512 , and an electron transport layer (Electron) At least one of a transporting layer (ETL) and an electron injection layer (EIL) may be further positioned between the emission layer 512 and the common electrode 613 .

As shown in FIG. 5 , the pixel electrode PE is positioned on the planarization layer 180 . A part or all of the pixel electrode PE is located in the emission area 900 . That is, the pixel electrode PE is positioned to correspond to the emission area 900 defined by the light blocking layer 190 to be described later. The pixel electrode PE is connected to the first connection electrode 701 through the ninth contact hole 19 penetrating the planarization layer 180 .

3 and 4E , the pixel electrode PE may have a rhombic shape. The pixel electrode PE may have various shapes other than a rhombic shape, for example, a quadrangular shape.

5 , the light blocking layer 190 is disposed on the pixel electrode PE and the planarization layer 180 . The light blocking film 190 has an opening 900 passing therethrough, and the opening 900 corresponds to the light emitting area 900 . 3 and 4G , the light emitting area 900 may have a rhombic shape. The light emitting area 900 may have various shapes other than a rhombic shape, for example, a quadrangular shape. The size of the emission area 900 may be smaller than the size of the aforementioned pixel electrode PE. At least a portion of the pixel electrode PE is positioned in the emission area 900 . In this case, the entire emission area 900 overlaps the pixel electrode PE.

The light blocking layer 190 may be made of a resin such as polyacrylates resin and polyimides.

The spacer 422 is positioned on the light blocking layer 190 . The spacer 422 may be made of the same material as the light blocking layer 190 . The spacer 422 serves to minimize a difference in height between a layer positioned in the display area 100a of the substrate 100 and a layer positioned in the non-display area 100b of the substrate 100 .

The emission layer 512 is located on the pixel electrode PE in the emission area 900 , and the common electrode 613 is located on the light blocking layer 190 and the emission layer 512 .

The pixel electrode PE and the common electrode 513 may be formed of any one of a transmissive electrode, a transflective electrode, and a reflective electrode.

The transmissive electrode may include a transparent conductive oxide (TCO). The transparent conductive oxide (TCO) is at least selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc oxide (ZnO), and mixtures thereof. may contain one.

Transflective and reflective electrodes are made of metals such as magnesium (Mg), silver (Ag), gold (Au), calcium (Ca), lithium (Li), chromium (Cr), aluminum (Al), and copper (Cu). or an alloy thereof. In this case, the transflective electrode and the reflective electrode are distinguished by their thickness. In general, the transflective electrode has a thickness of about 200 nm or less, and the reflective electrode has a thickness of 300 nm or more. As the thickness of the semi-transmissive electrode decreases, the light transmittance increases, but the resistance increases. As the thickness increases, the light transmittance decreases.

In addition, the transflective and reflective electrodes may have a multi-layer structure including a metal layer made of a metal or an alloy of a metal and a transparent conductive oxide (TCO) layer stacked on the metal layer.

The sealing part 750 is located on the common electrode 613 . The sealing part 750 may include a transparent insulating substrate made of glass or a transparent plastic material. In addition, the sealing part 750 may be formed in a thin film encapsulation structure in which one or more inorganic layers and one or more organic layers are alternately stacked along the Z-axis direction. For example, as shown in FIG. 5 , the sealing part 750 may include a first inorganic layer 751 , an organic layer 755 , and a second inorganic layer 752 . The organic layer 755 is positioned between the first inorganic layer 751 and the second inorganic layer 752 . The organic layer 755 has the largest thickness among the first inorganic layer 751 , the organic layer, and the second inorganic layer 752 . The first inorganic layer 751 and the second inorganic layer 752 may have the same thickness.

The first inorganic layer 751 and the second inorganic layer 752 may be made of the same material as the above-described second layer 112 .

The organic layer 755 may be made of the same material as the first layer 111 . Also, the organic layer 755 may include a monomer.

6 is a cross-sectional view taken along the line II-II' of FIG. 3 , and FIG. 7 is an enlarged view of part A of FIG. 6 . However, in FIG. 7 , the sealing part 750 and the common electrode 613 are omitted.

A portion of the sealing part 750 is inserted into the substrate 100 as shown in FIG. 6 . For example, the sealing portion 750 includes a cover portion 750a and an extension portion 750b extending from the cover portion 750a toward the substrate 100, and the extension portion 750b includes the substrate ( 100) is inserted.

To this end, the substrate 100 , the pixel circuit unit 200 , and the light blocking film 190 have holes or grooves in portions corresponding to the extension portion 750b of the sealing unit 750 . For example, as shown in FIGS. 6 and 7 , the substrate 100 includes a first hole 21 and a groove 20 positioned to correspond to the extension part 750b, and the pixel circuit part 200 includes The second hole 22 is positioned to correspond to the extension part 750b, and the light blocking film 190 includes a third hole 23 positioned to correspond to the extension part 750b.

The groove 20 of the substrate 100 may be located, for example, in the third layer 113 of the substrate 100 . The groove 20 is located in a lower layer than the switching element (eg, at least one of T1 to T7 ) of the pixel circuit unit 200 . For example, the groove 20 is located closer to the base layer 110 than the switching element. As a more specific example, the distance between the groove 20 and the base layer 110 measured in the Z-axis direction is smaller than the distance between the semiconductor layer 321 of the switching element and the base layer 110 measured in the Z-axis direction.

The first hole 21 of the substrate 100 may be located, for example, in the fourth layer 114 of the substrate 100 .

The first hole 21 , the second hole 22 , the third hole 23 , and the groove 20 are positioned to correspond to each other. In addition, adjacent ones of the first hole 21 , the second hole 22 , the third hole 23 , and the groove 20 are connected to each other.

The first hole 21 may be positioned between the groove 20 and the second hole 22 .

The groove 20 has a width (or diameter) that gradually increases along a direction (eg, Z-axis direction) from the third layer 113 to the fourth layer 114 . 7 , the width 20d (or diameter) of the groove 20 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 20d (or diameter) of the groove 20 means the maximum width (or maximum diameter) or average width (or average diameter) of the groove 20 .

At least one of the inner walls W1 and W2 facing each other of the groove 20 is inclined at a predetermined angle with respect to the interfaces S1 and S2 between the third layer 113 and the fourth layer 114 . For example, angles θ1 and θ2 formed between at least one of the inner walls W1 and W1 of the groove 20 facing each other and the interfaces S1 and S2 are obtuse angles. As a more specific example, the angle θ1 between the inner wall W1 and the interface S1 adjacent to the inner wall W1 is an obtuse angle.

The first hole 21 has a width (or diameter) that gradually increases along the Z-axis direction. The width 21d (or diameter) of the first hole 21 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 21d (or diameter) of the first hole 21 means the maximum width (or maximum diameter) or average width (or average diameter) of the first hole 21 .

The second hole 22 has a width (or diameter) that gradually increases along the Z-axis direction. The width 22d (or diameter) of the second hole 22 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 22d (or diameter) of the second hole 22 means the maximum width (or maximum diameter) or average width (or average diameter) of the second hole 22 .

The second hole 22 refers to a hole continuously penetrating the insulating layers included in the pixel circuit unit 200 . For example, the second hole means a hole continuously passing through the buffer layer 120 , the gate insulating layer 140 , the first interlayer insulating layer 150 , the second interlayer insulating layer 160 , and the planarization layer 180 . For example, the second hole 22 may include a hole 22-1 passing through the buffer layer 120 (hereinafter, referred to as a buffer hole), a hole 22-2 passing through the gate insulating layer 140 (hereinafter referred to as a gate hole); A hole 22-3 passing through the first interlayer insulating layer 150 (hereinafter, referred to as a first interlayer hole), a hole 22-4 passing through the second interlayer insulating layer 160 (hereinafter referred to as a second interlayer hole), and a planarization layer and a hole 22-5 passing through 180 (hereinafter, referred to as a planarization hole).

The buffer hole 22-1, the gate hole 22-2, the first interlayer hole 22-3, the second interlayer hole 22-4, and the planarization hole 22-5 have different widths (or diameters). ) can have For example, the holes 22-1, 22-2, 22-3, 22-4, and 22-5 included in the second hole 22 become larger as they move away from the substrate 100 in the Z-axis direction. It can have a width (or diameter). As a specific example, planarization holes among the buffer hole 22-1, the gate hole 22-2, the first interlayer hole 22-3, the second interlayer hole 22-4, and the planarization hole 22-5 (22-5) may have the largest width (or diameter). The width (or diameter) of each hole included in the second hole 22 is a value measured in the X-axis direction (or the Y-axis direction). At this time, the width (or diameter) of each hole 22-1, 22-2, 22-3, 22-4, 22-5 included in the second hole 22 is the maximum width (or maximum diameter) of the corresponding hole. or average width (or average diameter).

Each of the holes 22-1, 22-2, 22-3, 22-4, and 22-5 included in the second hole 22 also have a width (or diameter) that gradually increases along the Z-axis direction. can For example, the buffer hole 22-1 has a width (or diameter) that gradually increases along the Z-axis direction, and the gate hole 22-2 has a width (or diameter) that gradually increases along the Z-axis direction. ), the first interlayer hole 22-3 has a width (or diameter) that gradually widens along the Z-axis direction, and the second interlayer hole 22-4 has a width (or diameter) that gradually widens along the Z-axis direction. It has a width (or diameter), and the planarization hole 22 - 5 has a width (or diameter) that gradually increases along the Z-axis direction.

The third hole 23 may have a width (or diameter) that gradually increases along the Z-axis direction. The width 23d (or diameter) of the third hole 23 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 23d (or diameter) of the third hole 23 means the maximum width or the average width of the third hole 23 .

The width 20d (or diameter) of the groove 20 is greater than the width 21d (or diameter) of the first hole 21 . As shown in FIG. 7 , the cross-sections of the groove 20 and the first hole 21 may have the shape of an anchor. In this case, the cross section of the extended portion 750b inserted into the groove 20 and the first hole 21 may also have an anchor shape.

In the plan view of FIG. 1 , the first hole 21 is surrounded by a groove 20 . Also, in the plan view of FIG. 1 , the first hole 21 and the groove 20 overlap.

In the plan view of FIG. 1 , the first hole 21 , the second hole 22 and the groove 20 are surrounded by the third hole 23 .

The width 22d (or diameter) of the second hole 22 is greater than the width 21d (or diameter) of the first hole 21 .

The width 23d (or diameter) of the third hole 23 is greater than the width 22d (or diameter) of the second hole 22 .

The extended portion 750b of the above-described sealing unit 750 is inserted (or buried) in the groove 20, the first hole 21, the second hole 22, and the third hole 23 having such a structure. do. For example, the extension 750b is inserted into the groove 20 by sequentially passing through the third hole 23 , the second hole 22 , and the first hole 21 . At this time, since the width 20d (or diameter) of the groove 20 is larger than the width 21d (or diameter) of the first hole 21 , the groove 20 , the first hole 21 , and the second hole 22 . ) and the extended portion 750b inserted into the third hole 23 are not well separated in the Z-axis direction. Therefore, the bonding force between the sealing part 750 and the substrate 100 and the bonding force between the sealing part 750 and the lower structure thereof may be improved.

On the other hand, the edge of the sealing part 750 is located at the edge of the substrate 100 . At the edge of the substrate 100 , the sealing part 750 is the first inorganic layer 751 and the second inorganic layer in contact with each other. (752). That is, the sealing part 750 located at the edge of the substrate 100 does not include an organic layer. In addition, the planarization layer 180 is not located at the edge of the substrate 100 . In order to improve the bonding force between the sealing part 750 and the substrate 100 , the edge of the sealing part 750 contacts the edge of the substrate 100 . For example, the first inorganic layer 751 and the second inorganic layer 752 of the encapsulation unit 750 may contact the second interlayer insulating layer 160 located at the edge of the substrate 100 . Meanwhile, when the edge of the encapsulation unit 750 is lengthened, the bonding force between the encapsulation unit 750 and the substrate 100 is improved, while the dead space of the display device 1000 is increased. According to the present invention, since the bonding force between the sealing part 750 and the substrate 100 may be improved through the extension part 750b of the sealing part 750 , the length of the edge of the sealing part 750 may be reduced. Accordingly, the dead space of the display device 1000 may be minimized.

The aforementioned groove 20 , the first hole 21 , the second hole 22 , and the third hole 23 may be located in the display area 100a of the substrate 100 . For example, when defining the entire hole consisting of the groove 20, the first hole 21, the second hole 22, and the third hole 23 as one coupling groove 220, the coupling groove ( 220 ) and the extension 750b may be located in the display area 100a of the substrate 100 .

As shown in FIG. 3 , the coupling groove 220 and the extension part 750b of the display area 100a may be positioned between the high potential line VDL and the data line DL adjacent to each other.

FIG. 8 is a detailed plan view of a display device including a plurality of pixels shown in FIG. 1 and lines connected thereto.

A plurality of pixels is illustrated in FIG. 8 . Here, the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 include four pixels commonly connected to the m-th emission control line ELm, respectively. ) and a fourth pixel PX4 . In addition, the fifth pixel PX5 , the sixth pixel PX6 , the seventh pixel PX7 , and the eighth pixel PX8 are the four pixels commonly connected to the m+1th emission control line ELm+1, respectively. ) is defined as

The second pixel PX2 of FIG. 8 is the same as the aforementioned pixel PX of FIG. 3 . The first pixel PX1 , the third pixel PX3 , the fourth pixel PX4 , the fifth pixel PX5 , the sixth pixel PX6 , the seventh pixel PX7 and the eighth pixel PX8 are shown in FIG. It has substantially the same configuration as the third pixel PX.

The first pixel PX1 , the third pixel PX3 , the fifth pixel PX5 , and the seventh pixel PX7 may emit light of the same color. For example, the first pixel PX1 , the third pixel PX3 , the fifth pixel PX5 , and the seventh pixel PX7 are red pixels emitting green light, respectively.

The second pixel PX2 and the eighth pixel PX8 may emit light of the same color. For example, the second pixel PX2 and the eighth pixel PX8 are red pixels emitting red light, respectively.

The fourth pixel PX4 and the sixth pixel PX6 may emit light of the same color. For example, the fourth pixel PX4 and the sixth pixel PX6 are blue pixels emitting blue light, respectively.

Four adjacent pixels may form one unit pixel. For example, the first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the sixth pixel PX6 disposed adjacently form one unit pixel (hereinafter, referred to as a first unit pixel). . In addition, the third pixel PX3 , the fourth pixel PX4 , the eighth pixel PX8 , and another green pixel (not shown) that are adjacently arranged form another unit pixel (hereinafter, referred to as a second unit pixel). . Here, a green pixel (not shown) is connected to the mth emission control line ELm and is located adjacent to the fourth pixel PX4 and the eighth pixel PX8 . As described above, the adjacent first and second unit pixels share a green pixel (eg, the third pixel PX3 ) positioned therebetween. In addition, the second pixel PX2 of the first unit pixel forms another unit pixel together with the other three pixels adjacent to the upper side thereof, and the sixth pixel PX6 of the first unit pixel includes the other three pixels adjacent to the lower side thereof. Together with the pixels, it forms another unit pixel. That is, the display device of the present invention includes pixels having a PenTile structure.

Each of the pixels PX1 to PX8 includes a pixel electrode. For example, the first pixel PX1 includes a first pixel electrode PE1 , the second pixel PX2 includes a second pixel electrode PE2 , and the third pixel PX3 includes a third pixel The electrode PE3 is included, the fourth pixel PX4 includes the fourth pixel electrode PE4 , the fifth pixel PX5 includes the fifth pixel electrode PE5 , and the sixth pixel PX6 includes the sixth pixel PX6 . includes the sixth pixel electrode PE6 , the seventh pixel PX7 includes the seventh pixel electrode PE7 , and the eighth pixel PX8 includes the eighth pixel electrode PE8 .

Pixel electrodes included in pixels emitting light of the same color may have the same size. For example, the first pixel electrode PE1 , the third pixel electrode PE3 , the fifth pixel electrode PE5 , and the seventh pixel electrode PE7 of the green pixels may have the same size. Also, the second pixel electrode PE2 and the eighth pixel electrode PE8 of the red pixels may have the same size. Also, the fourth pixel electrode PE4 and the sixth pixel electrode PE6 of the blue pixels may have the same size.

Among the pixel electrodes, the pixel electrode of the green pixel may have the smallest size. For example, among the first to seventh pixel electrodes PE1 to PE7 , the first pixel electrode PE1 , the third pixel electrode PE3 , the fifth pixel electrode PE5 , and the seventh pixel electrode PE7 are It can have the smallest size.

The pixel electrode of the blue pixel may have a larger size than the pixel electrode of the red pixel. For example, the fourth pixel electrode PE4 may have a larger size than the second pixel electrode PE2 . Similarly, the fourth pixel electrode PE4 may have a larger size than the eighth pixel electrode PE8 . Also, the sixth pixel electrode PE6 may have a larger size than the second pixel electrode PE2 . Similarly, the sixth pixel electrode PE6 may have a larger size than the eighth pixel electrode PE8 .

Also, although not shown, each of the pixels PX1 to PX8 further includes first to seventh switching elements T1 to T7 and a storage capacitor Cst. For a detailed description of the first to seventh switching elements T1 to T7 and the storage capacitor Cst, refer to FIG. 3 and related descriptions.

As illustrated in FIG. 8 , the first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the fourth pixel PX4 are connected to the same scan line and the same emission control line. For example, the first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the fourth pixel PX4 may have an n−1 th scan line SLn−1 and an n th scan line SLn ), the n+1th scan line SLn+1, and the mth emission control line ELm are commonly connected.

The fifth pixel PX5 , the sixth pixel PX6 , the seventh pixel PX7 , and the eighth pixel PX8 are connected to the same scan line and the same emission control line. For example, the fifth pixel PX5 , the sixth pixel PX6 , the seventh pixel PX7 , and the eighth pixel PX8 have an n+1th scan line SLn+1 and an n+2th scan line (SLn+2), the n+3th scan line SLn+3, and the m+1th light emission control line ELm+1 are commonly connected.

The first pixel PX1 and the fifth pixel PX5 are commonly connected to the same data line. For example, the first pixel PX1 and the fifth pixel PX5 are commonly connected to the r−1 th data line DLr−1.

The second pixel PX2 and the sixth pixel PX6 are commonly connected to the same data line. For example, the second pixel PX2 and the sixth pixel PX6 are commonly connected to the r-th data line DLr.

The third pixel PX3 and the seventh pixel PX7 are commonly connected to the same data line. For example, the third pixel PX3 and the seventh pixel PX7 are commonly connected to the r+1th data line DLr+1.

The fourth pixel PX4 and the eighth pixel PX8 are commonly connected to the same data line. For example, the fourth pixel PX4 and the eighth pixel PX8 are commonly connected to the r+2 th data line DLr+2.

Hereinafter, first to first through which are commonly connected to the n-1th scan line SLn-1, the nth scan line SLn, the n+1th scan line SLn+1, and the mth emission control line ELm. The fourth pixels PX1 to PX4 are defined as a first pixel group. Then, the n+1th scan line SLn+1, the n+2th scan line SLn+2, the n+3th scan line SLn+3, and the m+1th light emission control line ELm+1 The fifth to eighth pixels PX5 to PX8 that are commonly connected to is defined as a second pixel group.

The first pixel group and the second pixel group are connected to different light emission control lines. At this time, the different light emission control lines are located adjacent to each other. For example, the first pixel group is connected to the mth emission control line ELm, and the second pixel group is connected to the m+1th emission control line ELm+1.

As shown in FIG. 8 , the above-described coupling groove 220 may be evenly disposed in the display area 100a of the substrate 100 .

As shown in FIG. 8 , the coupling groove 220 of the display area 100a is formed between the high potential line VDL adjacent to each other and the r−1th data line DLr−1 and the high potential line VDL adjacent to each other. ) and the rth data line DLr, between the high potential line VDL and the r+1th data line DLr+1 adjacent to each other, and the high potential line VDL and the r+2th data line DLr adjacent to each other. +2), respectively.

Similarly, the aforementioned extension 750b may be evenly disposed on the display area 100a of the substrate 100 .

The extended portion 750b of the display area 100a extends between the high potential line VDL and the r-1 th data line DLr-1 adjacent to each other, and the high potential line VDL and the r th data line DLr adjacent to each other. ), between the high potential line VDL and the r+1th data line DLr+1 adjacent to each other, and between the high potential line VDL and the r+2th data line DLr+2 adjacent to each other, respectively. can

9 is a detailed configuration diagram of the scan driver of FIG. 1 .

As shown in FIG. 9 , the scan driver 102 includes a plurality of driving switching elements TR, and the plurality of driving switching elements TR are to be connected to a plurality of clock lines CL. can

Each driving switching element TR receives a clock signal from a corresponding clock line, generates and outputs a scan signal based on the clock signal.

* The above-described coupling groove 220 and the extension part 750b may be disposed in the non-display area 100b of the substrate 100 . For example, the coupling groove 220 and the extension 750b of the non-display area 100b may be positioned between adjacent clock lines CL.

Meanwhile, although not shown, the above-described coupling groove 220 and the extension portion 750b may be located between other clock lines connected to the emission control driver 103 . That is, the above-described coupling groove 220 and the extension portion 750b may be located between adjacent ones of the other clock lines.

On the other hand, although not shown, the above-described coupling groove 220 and the extension portion 750b may not overlap the conductive pattern (eg, a scan line, a light emission control line, a data line, etc.) of the substrate 100 . It can be formed in any area.

10A to 10M are cross-sectional views illustrating a method of manufacturing a display device according to the present invention.

First, as shown in FIG. 10A , a first layer 111 , a second layer 112 , a third layer 113 , a fourth layer 114 , a buffer layer 120 on a carrier substrate 101 , A semiconductor layer 321 , a gate insulating layer 140 , a first interlayer insulating layer 150 , a second interlayer insulating layer 160 , a planarization layer 180 , and a pixel electrode PE are sequentially formed.

In addition, the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the fourth gate electrode GE4, the fifth gate electrode GE5, the sixth gate electrode GE6, The seventh gate electrode GE7, the n-1 th scan line SLn-1, the n th scan line SLn, the n+1 th scan line SLn+1, the emission control line EL, the initialization line ( IL), the capacitor electrode 201 , the first connection electrode 701 , the second connection electrode 702 , the third connection electrode 703 , the data line DL, and the high potential line VDL also include the carrier substrate 101 . ) is formed on

Next, as shown in FIG. 10B , an intermediate light blocking layer 190a is formed on the pixel electrode PE and the planarization layer 180 . The intermediate light blocking layer 190a may be formed on the pixel electrode PE and the planarization layer 180 by a chemical vapor deposition (CVD) method.

The intermediate light blocking film 190a may be made of, for example, a polyimide-based resin.

Next, as shown in FIG. 10C , the intermediate light blocking layer 190a is used as a mask and an etching process is performed. The planarization layer 180 , the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 are sequentially patterned by this etching process. In other words, each of the layers 180 , 160 , 150 , exposed by the intermediate light blocking layer 190a among the planarization layer 180 , the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 , 140) is selectively removed. Accordingly, the third intermediate hole 3 and the second intermediate hole 2 exposing the buffer layer 120 are formed.

The above-described planarization layer 180 , the second interlayer insulating layer 160 , the first interlayer insulating layer 150 , and the gate insulating layer 140 may be removed by a dry-etch method using an etching gas, respectively.

Then, as shown in FIG. 10D , an ashing process is performed. As a part of the intermediate light blocking layer 190a is removed by this ashing process, the light blocking layer 190 and the third hole 23 are formed. The light blocking layer 190 has a smaller thickness and width than the intermediate light blocking layer 190a , and the third hole 23 has a larger width than the third intermediate hole 3 .

Next, although not shown, a photoresist is formed on the entire surface of the carrier substrate 101 including the light blocking film 190 .

Thereafter, when a portion of the photoresist is selectively removed by the exposure process and the developing process, a photoresist pattern PR is formed as shown in FIG. 10E . The photoresist pattern PR exposes a portion of the buffer layer 120 . That is, the photoresist pattern PR masks the remaining portion except for a portion of the buffer layer 120 .

Subsequently, as shown in FIG. 10F , the photoresist pattern PR is used as a mask to perform an etching process. The buffer layer 120 and the fourth layer 114 are sequentially patterned by this etching process. In other words, portions of the respective layers 120 and 114 exposed by the photoresist pattern PR among the buffer layer 120 and the fourth layer 114 are selectively removed. Accordingly, the second hole 22 and the first hole 21 exposing the third layer 113 are formed.

The above-described buffer layer 120 and the fourth layer 114 may be removed by a dry-etch method using an etching gas, respectively.

Since the buffer layer 120 and the fourth layer 114 are inorganic materials, they may be removed by the dry etching described above. However, since the third layer 113 located under the fourth layer 114 is an organic material, this is a general dry etching method. is not well removed.

Meanwhile, the processes of FIGS. 10E and 10F may be performed simultaneously with the process of removing the insulating layer positioned on the bending portion 77 of the display device 1000 shown in FIG. 1 .

The display device 1000 is bent based on the bending part 77 . For example, the portion of the display device in which the data driver 104 is positioned is bent while rotating toward the rear surface of the display device 1000 with respect to the bending part 77 . In this case, a process of removing the insulating film of the bending portion 77 is performed so that the display device 1000 can be easily bent.

During the etching process of removing the insulating layer of the bending portion 77 , the above-described buffer layer 120 and the fourth layer 114 may be removed together. In this case, the buffer layer 120 and the fourth layer 114 may be selectively removed without a separate additional process.

Next, as shown in FIG. 10G , an etching process using the photoresist pattern PR as a mask is performed. The surface of the third layer 113 is patterned by this etching process. In other words, a portion of the surface of the third layer 113 exposed by the photoresist pattern PR is selectively removed. Accordingly, a groove 20 is created in the exposed surface of the third layer 113 .

Since the third layer 113 is made of an organic material, the third layer 113 may be removed by etching (eg, oxygen etching or oxygen ashing) using oxygen (O ₂ ) gas. Accordingly, during the oxygen etching process of FIG. 10G , the side surface of the fourth layer 114 (ie, the surface exposed by the first hole 21 ) is not removed, and only the third layer 113 made of an organic material is selectively selected. can be removed.

As the oxygen etching time increases, more of the third layer 113 is removed to increase the width of the groove 20 . Meanwhile, since the fourth layer 114 is not substantially removed during the oxygen etching process, the width of the first hole 21 is substantially maintained. When the oxygen etching time is sufficiently long and the width of the groove 20 of the third layer 113 is greater than the width of the first hole 21 , the groove 20 extends to the bottom of the fourth layer 114 . An under-cut phenomenon occurs. In other words, when the oxygen etching is performed for a long time enough to cause the under-cut phenomenon of the third layer 113 , the groove 20 of the third layer 113 is formed by the first hole ( 21) can have a larger width.

Then, when the photoresist pattern PR is removed, as shown in FIG. 10H , a coupling groove having a groove 20 , a first hole 21 , a second hole 22 , and a third hole 23 ( 220) is made.

Thereafter, as shown in FIG. 10I , the emission layer 512 and the common electrode 613 are sequentially formed. The emission layer 512 is formed on the pixel electrode PE in the emission region 900 , and the common electrode 613 is formed on the light blocking layer 190 and the emission layer 512 . In addition, the common electrode 613 is formed along the inner wall of the coupling groove 220 (ie, a portion of each film exposed by the coupling groove 220 ).

Thereafter, as shown in FIGS. 10J to 10L , a sealing portion 750 is formed. The sealing part 750 includes a first inorganic layer 751 , an organic layer 755 , and a second inorganic layer 752 . A method of manufacturing the sealing part 750 will be described as follows.

First, as shown in FIG. 10J , a first inorganic layer 751 is formed on the common electrode 613 .

Next, as shown in FIG. 10K , an organic layer 755 is formed on the first inorganic layer 751 .

Thereafter, as shown in FIG. 101 , a second inorganic layer 752 is formed on the organic layer 755 .

The sealing part 750 manufactured through FIGS. 10J to 10L includes a cover part 750a and an extension part 750b as shown in FIG. 10L . The extension 750b is inserted into the groove 20 through the third hole 23 , the second hole 22 , and the first hole 21 as shown in FIG. 10L .

Next, as shown in FIG. 10M , the carrier substrate 101 is removed from the first layer 111 .

Thereafter, as shown in FIG. 6 , the base layer 110 is attached to the first layer 111 .

11 is a view for explaining a method of forming a groove using a laser.

The groove 20 of the third layer 113 shown in FIG. 10G may be formed using laser light instead of the above-described oxygen etching.

For example, after the process of FIG. 10F , as shown in FIG. 11 , the laser light LL emitted from the laser device LS is incident on the surface of the third layer 113 . Then, the groove 20 is formed while the surface thereof is removed by the laser light LL. In other words, a portion of the surface of the third layer 113 exposed by the photoresist pattern PR is selectively removed by the laser light LL. Accordingly, a groove 20 is created in the exposed surface of the third layer 113 .

At this time, when the irradiation time of the laser light LL is sufficiently long or the intensity is sufficiently strong, an undercut is generated in the third layer 113 described above. In other words, when the irradiation time or intensity of the laser light LL is adjusted to such an extent that the under-cut phenomenon of the third layer 113 occurs, the groove 20 of the third layer 113 is formed in the fourth layer 114 . may have a greater width than the first hole 21 of

Meanwhile, the aforementioned laser light LL may be irradiated after the photoresist pattern PR is first removed. Specifically, the photoresist pattern PR may be removed immediately after FIG. 10F , and the laser light LL may be irradiated toward the exposed surface of the third layer 113 .

12 is a cross-sectional view of another embodiment taken along the line II-II' of FIG. 3 , and FIG. 13 is an enlarged view of part A of FIG. 12 . However, in FIG. 13 , the sealing part 750 and the common electrode 613 are omitted.

A portion of the encapsulation unit 750 is inserted into the pixel circuit unit 200 as shown in FIG. 12 . For example, the sealing part 750 includes a cover part 750a and an extension part 750b extending from the cover part 750a toward the pixel circuit part 200 , and the extension part 750b is a pixel. It is inserted into the circuit unit 200 .

To this end, the pixel circuit unit 200 and the light blocking layer 190 have a hole or a groove in a portion corresponding to the extension 750b of the sealing unit 750 . For example, the pixel circuit unit 200 includes a groove 40 , a first hole 41 , and a second hole 42 positioned to correspond to the extension portion 750b, and the light blocking film 190 includes the extension portion ( It includes a third hole 43 positioned to correspond to 750b).

The groove 40 of the pixel circuit unit 200 may be located, for example, in the first interlayer insulating layer 150 of the pixel circuit unit 200 . The first hole 41 of the pixel circuit unit 200 may be located, for example, in the second interlayer insulating layer 160 of the pixel circuit unit 200 . The second hole 42 of the pixel circuit unit 200 may be located, for example, in the planarization layer 180 of the pixel circuit unit 200 .

The groove 40 , the first hole 41 , the second hole 42 , and the third hole 43 are positioned to correspond to each other. Also, adjacent ones of the groove 40 , the first hole 41 , the second hole 42 , and the third hole 43 are connected to each other.

The first hole 41 may be positioned between the groove 40 and the second hole 42 .

12 and 13 , the width of the groove 40 gradually increases along a direction (eg, Z-axis direction) from the first interlayer insulating film 150 to the second interlayer insulating film 160 . (or diameter). 13 , the width 40d (or diameter) of the groove 40 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 40d (or diameter) of the groove 40 means the maximum width (or maximum diameter) or average width (or average diameter) of the groove 40 .

At least one of the inner walls W11 and W22 facing each other of the groove 40 is inclined at a predetermined angle with respect to the interface S11 and S22 between the first interlayer insulating film 150 and the second interlayer insulating film 160 . For example, an angle formed between at least one of the inner walls W11 and W22 facing each other of the groove 40 and the interfaces S11 and S22 is an obtuse angle. As a more specific example, the angle θ11 between the inner wall W11 and the interface S11 adjacent to the inner wall W11 is an obtuse angle.

The first hole 41 has a width (or diameter) that gradually increases along the Z-axis direction. The width 41d (or diameter) of the first hole 41 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 41d (or diameter) of the first hole 41 means the maximum width (or maximum diameter) or average width (or average diameter) of the first hole 41 .

The second hole 42 has a width (or diameter) that gradually increases along the Z-axis direction. The width 42d (or diameter) of the second hole 42 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 42d (or diameter) of the second hole 42 means the maximum width (or maximum diameter) or average width (or average diameter) of the second hole 42 .

The third hole 43 may have a width (or diameter) that gradually increases along the Z-axis direction. The width 43d (or diameter) of the third hole 43 is a value measured in the X-axis direction (or the Y-axis direction). In this case, the width 43d (or diameter) of the third hole 43 means the maximum width or average width of the third hole 43 .

The width 40d (or diameter) of the groove 40 is greater than the width 41d (or diameter) of the first hole 41 . 13 , the cross-sections of the groove 40 and the first hole 41 may have an anchor shape. In this case, the cross section of the extended portion 750b inserted into the groove 40 and the first hole 41 may also have an anchor shape.

In a plan view, the first hole 41 is surrounded by the groove 40 . Also, in the plan view of FIG. 1 , the first hole 41 and the groove 40 overlap.

In a plan view, the first hole 41 , the second hole 42 and the groove 40 are surrounded by the third hole 43 .

The width 42d (or diameter) of the second hole 42 is greater than the width 41d (or diameter) of the first hole 41 .

The width 43d (or diameter) of the third hole 43 is greater than the width 42d (or diameter) of the second hole 42 .

The extended portion 750b of the above-described sealing unit 750 is inserted (or buried) in the groove 40, the first hole 41, the second hole 42, and the third hole 43 having such a structure. do. For example, the extension part 750b is inserted into the groove 40 by sequentially passing through the third hole 43 , the second hole 42 , and the first hole 41 . At this time, since the width 40d (or diameter) of the groove 40 is larger than the width 41d (or diameter) of the first hole 41 , the groove 40 , the first hole 41 , and the second hole 42 . ) and the extended portion 750b inserted into the third hole 43 are not well separated in the Z-axis direction. Therefore, the bonding force between the sealing part 750 and its lower structure may be improved.

The aforementioned groove 40 , the first hole 41 , the second hole 42 , and the third hole 43 may be located in the display area 100a of the substrate 100 . For example, when defining the entire hole consisting of the groove 40, the first hole 41, the second hole 42, and the third hole 43 as one coupling groove 440, the coupling groove ( 440 and the extension 750b may be located in the display area 100a of the substrate 100 .

The coupling groove 440 and the extension 750b of the display area 100a may be positioned between the high potential line VDL and the data line DL adjacent to each other.

In addition, the above-described coupling groove 440 and the extension part 750b may be disposed in the non-display area 100b of the substrate 100 . For example, the coupling groove 440 and the extension 750b of the non-display area 100b may be positioned between adjacent clock lines CL.

Meanwhile, although not shown, the above-described coupling groove 440 and the extension portion 750b may be located between clock lines connected to the emission control driver 103 .

The groove of FIG. 12 may be formed by the above-described oxygen etching or laser light LL. In this case, the first interlayer insulating layer 150 may be made of an organic material, and the second interlayer insulating layer 160 may be made of an inorganic material.

Meanwhile, when both the first interlayer insulating layer 150 and the second interlayer insulating layer 160 are made of an inorganic material, the first interlayer insulating layer 150 and the second interlayer insulating layer 160 may be removed by general dry etching. In this case, the greater the difference in the etch rate between the first interlayer insulating layer 150 and the second interlayer insulating layer 160 , the better. For example, it is preferable that the first interlayer insulating layer 150 has a higher etch rate than that of the second interlayer insulating layer 160 .

14 is a cross-sectional view of another embodiment taken along the line II-II' of FIG. 3 .

As shown in FIG. 14 , any one of the inner walls facing each other of the groove 20 and one of the inner walls facing each other of the first hole 21 may be positioned on a straight line. Accordingly, the cross section of the groove 20 may have an asymmetrical shape with respect to the Z axis.

For example, the groove 20 and the first hole 21 located on the left side of FIG. 14 are defined as the left groove and the first left hole, respectively, and the groove 20 and the first hole 21 located on the right side of FIG. 14 , respectively. When ? is defined as the right groove and the first right hole, respectively, the right inner wall of the left groove and the right inner wall of the first left hole are located on a straight line, and the left inner wall of the right groove and the left inner wall of the first right hole are located on a straight line.

The structure of the groove 20 shown in FIG. 14 may be made by the above-described laser light LL. For example, according to the change of the irradiation angle of the laser light LL, the groove 20 having the structure shown in FIG. 14 may be made.

15 is a cross-sectional view of another embodiment taken along the line II-II′ of FIG. 3 .

As shown in FIG. 15 , any one of the inner walls facing each other of the groove 40 and one of the inner walls facing each other of the first hole 41 may be positioned on a straight line. Accordingly, the cross section of the groove 40 may have an asymmetrical shape with respect to the Z axis.

For example, the groove 40 and the first hole 41 located on the left side of FIG. 15 are defined as the left groove and the first left hole, respectively, and the groove 40 and the first hole 41 located on the right side of FIG. 15 , respectively. When ? is defined as the right groove and the first right hole, respectively, the right inner wall of the left groove and the right inner wall of the first left hole are located on a straight line, and the left inner wall of the right groove and the left inner wall of the first right hole are located on a straight line.

The structure of the groove 40 shown in FIG. 15 may be made by the above-described laser light LL. For example, according to a change in the irradiation angle of the laser light LL, the groove 40 having the structure shown in FIG. 15 may be formed.

*

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

100: substrate 110: base layer
111: first floor 112: second floor
113: third layer 114: fourth floor
200: pixel circuit unit 120: buffer
140: gate insulating film 150: first interlayer insulating film
160: second interlayer insulating film 180: planarization film
190: light shielding film 900: light emitting region
LED: light emitting element PE: pixel electrode
512: light emitting layer 613: common electrode
DL: data line 321: semiconductor layer
702: second connection electrode VDL: high potential line
GE3: third gate electrode 750: sealing part
751: first inorganic film 755: organic film
752: second inorganic membrane 750a: cover part
750b: extension 20: groove
21: Hall 1 22: Hall 2
23: Hall 3

Claims (14)

Board;
a switching element on the substrate;
a pixel electrode connected to the switching element;
a light emitting layer on the pixel electrode;
and a sealing portion including a cover portion on the light emitting layer and an extension portion extending from the cover portion toward the substrate,
The extension portion includes a first portion disposed inside the groove of the substrate and a second portion disposed outside the groove,
wherein the second portion of the first and second portions of the extension is disposed closer to the cover portion,
A display device having a size different from a width of the first portion of the extension portion and a width of the second portion of the extension portion. The method of claim 1,
A width of the first portion is greater than a width of the second portion. 3. The method of claim 2,
a pixel circuit unit including the switching element; and
a light blocking film disposed on the pixel circuit unit and defining a light emitting area in which the light emitting layer is located;
the pixel circuit part has a second hole passing therethrough;
the light blocking film has a third hole corresponding to the second hole;
The substrate is
a third layer having the groove corresponding to the second hole; and
a fourth layer disposed between the third layer and the pixel circuit unit and having a first hole positioned between the groove and the third hole;
the extension portion of the sealing portion is inserted into the second hole, the third hole, the first hole and the groove;
the first part is positioned to correspond to the groove, and the second part is positioned to correspond to the first hole;
The groove has a greater width than the first hole. 4. The method of claim 3,
The groove has a width that gradually increases in a direction from the third layer toward the fourth layer. 5. The method of claim 4,
At least one of the inner walls facing each other of the groove is inclined at a predetermined angle with respect to an interface between the third layer and the fourth layer. 6. The method of claim 5,
An angle between at least one of the inner walls of the groove facing each other and the interface is an obtuse angle. 4. The method of claim 3,
The first hole is surrounded by the groove. 4. The method of claim 3,
The first hole and the groove overlap each other. 4. The method of claim 3,
The second hole, the third hole, the first hole, and the groove are located in at least one of a display area and a non-display area of the substrate. 10. The method of claim 9,
The second hole, the third hole, the first hole, and the groove are located in the display area and are located between a high potential line and a data line adjacent to each other. 10. The method of claim 9,
and a driving circuit unit positioned in the non-display area and connected to a scan line or a light emission control line of the pixel circuit unit. 12. The method of claim 11,
a plurality of clock lines positioned in the non-display area and connected to the driving circuit unit;
The second hole, the third hole, the first hole, and the groove are located between adjacent clock lines. 4. The method of claim 3,
One of the inner walls facing each other of the groove and one of the inner walls facing each other of the second hole are positioned in a straight line. 4. The method of claim 3,
One of the third and fourth layers includes an organic material and the other includes an inorganic material.

Images