KR102384589B1 - Method for monitoring and controlling status of an embedded terminal device using Power Management IC and an embedded terminal device for the same - Google Patents

Abstract

Disclosed are a calculation device and a method for controlling a terminal device including a PMIC. The method includes a step of deactivating a watch dog of the PMIC while a boot loader of the terminal device is executed. In addition, the method includes a step of activating the watch dog when an application program for monitoring executed from the terminal device generates a call to activate the watch dog.

Description

Method for monitoring and controlling status of an embedded terminal device using Power Management IC and an embedded terminal device for the same}

The present invention relates to computing technology, and in particular, to technology for periodically monitoring the state of an embedded terminal, automatically recognizing when the terminal is in a holding state at an unspecified time, and continuously providing a service by automatically rebooting the terminal. it's about

Public transportation embedded payment terminals (hereinafter, simply 'terminals') installed on buses and subways have been used to provide transportation services. In this case, the terminal must continuously provide a traffic service during the operating time of the vehicle. Therefore, when some terminals are stopped, there is a problem that a load may be concentrated on the other terminals because the payment service must be provided using another terminal on standby.

In addition, in order to monitor the state of the terminal, a mechanism for periodically recognizing the state of the terminal is used by interworking the terminal with a server provided separately from the terminal. If the terminal is in an abnormal state (terminal stop phenomenon), the monitoring server cannot distinguish whether a network connection error has occurred or whether the state of the terminal itself is abnormal, but can recognize that the terminal is not operating normally.

However, since there is no way to remotely control the terminal from the monitoring server, it is inconvenient to have to manually control the terminal (Power Off->On) by notifying the person in charge who operates the terminal to reboot the terminal and run the service. There is a difference in the normal recovery time of the terminal depending on the recognition and manual action time.

Although it is possible to check and control the state of the terminal in this way, it is premised on the condition that the CPU (= arithmetic unit) of the terminal and the network connecting the terminal and the server operate normally. That is, in a state in which the kernel (OS) of the terminal is operating normally, the terminal periodically checks the state of the terminal using a monitoring program that is an application program. The monitoring program interworks with the monitoring server to periodically provide status information of the terminal to the monitoring server. The monitoring server may indicate the state of the terminal and define a mutual control command for controlling a specific terminal. When the monitoring server provides a predefined command to the terminal, the monitoring program of the terminal performs software control according to the command. To this end, an environment in which the connection to the monitoring server is normally operated in a state in which the terminal operates normally is required.

The monitoring server transmits a control command to the terminal. The terminal is controlled by the control command. Therefore, when the application service of the terminal is stopped or the kernel is stopped at an unspecified time, the driver or the person in charge of the railway can check this, but in order to reboot the stopped terminal and provide the service again, manually turn off the power and then turn it on There is a problem in that it needs to be controlled again with the controller or a separately provided control device must be used.

In addition, since an operator such as a bus driver or a railway operator must directly monitor the terminal status and manually re-execute it through power control, a lot of difference occurs in the normal recovery time of the terminal depending on the time the operator recognizes it and the time of power control will do

In the present invention, the terminal status is periodically checked by using the watchdog function of the PMIC, which is designed to stably provide power to the embedded terminal, and when the terminal is in the holding state, SW for rebooting the terminal in the PMIC An object of the present invention is to provide a technology for automatically performing reset or power control to control a terminal to operate again.

In the present invention, the state of the terminal is periodically checked in the terminal's internal system without changing the hardware of the terminal in service, and when an abnormal phenomenon such as a stop phenomenon occurs, it is quickly automatically recognized and the terminal is rebooted to provide the service normally. We want to improve our skills.

According to one aspect of the present invention, the function for checking the status of the terminal and rebooting the terminal when the terminal is stopped utilizes the watchdog function of the Power Management Integrated Circuit (PMIC) that stably supplies the power inside the terminal. technology is provided. PMIC is a power management integrated circuit, a chip that receives main power input and converts it into stable and efficient voltage or current required by electronic devices, rectifies, distributes, and controls. The PMIC provides a function to enable/disable the watchdog status information and functions through the interface (ex I2C) interlocked with the CPU.

A terminal provided according to an aspect of the present invention includes a PMIC, a CPU, a memory, a Real Time Clock (RTC), and a SAM. The PMIC can distribute a stable and efficient voltage and current to hardware. PMIC, CPU, memory, RTC (Real Time Clock), and SAM can be connected through the same interface as I2C.

In the terminal provided according to one aspect of the present invention, when booting, the boot loader initializes the hardware of the terminal. Then, the bootloader requests the terminal to release the watchdog function included in the PMIC from the PMIC. As a result, by disabling the watchdog function of the PMIC at boot time, the terminal is not controlled by the PMIC during booting.

When the watchdog function of the PMIC is activated, the watchdog function operates if a command to deactivate the watchdog is not executed or the power of the terminal is not completely turned off. In this case, if the watchdog is not deactivated before the watchdog timer expires, the terminal continues to reboot. As a result, the terminal is in a state in which it cannot operate normally. Usually, the watchdog timer is set for a very short time (4 seconds) and the value of the timer cannot be changed. Therefore, considering this case, the watchdog function should be deactivated within a short time while the terminal is rebooting. Therefore, the terminal provided according to an aspect of the present invention deactivates the PMIC watchdog timer in the boot loader entry step (1st Boot Loader) after rebooting.

A terminal provided according to an aspect of the present invention is an embedded terminal including a CPU, DRAM, and a booting device. The CPU includes a core, a DRAM controller, a boot device controller, internal ROM, and SRAM and the like.

The internal ROM may include an iROM code. And the booting device may be a NAND device or an MMC device. Codes for the first boot loader, the second boot loader, and the OS may be recorded in the booting device.

While the terminal is booting, the code recorded in the internal ROM, the code recorded in the first to the loader, the code recorded in the second boot loader, and the OS code may be sequentially executed.

While the first loader is being executed, the processor's entry into supervisor mode and interrupt inhibition are executed first. Next, set the speed of the processor. Then initialize the memory. Then disable the watchdog of the PMIC.

Execution of the function of the first boot loader should be completed within a short time. In addition, due to the limitation of the size of the code recorded in the first boot loader, the first loader should operate as simply as possible. Accordingly, the configuration for deactivating the watchdog of the PMIC in order to deactivate the function of the watchdog of the PMIC is simply composed of a command generator and a signal controller.

The command generator serves to generate a command for disabling the watchdog function of the PMIC. In addition, the signal controller includes a transmitter for transmitting a signal including a deactivation command generated from the command generator through an interface linked to a PMIC, and a receiver for receiving the execution result of the command.

When the kernel of the terminal is normally driven, a monitoring process, which is an application program for monitoring, is automatically executed. The monitoring process transmits a message for activating the watchdog function of the PMIC to the PMIC, and the PMIC receives it and activates the watchdog function.

The monitoring process can be operated as a separate application program or as a separate function (thread) in the application program for the main service.

After that, the monitoring process periodically interworks with the PMIC to perform a receiving function to check the watchdog status information of the PMIC, and transmits a message to the PMIC indicating that the terminal is operating normally by generating a transaction. .

Thereafter, the monitoring process periodically interworks with the PMIC to generate a transaction, transmits a message for confirming the watchdog status information of the PMIC, and receives status information data therefor.

If the terminal becomes in an abnormal state (terminal stops) and the monitoring process fails to transmit a periodic transaction message to the PMIC, as a result, the PMIC cannot receive the transaction message within the watchdog timeout time. In this case, the PMIC automatically reboots the terminal.

After the terminal is normally driven, the monitoring process is automatically executed. The function of the monitoring process consists of a command control function, a transaction processing function, and a message processing function.

The command control function is a function capable of setting activation/deactivation of the watchdog function, and generates a command to be transmitted to the PMIC.

The transaction processing function periodically generates a command for processing a transaction with the PMIC, and checks the status by analyzing the response from the PMIC.

The message processing function has a function of generating and processing a message for transmitting a command and receiving a response based on an interface interworking with the PMIC.

According to an aspect of the present invention, a terminal including an arithmetic unit and a PMIC may be provided. The arithmetic unit is configured to transmit a first command to the PMIC to deactivate a watchdog controlled by the PMIC while the bootloader of the terminal is running. The PMIC is configured to deactivate the watchdog according to the first command. The arithmetic unit is configured to transmit a second command to activate the watchdog to the PMIC when the application program executed in the terminal generates a call to activate the watchdog. And the PMIC is configured to activate the watchdog according to the second command.

At this time, the PMIC is configured to initialize a timer of the watchdog after activating the watchdog according to the second command to execute the timer, and output a system reset signal when the timer expires. there may be

In this case, the system reset signal may be provided to devices other than the PMIC among devices included in the terminal.

In this case, the application program may be configured to repeatedly generate a call to activate the watchdog according to a preset schedule.

In this case, the application program may be configured to repeatedly generate a call to activate the watchdog according to a third predetermined period.

In this case, the third period may be shorter than the second period between the reset of the timer and the expiration of the timer.

According to an aspect of the present invention, a terminal control method for controlling a terminal including an arithmetic unit and a PMIC may be provided. The terminal control method may include: transmitting, by the computing device, a first command to the PMIC to deactivate a watchdog controlled by the PMIC while the bootloader of the terminal is running; deactivating, by the PMIC, the watchdog according to the first command; transmitting, by the arithmetic unit, a second command to activate the watchdog to the PMIC when the application program executed in the terminal generates a call to activate the watchdog; and activating, by the PMIC, the watchdog according to the second command.

In this case, the method for controlling the terminal may further include, by the PMIC, after activating the watchdog according to the second command, initialize a timer of the watchdog and execute the timer. In addition, the PMIC may be configured to output a system reset signal when the timer expires.

At this time, the application program is configured to repeatedly generate a call to activate the watchdog according to a third predetermined period, and the third period is until the reset of the timer and expiration of the timer. It may be shorter than the second period.

In this case, the system reset signal may be provided to devices other than the PMIC among devices included in the terminal.

In this case, the application program may be configured to repeatedly generate a call to activate the watchdog according to a preset schedule.

According to the present invention, it is possible to periodically check the terminal status and automatically control (reboot) the terminal to operate normally when a terminal error (stoppage) occurs at an unspecified time.

According to the present invention, the state of the terminal is checked using the watchdog function of the PMIC without changing the hardware of the existing terminal in order to check and control the terminal state, and when the terminal is in an abnormal state (stopped phenomenon), it is automatically detected By recognizing and controlling (rebooting) the terminal, continuous and stable service can be provided.

1 shows the configuration of a terminal provided according to an embodiment of the present invention.
FIG. 2 shows the internal structure of the CPU and the detailed configuration of the memory shown in FIG. 1 .
3 is a flowchart illustrating a bootloading process according to an embodiment executed by the code for the first bootloader shown in FIG. 2 .
4 shows functions included in the first boot loader.
5 is a flowchart illustrating a terminal state control method provided according to an embodiment of the present invention.
FIG. 6 is for explaining a process in which a reset is automatically executed due to a terminal stop phenomenon in the terminal state control method shown in FIG. 5 .
7 is a flowchart illustrating a comparative example showing a method compared to the method shown in FIG. 6 .
8 illustrates a function of a monitoring process executed by an application program provided according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terminology used herein is for the purpose of helping the understanding of the embodiments, and is not intended to limit the scope of the present invention. Also, singular forms used hereinafter include plural forms unless the phrases clearly indicate the opposite.

1 shows the configuration of a terminal provided according to an embodiment of the present invention.

The terminal 100 may include a PMIC 10 , a CPU 20 , a memory 30 , and a Real Time Clock (RTC) 40 . The terminal 100 may further include a SAM 50 .

The CPU 20 and the PMIC 10 may be connected to each other through an I2C interface to communicate with each other. The CPU 20 , the memory 30 , the RTC 40 , and the SAM 50 may communicate with each other through a wired connection.

The terminal 100 may further include a power supply unit, a network communication unit, and a short-range communication unit (not shown).

FIG. 2 shows the internal structure of the CPU and the detailed configuration of the memory shown in FIG. 1 .

The CPU 20 may include an internal ROM 121 , a core 122 , an SRAM 123 , a DRAM controller 124 , and a NAND controller 125 .

The internal ROM 121 may be a non-volatile memory.

The SRAM 123 may be a volatile memory.

The DRAM controller 124 may be a term referring to an IP that controls a volatile memory external to the CPU 20 .

Here, IP may mean a circuit having a specific function included in an IC chip that is an independent transaction target. The IC chip manufacturer may design all the circuits inside the IC chip, but information on circuits having some of the functions may be purchased from another company and integrated into the IC chip. The information about the circuit may be downloadable software or data, or an intangible property that can be traded through media such as a CD. The IP may be a term meaning information specifying a specific circuit as such intangible property.

The NAND controller 125 may be a term referring to an IP that controls a nonvolatile memory external to the CPU 20 .

The memory 30 may include a DRAM 31 , which is a volatile memory, and a non-volatile memory 32 . The non-volatile memory 32 may be constituted of, for example, a NAND memory, an MMC memory, or the like.

Codes for a boot loader and codes for an OS may be recorded in the non-volatile memory 32 .

The code for the boot loader may be divided into a code for a first boot loader that is executed first and a code for a second boot loader that is executed later.

3 is a flowchart illustrating a bootloading process according to an embodiment executed by the code for the first bootloader shown in FIG. 2 .

The bootloading process may be executed in the core of the CPU 20 .

The bootloading process may include the following steps.

In step S510, the bootloading process executes the processor to enter the supervisor mode and disable interrupt.

In step S520, the bootloading process may set the speed of the processor.

In step S530 , the bootloading process may initialize a memory external to the CPU using a processor.

In step S540 , the bootloading process may deactivate the watchdog included in the PMIC 10 .

In an embodiment, the code for the second bootloader may be executed after deactivation of the watchdog included in the PMIC 10 is completed.

4 shows the functions included in the first boot loader.

In order to execute the function of the first bootloader described in FIG. 3 , the code for the first bootloader may include a command generation function and a signal control function.

The command generation function may include a function in which the bootloader generates a watchdog release command, ie, a watchdog deactivation command, to the PMIC 10 .

The signal control function may include a command transmission function and a command reception function. The command transmission function may include a function in which the bootloader transmits the watchdog deactivation command to the PMIC 10 .

5 is a flowchart illustrating a terminal state control method provided according to an embodiment of the present invention.

In FIG. 5 , the PMIC 10 , the boot loader 21 , the kernel 22 , and the application program 23 are presented as subjects for exchanging messages.

Among them, the boot loader 21 , the kernel 22 , and the application program 23 may be functional modules executed in the CPU 20 . In order to execute the boot loader 21, the kernel 22, and the application program 23 in the CPU 20, the memory 30 includes the boot loader 21, the kernel 22, and an instruction code set for executing the application program 23 , and the CPU 20 may read and execute the instruction code set.

In an embodiment, the PMIC 10 may be a chip provided separately from the CPU 20 .

In one embodiment, when the terminal 100 is rebooted by S/W reset, if the watchdog of the PMIC 10 was already activated before the reboot, the watchdog after the rebooting The dog may be automatically activated (step S110). Here, the S/W reset may mean rebooting the terminal in a power-on state.

Unlike the S/W reset situation, when the PMIC 10 is powered off (power off) and the PMIC 10 starts to be powered on (power on) and booting is performed, the watchdog It can also be disabled.

When the S/W reset for the terminal 100 is performed, the process of the boot loader 21 may be started.

In step S111 , the bootloader 21 may transmit a watchdog release command to the PMIC 10 . The watchdog release command may be transmitted by the first bootloader.

In step S112 , the PMIC 10 may deactivate the watchdog included in the PMIC 10 according to the watchdog release command.

In step S121 , the kernel 22 may execute a booting process.

When booting is completed, in step S130, a predetermined application program 23 may be executed. The application program 23 may be a dedicated monitoring program for monitoring whether the terminal 100 is stopped. That is, in step S130, a predetermined monitoring process corresponding to the application may be executed.

In step S131 , the application program 23 may transmit a call requesting watchdog setting to the kernel 22 . The watchdog setting request may be a request for activating the watchdog and resetting the timer.

In step S132 , the kernel 22 may transmit a command requesting watchdog setting to the PMIC 10 .

In step S133, the PMIC 10 may set the watchdog according to a command requesting the watchdog setting. That is, the PMIC 10 may activate the watchdog and execute a timer reset.

The PMIC 10 may automatically reset a timer of the watchdog immediately after activating the watchdog.

In step S134, a timer reset in which the timer of the watchdog is reset may occur, and a countdown of the timer may start.

In this case, the count period of the timer may be expressed as T2.

In step S150, the PMIC 10 may output a system reset signal. However, the system reset signal may be generated only when the counter of the timer reaches a specific value, for example, zero (0).

The system reset signal may be transmitted to, for example, various chips of the terminal 100 . When the chips are reset, the bootloader process can be restarted. When the boot loader 21 is restarted according to the system reset signal, step S112 is executed again.

However, if a predetermined timer reset condition is satisfied in step S134, the timer reset may occur again before the timer reaches the specific value. When the timer reset occurs, the count of the timer may be reset to a predetermined initial value.

The predetermined timer reset condition may be generated by the application program 23 . A process for generating the predetermined timer reset condition will be described through the following steps.

In step S141, the application program 23 may transmit a call (command) requesting reset of the PMIC watchdog timer to the kernel 22 through a transaction with the PMIC. Step S141 may be repeated by a predetermined period T3 (=reset call period).

PMIC performs command processing and reset watchdog timer through application program and transaction execution.

In step S142 , the kernel 22 may transmit a command requesting reset of the watchdog to the PMIC 10 .

In step S143, the PMIC 10 executes a command according to a transaction, transmits a response thereto, and restarts the step S134 of requesting a timer reset of the watchdog to restart the timer. A reset may set the count to the predetermined initial value and restart the count down of the timer.

In this way, step S134 is repeatedly restarted by performing a transaction with an application program after step 133, and when the PMIC 10 does not perform a transaction with an application program, the timer expires and the It may be configured to perform a system reset.

If the count period T2 of the timer of the PMIC 10 is shorter than the reset call period T3 of the application program 23, the terminal 100 will fall into an abnormal system reset loop. Therefore, the count period T2 of the timer should be longer than the reset call period T3.

At least two cases may occur when the PMIC 10 fails to perform the transaction from the kernel 22 . First, the application program 23 is unintentionally stopped. Second, the kernel 22 is unintentionally stopped. A state in which both the application program 23 and the kernel 22 are stopped may exist.

In one embodiment, steps S131 and S132 are steps that are executed only once after the terminal 100 is powered on and S/W reset, respectively, whereas steps S141 and S142 are It is a step that can be repeatedly executed a plurality of times after the terminal 100 is powered on and S/W is reset, respectively.

FIG. 6 is for explaining a process in which a reset is automatically executed due to a terminal stop phenomenon in the terminal state control method shown in FIG. 5 .

The flowchart shown in FIG. 6 is the same as that shown in FIG. 5 .

If the application program 23 is stopped while proceeding from step S131 to step S141 (91), step S141 is not executed. Alternatively, after step S141 is executed, if the application program 23 is stopped before step S141 is executed again according to the reset call period T3 (91), step S141 is not executed. does not As a result, steps S142 and S143 are not sequentially executed. As a result, the timer expires by step S134, and eventually the system reset occurs.

Also, if the kernel 22 is stopped between steps S141 and S142 (93), step S142 is not executed. As a result, step S143 is not executed in series. As a result, the timer expires by step S134, and eventually the system reset occurs.

When the kernel 22 is stopped, there is a possibility that the application program 23 is stopped.

7 is a flowchart illustrating a comparative example showing a method compared to the method shown in FIG. 6 .

FIG. 7 is for explaining a case in which a system reset occurs according to the stopping phenomenon of the kernel 22 or the application program 23 as shown in FIG. 6 .

In the embodiment shown in FIG. 7 , steps S111 and S112 shown in FIG. 5 do not exist. As a result, in the embodiment shown in FIG. 7 , the watchdog of the PMIC 10 remains activated immediately after the system reset by step S150 .

When the system reset is performed, the system reset proceeds only to devices other than the PMIC 10 , and the state of the PMIC 10 may not be changed. As a result, when the system reset is performed, the system reset signal is transmitted only to devices other than the PMIC 10 , and the system reset signal may not change the state of the PMIC 10 .

As a result, the state of the PMIC 10 immediately after the system reset is the same as the state of the PMIC 10 immediately before the system reset. Accordingly, the timer period T2 of the PMIC 10 does not change.

At this time, when the system reset is made, when the timer of the PMIC 10 reaches the specific value, for example, zero (0), the count of the timer is cyclically returned to the predetermined initial value. , so you can start counting down again. That is, the countdown of the timer may start again from the point in time when the system reset is performed.

In this case, if the length T4 of the time period from the system reset time to the time when step S131 occurs is shorter than the timer period T2, the timer expires again before step S133 is performed and the timer is reset. will be. In this case, the PMIC 10 will output the system reset, and the terminal 100 will be reset abnormally.

However, the length T4 of the time period may change according to the state of the power supply of the terminal 100 and operating conditions of the bootloader 21 and the kernel 22 . Accordingly, it is not guaranteed that the length T4 of the time period is longer than the timer period T2.

That is, as in the embodiment shown in FIG. 6 , when steps S111 and S112 shown in FIG. 5 do not exist, after the system reset is executed by the watchdog of the PMIC 10 , the application An abnormal reset situation in which the terminal 100 is abnormally reset cannot be excluded because the timer expires again before the program 23 is executed again. Accordingly, steps S111 and S112 shown in FIG. 5 are necessary steps to solve this problem.

On the other hand, if the countdown of the timer is already started in step S110, which is executed after the terminal 100 is S/W reset in the power-on state and rebooting is started, the abnormal reset situation may occur even in this case. I can understand.

8 illustrates a function of a monitoring process executed by an application program provided according to an embodiment of the present invention.

After the terminal 100 is normally driven, the monitoring process is automatically executed by the application program 23 . The function of the monitoring process consists of a command control function, a transaction processing function, and a message processing function.

By using the above-described embodiments of the present invention, those skilled in the art will be able to easily implement various changes and modifications within the scope without departing from the essential characteristics of the present invention. The content of each claim in the claims may be combined with other claims without reference within the scope that can be understood through this specification.

Claims (11)

A terminal including an arithmetic unit and a PMIC, comprising:
the arithmetic unit transmits to the PMIC a first command to deactivate a watchdog controlled by the PMIC while the bootloader of the terminal is running;
the PMIC is configured to deactivate the watchdog according to the first command;
the arithmetic unit, when an application program executed in the terminal generates a call to activate the watchdog, transmits a second command to activate the watchdog to the PMIC;
the PMIC is configured to activate the watchdog according to the second command;
terminal. The method of claim 1,
the PMIC is configured to initialize a timer of the watchdog after activating the watchdog according to the second command to execute the timer, and output a system reset signal when the timer expires;
terminal. The terminal according to claim 2, wherein the system reset signal is provided to devices other than the PMIC among devices included in the terminal. The terminal of claim 1, wherein the application program repeatedly generates a call to activate the watchdog according to a preset schedule. The terminal according to claim 4, wherein the application program is configured to repeatedly generate a call to activate the watchdog according to a third predetermined period. 6. The method of claim 5,
the PMIC is configured to initialize a timer of the watchdog to execute the timer after activating the watchdog according to the second command;
output a system reset signal when the timer expires, and
The third period is shorter than a second period from reset of the timer to expiration of the timer. A terminal control method for controlling a terminal including an arithmetic unit and a PMIC, comprising:
transmitting, by the arithmetic unit, a first command to deactivate a watchdog controlled by the PMIC to the PMIC while the boot loader of the terminal is running;
deactivating, by the PMIC, the watchdog according to the first command;
transmitting, by the arithmetic unit, a second command to activate the watchdog to the PMIC when the application program executed in the terminal generates a call to activate the watchdog; and
activating, by the PMIC, the watchdog according to the second command;
containing,
terminal control method. 8. The method of claim 7,
after the PMIC activates the watchdog according to the second command, initializes a timer of the watchdog and executes the timer;
further comprising,
The PMIC is configured to output a system reset signal when the timer expires,
terminal control method. 9. The method of claim 8,
The application program is configured to repeatedly generate a call to activate the watchdog according to a third predetermined period, and
The third period is shorter than the second period between the reset of the timer and the expiration of the timer,
terminal control method. The method of claim 8, wherein the system reset signal is provided to other devices except for the PMIC among devices included in the terminal. The method of claim 7, wherein the application program repeatedly generates a call to activate the watchdog according to a preset schedule.

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