KR102380670B1 - 메모리 제어기에서의 세분화된 대역폭 프로비저닝 - Google Patents

메모리 제어기에서의 세분화된 대역폭 프로비저닝 Download PDF

Info

Publication number
KR102380670B1
KR102380670B1 KR1020167031743A KR20167031743A KR102380670B1 KR 102380670 B1 KR102380670 B1 KR 102380670B1 KR 1020167031743 A KR1020167031743 A KR 1020167031743A KR 20167031743 A KR20167031743 A KR 20167031743A KR 102380670 B1 KR102380670 B1 KR 102380670B1
Authority
KR
South Korea
Prior art keywords
memory
dram
request
bandwidth
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020167031743A
Other languages
English (en)
Korean (ko)
Other versions
KR20160144482A (ko
Inventor
뇬 토아이 콰치
수잔 캐리
제프리 앤드류스
존 셀
케빈 포
Original Assignee
마이크로소프트 테크놀로지 라이센싱, 엘엘씨
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 마이크로소프트 테크놀로지 라이센싱, 엘엘씨 filed Critical 마이크로소프트 테크놀로지 라이센싱, 엘엘씨
Publication of KR20160144482A publication Critical patent/KR20160144482A/ko
Application granted granted Critical
Publication of KR102380670B1 publication Critical patent/KR102380670B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
KR1020167031743A 2014-04-14 2015-04-06 메모리 제어기에서의 세분화된 대역폭 프로비저닝 Active KR102380670B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/252,673 2014-04-14
US14/252,673 US9563369B2 (en) 2014-04-14 2014-04-14 Fine-grained bandwidth provisioning in a memory controller
PCT/US2015/024414 WO2015160541A1 (en) 2014-04-14 2015-04-06 Fine-grained bandwidth provisioning in a memory controller

Publications (2)

Publication Number Publication Date
KR20160144482A KR20160144482A (ko) 2016-12-16
KR102380670B1 true KR102380670B1 (ko) 2022-03-29

Family

ID=52875816

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167031743A Active KR102380670B1 (ko) 2014-04-14 2015-04-06 메모리 제어기에서의 세분화된 대역폭 프로비저닝

Country Status (6)

Country Link
US (1) US9563369B2 (https=)
EP (1) EP3132355B1 (https=)
JP (1) JP6495327B2 (https=)
KR (1) KR102380670B1 (https=)
CN (1) CN106233269B (https=)
WO (1) WO2015160541A1 (https=)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101699377B1 (ko) * 2014-07-02 2017-01-26 삼성전자주식회사 불휘발성 메모리 및 메모리 컨트롤러를 포함하는 스토리지 장치 및 스토리지 장치의 동작 방법
EP3251021B1 (en) * 2015-01-30 2023-07-19 Hewlett Packard Enterprise Development LP Memory network to prioritize processing of a memory access request
US10158712B2 (en) * 2015-06-04 2018-12-18 Advanced Micro Devices, Inc. Source-side resource request network admission control
US20210182190A1 (en) * 2016-07-22 2021-06-17 Pure Storage, Inc. Intelligent die aware storage device scheduler
US10298511B2 (en) 2016-08-24 2019-05-21 Apple Inc. Communication queue management system
US10613612B2 (en) * 2017-03-16 2020-04-07 Qualcomm Incorporated Power reduction via memory efficiency compensation
US10732895B2 (en) * 2017-03-22 2020-08-04 Burlywood, Inc. Drive-level internal quality of service
US10795836B2 (en) * 2017-04-17 2020-10-06 Microsoft Technology Licensing, Llc Data processing performance enhancement for neural networks using a virtualized data iterator
US10437482B2 (en) * 2017-07-25 2019-10-08 Samsung Electronics Co., Ltd. Coordinated near-far memory controller for process-in-HBM
US10481944B2 (en) * 2017-08-09 2019-11-19 Xilinx, Inc. Adaptive quality of service control circuit
US10360832B2 (en) 2017-08-14 2019-07-23 Microsoft Technology Licensing, Llc Post-rendering image transformation using parallel image transformation pipelines
US10678690B2 (en) 2017-08-29 2020-06-09 Qualcomm Incorporated Providing fine-grained quality of service (QoS) control using interpolation for partitioned resources in processor-based systems
US10318301B2 (en) 2017-08-31 2019-06-11 Micron Technology, Inc. Managed multiple die memory QoS
US10372609B2 (en) * 2017-09-14 2019-08-06 Intel Corporation Fast cache warm-up
KR102417977B1 (ko) * 2017-10-19 2022-07-07 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
US10700954B2 (en) * 2017-12-20 2020-06-30 Advanced Micro Devices, Inc. Scheduling memory bandwidth based on quality of service floorbackground
US10296230B1 (en) * 2017-12-22 2019-05-21 Advanced Micro Devices, Inc. Scheduling memory requests with non-uniform latencies
US10275352B1 (en) * 2017-12-28 2019-04-30 Advanced Micro Devices, Inc. Supporting responses for memory types with non-uniform latencies on same channel
US11144457B2 (en) * 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures
US10705985B1 (en) * 2018-03-12 2020-07-07 Amazon Technologies, Inc. Integrated circuit with rate limiting
US11099778B2 (en) 2018-08-08 2021-08-24 Micron Technology, Inc. Controller command scheduling in a memory system to increase command bus utilization
CN109062514B (zh) * 2018-08-16 2021-08-31 郑州云海信息技术有限公司 一种基于命名空间的带宽控制方法、装置和存储介质
US10838884B1 (en) 2018-09-12 2020-11-17 Apple Inc. Memory access quality-of-service reallocation
US10635355B1 (en) * 2018-11-13 2020-04-28 Western Digital Technologies, Inc. Bandwidth limiting in solid state drives
US10860254B2 (en) * 2019-04-17 2020-12-08 Vmware, Inc. Throttling resynchronization operations in a data store cluster based on I/O bandwidth limits
US12547562B2 (en) 2020-03-06 2026-02-10 Infineon Technologies Ag Distribution of interconnect bandwidth among master agents
US12223174B2 (en) 2020-10-26 2025-02-11 Google Llc Modulating credit allocations in memory subsystems
US20220357879A1 (en) * 2021-05-06 2022-11-10 Apple Inc. Memory Bank Hotspotting
US20250077470A1 (en) * 2021-12-30 2025-03-06 Lx Semicon Co., Ltd. Memory control system and display device including memory control function
US12498969B2 (en) * 2022-04-21 2025-12-16 Microsoft Technology Licensing, Llc. Distributed, decentralized traffic control for worker processes in limited-coordination environments
JP7695292B2 (ja) * 2023-05-01 2025-06-18 キヤノン株式会社 メモリコントローラ、メモリコントローラの制御方法及びプログラム
US12457160B2 (en) 2023-10-18 2025-10-28 SanDisk Technologies, Inc. Bandwidth averaging in a stochastic system
CN118900251B (zh) * 2024-07-17 2026-03-31 无锡众星微系统技术有限公司 基于预占信用动态流控的发包优化方法、装置、设备及存储介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2778258A1 (fr) 1998-04-29 1999-11-05 Texas Instruments France Controleur d'acces de trafic dans une memoire, systeme de calcul comprenant ce controleur d'acces et procede de fonctionnement d'un tel controleur d'acces
US6961834B2 (en) 2001-10-12 2005-11-01 Sonics, Inc. Method and apparatus for scheduling of requests to dynamic random access memory device
US6804738B2 (en) * 2001-10-12 2004-10-12 Sonics, Inc. Method and apparatus for scheduling a resource to meet quality-of-service restrictions
US7363427B2 (en) * 2004-01-12 2008-04-22 Hewlett-Packard Development Company, L.P. Memory controller connection to RAM using buffer interface
US7461214B2 (en) 2005-11-15 2008-12-02 Agere Systems Inc. Method and system for accessing a single port memory
CN101046784A (zh) * 2006-07-18 2007-10-03 威盛电子股份有限公司 存储器数据存取系统与方法以及存储器控制器
US7577780B2 (en) 2007-02-28 2009-08-18 National Chiao Tung University Fine-grained bandwidth control arbiter and the method thereof
US8484411B1 (en) 2007-12-31 2013-07-09 Synopsys Inc. System and method for improving access efficiency to a dynamic random access memory
US8180975B2 (en) 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
CN101876944B (zh) 2009-11-26 2012-02-15 威盛电子股份有限公司 动态随机存取存储器控制器和控制方法
US8898674B2 (en) 2009-12-23 2014-11-25 International Business Machines Corporation Memory databus utilization management system and computer program product
RU2556443C2 (ru) 2010-09-16 2015-07-10 Эппл Инк. Многопортовый контроллер запоминающего устройства с портами, ассоциированными с классами трафика
US8314807B2 (en) 2010-09-16 2012-11-20 Apple Inc. Memory controller with QoS-aware scheduling
JP2013196321A (ja) 2012-03-19 2013-09-30 Pfu Ltd 電子回路及び調停方法

Also Published As

Publication number Publication date
EP3132355A1 (en) 2017-02-22
JP2017511545A (ja) 2017-04-20
EP3132355B1 (en) 2019-09-04
JP6495327B2 (ja) 2019-04-03
WO2015160541A1 (en) 2015-10-22
US9563369B2 (en) 2017-02-07
CN106233269B (zh) 2019-12-10
US20150293709A1 (en) 2015-10-15
CN106233269A (zh) 2016-12-14
KR20160144482A (ko) 2016-12-16

Similar Documents

Publication Publication Date Title
KR102380670B1 (ko) 메모리 제어기에서의 세분화된 대역폭 프로비저닝
US20200089537A1 (en) Apparatus and method for bandwidth allocation and quality of service management in a storage device shared by multiple tenants
US9639280B2 (en) Ordering memory commands in a computer system
EP2616945B1 (en) Allocation of memory buffers in computing system with multiple memory channels
KR20210021302A (ko) 메모리 제어기에서의 리프레시 방식
KR102402630B1 (ko) 캐시 제어 인지 메모리 컨트롤러
CN104461735B (zh) 一种虚拟化场景下分配cpu资源的方法和装置
US12242376B2 (en) Paging in thin-provisioned disaggregated memory
CN108710583A (zh) Ssd写缓存区的管理方法、装置、计算机设备及介质
US9436625B2 (en) Approach for allocating virtual bank managers within a dynamic random access memory (DRAM) controller to physical banks within a DRAM
US11385928B2 (en) System and method for priority orchestration and scheduling of different background operations
US10216660B1 (en) Method and system for input/output (IO) scheduling in a storage system
KR20240162226A (ko) 입출력 요청 스케줄링 방법 및 스토리지 장치
US10942875B2 (en) System and method for regulating host IOs and internal background operations in a storage system
US8966133B2 (en) Determining a mapping mode for a DMA data transfer
CN104750547A (zh) 虚拟机的输入输出io请求处理方法及装置
Peng et al. Weight‐based strategy for an I/O‐intensive application at a cloud data center
CN105204775A (zh) 电子装置以及数据写入方法
KR102955920B1 (ko) 스토리지 장치 및 이의 동작 방법

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20161114

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20200306

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20210608

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20211227

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20220325

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20220325

End annual number: 3

Start annual number: 1

PG1601 Publication of registration