CN106233269B - 在存储器控制器中的精细粒度带宽供应 - Google Patents

在存储器控制器中的精细粒度带宽供应 Download PDF

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Publication number
CN106233269B
CN106233269B CN201580019963.9A CN201580019963A CN106233269B CN 106233269 B CN106233269 B CN 106233269B CN 201580019963 A CN201580019963 A CN 201580019963A CN 106233269 B CN106233269 B CN 106233269B
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memory
dram
host
bandwidth
request
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Chinese (zh)
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CN106233269A (zh
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N·T·考齐
S·卡里
J·安德鲁斯
J·塞尔
K·波
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Microsoft Technology Licensing LLC
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Microsoft Technology Licensing LLC
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629Configuration or reconfiguration of storage systems
    • G06F3/0631Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0674Disk device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
CN201580019963.9A 2014-04-14 2015-04-06 在存储器控制器中的精细粒度带宽供应 Active CN106233269B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/252,673 2014-04-14
US14/252,673 US9563369B2 (en) 2014-04-14 2014-04-14 Fine-grained bandwidth provisioning in a memory controller
PCT/US2015/024414 WO2015160541A1 (en) 2014-04-14 2015-04-06 Fine-grained bandwidth provisioning in a memory controller

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CN106233269A CN106233269A (zh) 2016-12-14
CN106233269B true CN106233269B (zh) 2019-12-10

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US (1) US9563369B2 (https=)
EP (1) EP3132355B1 (https=)
JP (1) JP6495327B2 (https=)
KR (1) KR102380670B1 (https=)
CN (1) CN106233269B (https=)
WO (1) WO2015160541A1 (https=)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101699377B1 (ko) * 2014-07-02 2017-01-26 삼성전자주식회사 불휘발성 메모리 및 메모리 컨트롤러를 포함하는 스토리지 장치 및 스토리지 장치의 동작 방법
EP3251021B1 (en) * 2015-01-30 2023-07-19 Hewlett Packard Enterprise Development LP Memory network to prioritize processing of a memory access request
US10158712B2 (en) * 2015-06-04 2018-12-18 Advanced Micro Devices, Inc. Source-side resource request network admission control
US20210182190A1 (en) * 2016-07-22 2021-06-17 Pure Storage, Inc. Intelligent die aware storage device scheduler
US10298511B2 (en) 2016-08-24 2019-05-21 Apple Inc. Communication queue management system
US10613612B2 (en) * 2017-03-16 2020-04-07 Qualcomm Incorporated Power reduction via memory efficiency compensation
US10732895B2 (en) * 2017-03-22 2020-08-04 Burlywood, Inc. Drive-level internal quality of service
US10795836B2 (en) * 2017-04-17 2020-10-06 Microsoft Technology Licensing, Llc Data processing performance enhancement for neural networks using a virtualized data iterator
US10437482B2 (en) * 2017-07-25 2019-10-08 Samsung Electronics Co., Ltd. Coordinated near-far memory controller for process-in-HBM
US10481944B2 (en) * 2017-08-09 2019-11-19 Xilinx, Inc. Adaptive quality of service control circuit
US10360832B2 (en) 2017-08-14 2019-07-23 Microsoft Technology Licensing, Llc Post-rendering image transformation using parallel image transformation pipelines
US10678690B2 (en) 2017-08-29 2020-06-09 Qualcomm Incorporated Providing fine-grained quality of service (QoS) control using interpolation for partitioned resources in processor-based systems
US10318301B2 (en) 2017-08-31 2019-06-11 Micron Technology, Inc. Managed multiple die memory QoS
US10372609B2 (en) * 2017-09-14 2019-08-06 Intel Corporation Fast cache warm-up
KR102417977B1 (ko) * 2017-10-19 2022-07-07 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
US10700954B2 (en) * 2017-12-20 2020-06-30 Advanced Micro Devices, Inc. Scheduling memory bandwidth based on quality of service floorbackground
US10296230B1 (en) * 2017-12-22 2019-05-21 Advanced Micro Devices, Inc. Scheduling memory requests with non-uniform latencies
US10275352B1 (en) * 2017-12-28 2019-04-30 Advanced Micro Devices, Inc. Supporting responses for memory types with non-uniform latencies on same channel
US11144457B2 (en) * 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures
US10705985B1 (en) * 2018-03-12 2020-07-07 Amazon Technologies, Inc. Integrated circuit with rate limiting
US11099778B2 (en) 2018-08-08 2021-08-24 Micron Technology, Inc. Controller command scheduling in a memory system to increase command bus utilization
CN109062514B (zh) * 2018-08-16 2021-08-31 郑州云海信息技术有限公司 一种基于命名空间的带宽控制方法、装置和存储介质
US10838884B1 (en) 2018-09-12 2020-11-17 Apple Inc. Memory access quality-of-service reallocation
US10635355B1 (en) * 2018-11-13 2020-04-28 Western Digital Technologies, Inc. Bandwidth limiting in solid state drives
US10860254B2 (en) * 2019-04-17 2020-12-08 Vmware, Inc. Throttling resynchronization operations in a data store cluster based on I/O bandwidth limits
US12547562B2 (en) 2020-03-06 2026-02-10 Infineon Technologies Ag Distribution of interconnect bandwidth among master agents
US12223174B2 (en) 2020-10-26 2025-02-11 Google Llc Modulating credit allocations in memory subsystems
US20220357879A1 (en) * 2021-05-06 2022-11-10 Apple Inc. Memory Bank Hotspotting
US20250077470A1 (en) * 2021-12-30 2025-03-06 Lx Semicon Co., Ltd. Memory control system and display device including memory control function
US12498969B2 (en) * 2022-04-21 2025-12-16 Microsoft Technology Licensing, Llc. Distributed, decentralized traffic control for worker processes in limited-coordination environments
JP7695292B2 (ja) * 2023-05-01 2025-06-18 キヤノン株式会社 メモリコントローラ、メモリコントローラの制御方法及びプログラム
US12457160B2 (en) 2023-10-18 2025-10-28 SanDisk Technologies, Inc. Bandwidth averaging in a stochastic system
CN118900251B (zh) * 2024-07-17 2026-03-31 无锡众星微系统技术有限公司 基于预占信用动态流控的发包优化方法、装置、设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070113023A1 (en) * 2005-11-15 2007-05-17 Agere Systems Inc. Method and system for accessing a single port memory
CN101046784A (zh) * 2006-07-18 2007-10-03 威盛电子股份有限公司 存储器数据存取系统与方法以及存储器控制器
US20080104293A1 (en) * 2004-01-12 2008-05-01 Hewlett-Packard Development Company, L.P. Memory controller connection to RAM using buffer interface
US20110154352A1 (en) * 2009-12-23 2011-06-23 International Business Machines Corporation Memory management system, method and computer program product

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2778258A1 (fr) 1998-04-29 1999-11-05 Texas Instruments France Controleur d'acces de trafic dans une memoire, systeme de calcul comprenant ce controleur d'acces et procede de fonctionnement d'un tel controleur d'acces
US6961834B2 (en) 2001-10-12 2005-11-01 Sonics, Inc. Method and apparatus for scheduling of requests to dynamic random access memory device
US6804738B2 (en) * 2001-10-12 2004-10-12 Sonics, Inc. Method and apparatus for scheduling a resource to meet quality-of-service restrictions
US7577780B2 (en) 2007-02-28 2009-08-18 National Chiao Tung University Fine-grained bandwidth control arbiter and the method thereof
US8484411B1 (en) 2007-12-31 2013-07-09 Synopsys Inc. System and method for improving access efficiency to a dynamic random access memory
US8180975B2 (en) 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
CN101876944B (zh) 2009-11-26 2012-02-15 威盛电子股份有限公司 动态随机存取存储器控制器和控制方法
RU2556443C2 (ru) 2010-09-16 2015-07-10 Эппл Инк. Многопортовый контроллер запоминающего устройства с портами, ассоциированными с классами трафика
US8314807B2 (en) 2010-09-16 2012-11-20 Apple Inc. Memory controller with QoS-aware scheduling
JP2013196321A (ja) 2012-03-19 2013-09-30 Pfu Ltd 電子回路及び調停方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080104293A1 (en) * 2004-01-12 2008-05-01 Hewlett-Packard Development Company, L.P. Memory controller connection to RAM using buffer interface
US20070113023A1 (en) * 2005-11-15 2007-05-17 Agere Systems Inc. Method and system for accessing a single port memory
CN101046784A (zh) * 2006-07-18 2007-10-03 威盛电子股份有限公司 存储器数据存取系统与方法以及存储器控制器
US20110154352A1 (en) * 2009-12-23 2011-06-23 International Business Machines Corporation Memory management system, method and computer program product

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Publication number Publication date
EP3132355A1 (en) 2017-02-22
JP2017511545A (ja) 2017-04-20
EP3132355B1 (en) 2019-09-04
JP6495327B2 (ja) 2019-04-03
WO2015160541A1 (en) 2015-10-22
US9563369B2 (en) 2017-02-07
US20150293709A1 (en) 2015-10-15
CN106233269A (zh) 2016-12-14
KR20160144482A (ko) 2016-12-16
KR102380670B1 (ko) 2022-03-29

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