KR102373536B1 - Circle display and driving method thereof - Google Patents

Abstract

The non-rectangular display includes a plurality of first signal lines formed in a first direction, a plurality of DC voltage lines formed in the first direction, and a plurality of second signal lines formed in the first direction do. A first DC voltage line of the plurality of DC voltage lines is positioned between a first line of the plurality of first signal lines and a second line of the plurality of second signal lines, and a third of the plurality of first signal lines is disposed. A second DC voltage line of the plurality of DC voltage lines is positioned between a line and a fourth line of the plurality of second signal lines, and the first line and the third line are adjacent to each other, or the second line and the fourth line it is adjacent

Description

Non-Rectangular Display {CIRCLE DISPLAY AND DRIVING METHOD THEREOF}

Embodiments relate to non-rectangular displays.

A plurality of pixels, a plurality of gate lines, and a plurality of data lines are formed on a display panel constituting the display. Each of the plurality of pixels is connected to a corresponding gate line and a data line. A plurality of scan signals are supplied through a plurality of gate lines, and a plurality of data signals are supplied through a plurality of data lines.

However, a non-rectangular, for example, a circular display having a circular display unit has limitations depending on the shape of the display unit. In a circular display, the width of the bezel area around the display unit is limited. The wider the bezel on the display, the less likely the display area will be, which will not meet the needs of the user.

As the bezel area is made narrower, an area in which a driver IC generating a plurality of scan signals and a plurality of data signals can be located is limited. For example, the driver IC may be positioned in a predetermined area around the entire circumference of the circular display panel. The driver IC includes a gate driving circuit and a data driving circuit.

Then, the gate line and the data line are formed in parallel, and coupling by the parasitic capacitor occurs between the two lines. Then, when the gate signal is applied to the gate line, the data signal of the data line is changed due to coupling.

An object of the present invention is to provide a non-rectangular display capable of blocking coupling by a parasitic capacitor between a gate line and a data line.

A non-rectangular display according to an embodiment includes a plurality of first signal lines formed in a first direction, a plurality of DC voltage lines formed in the first direction, and a plurality of second signal lines formed in the first direction. Includes signal lines. A first DC voltage line of the plurality of DC voltage lines is positioned between a first line of the plurality of first signal lines and a second line of the plurality of second signal lines, and a third of the plurality of first signal lines is disposed. A second DC voltage line of the plurality of DC voltage lines is positioned between a line and a fourth line of the plurality of second signal lines, and the first line and the third line are adjacent to each other, or the second line and the fourth line it is adjacent

A non-rectangular display according to an embodiment includes a plurality of semiconductors, a gate insulating layer formed on the plurality of semiconductors, a first electrode formed on the gate insulating layer, and a first interlayer insulating layer formed on the first electrode , a second electrode formed on the first interlayer insulating layer, a second interlayer insulating layer formed on the second electrode, and a first signal line, a DC voltage line, and a first signal line formed on the second interlayer insulating layer Includes 2 signal lines.

In the non-rectangular display according to the embodiment, a first signal line formed in a first direction, a second signal line formed in the first direction, and the first direction between the first signal line and the second signal line and a third signal line connected to the second signal line through a contact hole and formed in a second direction crossing the first direction.

A non-rectangular display capable of blocking coupling by a parasitic capacitor between a gate line and a data line is provided.

1 is a diagram illustrating a part of a configuration of a display according to an embodiment.
FIG. 2 is a view showing another part of the configuration of a display according to an embodiment, not shown in FIG. 1 .
3 is a diagram illustrating a plurality of contact points to which a plurality of third signal lines and a plurality of second signal lines are connected.
4 is a diagram schematically illustrating a portion of a circular display panel according to an exemplary embodiment.
FIG. 5 is a pixel circuit diagram of one pixel among the plurality of pixels shown in FIG. 4 .
6 is a diagram schematically illustrating a portion of a circular display panel according to another exemplary embodiment.
FIG. 7 is a circuit diagram of one of the plurality of pixels shown in FIG. 6 .
8 is a plan view illustrating a layout of four pixels illustrated in FIG. 6 .
9 is a view showing a cross-section taken along line A-A' in the plan view of FIG. 8 .

Hereinafter, with reference to the accompanying drawings, the embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. However, the present invention may be implemented in several different forms and is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout the specification, when a part is "connected" with another part, this includes not only the case of being "directly connected" but also the case of being "electrically connected" with another element interposed therebetween. . Also, when a part "includes" a certain component, it means that other components may be further included, rather than excluding other components, unless otherwise stated.

1 is a diagram illustrating a part of a configuration of a display according to an embodiment.

In FIG. 1 , a plurality of first signal lines D1-D20 , a plurality of second signal lines G1-G20 , and a plurality of DC voltage lines DCL1-DCL20 are formed on the non-rectangular display panel 20 . . The plurality of DC voltage lines DCL1 - DCL20 are connected to one DC voltage line DCL, so that the same DC voltage may be supplied.

Each of the plurality of first signal lines D1 - D20 is formed in the y-axis direction, arranged in the x-axis direction, and connected to the driver IC 10 . Each of the plurality of second signal lines G1 - G20 is also formed in the y-axis direction, arranged in the x-axis direction, and connected to the driver IC 10 .

A plurality of DC voltage lines DCL1-DCL20 are formed between the plurality of first signal lines D1-D20 and the plurality of second signal lines G1-G20. Each of the plurality of DC voltage lines DCL1 - DCL20 is formed in the y-axis direction between the corresponding first and second signal lines and is arranged in the x-axis direction. For example, the DC voltage line DCL1 is positioned between the first signal line D1 and the second signal line G1, and the DC voltage line DCL2 is located between the first signal line D2 and the second signal line G1. G2) is located between

Looking at the arrangement order along the X-axis direction, the second signal line, the DC voltage line, the first signal line, the first signal line, the DC voltage line, and the second signal line are arranged in the order. For example, they are arranged in the order of G1, DCL1, D1, D2, DCL2, G2. or a first signal line, a DC voltage line, a second signal line, a second signal line, a DC voltage line, and a first signal line. For example, it is arranged in the order of D4, DCL4, G5, G6, DCL6, D6.

Such an arrangement is hereinafter referred to as a flip arrangement. According to the flip arrangement, the first signal line positioned between two adjacent second signal lines (eg, G2 and G3) among the plurality of second signal lines G1 - G20 does not exist. Similarly, a second signal line positioned between two adjacent first signal lines (eg, D3 and D4 ) among the plurality of first signal lines D1 - D20 does not exist.

For example, the plurality of first signal lines D1-D20 may be a plurality of data lines to which a plurality of data signals are transmitted, and the plurality of second signal lines G1 to G20 may be a plurality of data lines to which a plurality of gate signals are transmitted. may be a gate line of Then, a corresponding one of the plurality of DC voltage lines DCL1-DCL20 is positioned between the data line and the gate line.

Coupling between the data signal and the gate signal may occur due to a parasitic capacitor generated between the data line and the gate line. However, according to an embodiment, since a DC voltage line is connected between the data line and the gate line, coupling through the parasitic capacitor may be blocked.

Specifically, when there is no DC voltage line, the gate signal may change abruptly while the data signal is supplied through the data line, and the data signal may change due to coupling between the two lines by a parasitic capacitor. However, since there is a DC voltage line between the two lines, a parasitic capacitor is not formed between the gate line and the data line. Then, there is no change in the data signal due to coupling.

In FIG. 1 , a circular display panel is illustrated as an example of the non-rectangular display panel 20 . However, the invention is not limited thereto. The entire display panel 20 may be formed in a circular shape, a portion thereof may be circular, or may have a polygonal structure instead of a circular shape. Due to a shape different from the conventional rectangular display, the embodiment may be applied to a non-rectangular display panel in which a plurality of gate lines are formed in the same direction as a plurality of data lines.

The display unit 30 of the circular display panel 20 is driven by a signal supplied from a corresponding one of the plurality of first signal lines D1-D20 and a corresponding one of the plurality of second signal lines G1-G20 A plurality of pixels may be formed.

For example, a pixel row indicated by a plurality of dashed-line boxes is shown in the center of FIG. 1 . Although a pixel row is shown, this is an example of indicating a region in which a pixel can be formed, and the embodiment is not limited thereto. That is, a plurality of pixels may be formed in the display unit 30 in various shapes.

FIG. 2 is a view showing another part of the configuration of a display according to an embodiment, not shown in FIG. 1 .

In FIG. 2 , a plurality of third signal lines S1 - S20 are formed on the display panel 20 . A first layer in which a plurality of first and second signal lines D1-D20 and G1-G20 and a plurality of DC voltage lines shown in FIG. 1 are formed above and a plurality of third signal lines shown in FIG. 2 The second layers on which (S1-Sn) are formed are different from each other. A first layer may be formed over the second layer, and an insulating layer may be positioned between the first layer and the second layer. The reverse may also be possible.

Although only the plurality of third signal lines S1-S20 are illustrated in the second layer illustrated in FIG. 2 , the present invention is not limited thereto. For the description of the embodiment, only the plurality of second signal lines G1-G20 and the plurality of lines S1-S20 electrically connected through the plurality of contact points are illustrated, but the present invention is not limited thereto. A plurality of other signal lines may be formed in the second layer.

3 is a diagram illustrating a plurality of contact points to which a plurality of third signal lines and a plurality of second signal lines are connected.

3 illustrates a plurality of lines S1-S20 connected to the plurality of second signal lines G1-G20.

The layer on which the plurality of lines G1-G20 is formed and the layer on which the plurality of lines S1-S20 are formed may be different from each other, and the two lines G1-G20 corresponding to the plurality of contact points P1-P20 one of them and one of P1-P20) may be connected to each other. The plurality of contact points P1 - P20 may be formed of a contact hole (not shown) and a contact electrode (not shown) formed in the contact hole, and implementation means are not limited thereto.

The gate driving circuit 100 is connected to the plurality of gate lines G1-G20, and generates and outputs a plurality of gate signals to the plurality of gate lines G1-G20.

The plurality of gate lines G1-G20 is connected to the plurality of contact points P10, P9, P8, ..., P1 to the plurality of scan lines S10, S9, S8, ..., S1, S11, S12, ..., S18, S19, S20. , P11, P12, …, P18, P19, P20).

For example, the gate line G1 is connected to the scan line S10 through the contact point P10, the gate line G2 is connected to the scan line S9 through the contact point P9, and the gate line G3 ) is connected to the scan line S8 through the contact point P8, and the gate line G10 is connected to the scan line S1 through the contact point P1. The gate line G20 is connected to the scan line S11 through the contact point P11, the gate line G19 is connected to the scan line S12 through the contact point P12, and the gate line G18 is connected to the contact point ( It is connected to the scan line S13 through P13 , and the gate line G11 is connected to the scan line S20 through a contact point P20 .

4 is a diagram schematically illustrating a portion of a circular display panel according to an exemplary embodiment.

FIG. 5 is a pixel circuit diagram of one pixel among the plurality of pixels shown in FIG. 4 .

The plurality of contact points P1 - P20 shown in FIG. 3 is directly applied to the embodiment shown in FIG. 4 . 4, the second signal line G10 and the scan line S1 are connected at a contact point P1, and the second signal line G9 and the scan line S2 are connected at the contact point P2, The second signal line G11 and the scan line S20 are connected at the contact point P20 , and the second signal line G12 and the scan line S19 are connected at the contact point P19 .

5 , the pixel PX1 includes a driving transistor M1 , a switching transistor M2 , a capacitor C1 formed between a gate electrode and a source electrode of the driving transistor M1 , and an organic light emitting diode OLED. ) is included.

As shown in FIG. 4 , a plurality of pixels indicated by a rectangular box are formed in the display unit 30 . The plurality of first signal lines D1-D20, the plurality of DC voltage lines DCL1-DCL20, and the plurality of third signal lines S1-S20 connected to the plurality of pixels include a plurality of data lines and a plurality of ELVDDs. It may be a voltage line, and a plurality of scan lines. The plurality of second signal lines G1 - G20 may be a plurality of gate lines that transmit the plurality of scan signals output from the gate driving circuit 100 to the corresponding plurality of scan lines S1 - S20 .

A plurality of data signals transmitted through the plurality of data lines in synchronization with each of the plurality of scan signals transmitted through the plurality of scan lines are written in the plurality of pixels. In addition, the ELVDD voltage supplied through the plurality of ELVDD voltage lines is a voltage for driving the plurality of pixels.

For example, in the pixel PX1 that is one of the plurality of pixels, the scan line S1 is a gate electrode of the switching transistor M2 of the pixel PX1 . At the node N1, one electrode of the switching transistor M2 and the data line D9 are connected. Specifically, one electrode of the switching transistor M and the data line may be connected through a contact electrode formed in a contact hole (not shown). At the node N2 , the source electrode of the driving transistor M1 and the DC voltage line DCL9 are connected. Specifically, the source electrode of the driving transistor M1 and the DC voltage line DCL9 may be connected through a contact electrode formed in a contact hole (not shown). The source electrode of the driving transistor M1 and one electrode of the capacitor C1 may be connected to the DC voltage line DCL9 together.

The other electrode of the switching transistor M2 is connected to the gate electrode of the driving transistor M1 and the other electrode of the capacitor C1. The drain electrode of the driving transistor M is connected to the anode electrode of the organic light emitting diode OLED. A voltage VSS is supplied to the cathode electrode of the organic light emitting diode (OLED).

As such, a DC voltage line (eg, an ELVDD voltage supply line) is positioned between the gate line and the data line to prevent coupling between the gate line and the data line by the parasitic capacitor.

Although the pixel circuit of one pixel PX1 is illustrated in FIG. 5 , the plurality of pixels illustrated in FIG. 4 may be implemented with the same pixel circuit as the pixel circuit illustrated in FIG. 5 .

Although the flip arrangement according to the embodiment is applied to a non-rectangular display panel including a pixel including two transistors and one capacitor in FIG. 5 , the present invention is not limited thereto.

That is, the flip arrangement in which the gate line, the DC voltage line, and the data line are arranged is applicable to various pixel structures.

6 is a diagram schematically illustrating a portion of a circular display panel according to another exemplary embodiment.

FIG. 7 is a circuit diagram of one of the plurality of pixels shown in FIG. 6 .

The plurality of contact points P1 - P20 shown in FIG. 3 is directly applied to the other embodiment shown in FIG. 6 . 6, the second signal line G10 and the scan line S1 are connected at a contact point P1, and the second signal line G9 and the scan line S2 are connected at the contact point P2, The second signal line G8 and the scan line S3 are connected at the contact point P3. In FIG. 6, the scan line S0 is further illustrated. A second signal line not shown in FIG. 3 may be added and connected through a contact point (not shown). In this case, the added second signal line may be appropriately positioned along the flip arrangement.

7 , the pixel PX21 includes a driving transistor T1 , a switching transistor T2 , a compensation transistor T3 , and a capacitor formed between the gate electrode of the driving transistor T1 and the DC voltage line DCL9 . (C2), an initialization transistor T4, light emission control transistors T5 and T6, and an organic light emitting diode (OLED).

As shown in FIG. 6 , a plurality of pixels indicated by a rectangular box are formed in the display unit 40 . The plurality of first signal lines D8 - D12 , the plurality of DC voltage lines DC8 - DCL12 , and the plurality of third signal lines S0 - S3 connected to the plurality of pixels are a plurality of data lines and a plurality of ELVDDs. It may be a voltage line, and a plurality of scan lines. The plurality of second signal lines G8 - G10 may be a plurality of gate lines that transmit the plurality of scan signals output from the gate driving circuit 100 to the corresponding plurality of scan lines S1 - S3 .

Each of the plurality of scan lines S1 - S3 is formed over the corresponding main pixel row and is also formed over the next pixel row of the main pixel row. For example, the scan line S1 is formed over the current pixel row including the plurality of pixels PX11 - PX14 as well as the next pixel row including the plurality of pixels PX21 - PX24 .

As shown in FIG. 6 , the display unit 40 includes a plurality of initialization voltage lines (eg, a plurality of first signal lines, a plurality of DC voltage lines, and a plurality of initialization voltage lines to which an initialization voltage Vint is supplied together with a plurality of third signal lines). For example, VIN1-VIN3) and a plurality of emission control lines (eg, E1-E3) to which emission control signals are supplied are further formed. In addition, corresponding two scan lines among the plurality of scan lines are positioned in the plurality of pixels. Two scan lines in each pixel may be gate electrodes of transistors (eg, T2, T3, and T4).

The initialization voltage Vint may be supplied to the gate electrode of the driving transistor T1 of each of the plurality of pixels in synchronization with a plurality of scan signals supplied through a plurality of scan lines positioned in a previous pixel row. In addition, a plurality of data signals transmitted through a plurality of data lines in synchronization with a plurality of scan signals transmitted through a plurality of scan lines positioned in the present pixel row are written into the plurality of pixels. In addition, the ELVDD voltage supplied through the plurality of ELVDD voltage lines is a voltage for driving the plurality of pixels, and the emission of the organic light emitting diode (OLED) is controlled by the plurality of light emission control signals supplied through the plurality of emission control lines.

For example, in the pixel PX21 that is one of the plurality of pixels, the scan line S1 is a gate electrode of the initialization transistor T4 of the pixel PX21 , and the scan line S2 is the switching transistor T2 of the pixel PX21 . ) and the gate electrode of the compensation transistor T3.

At the node N3, one electrode of the switching transistor T2 and the data line D9 are connected. Specifically, one electrode of the switching transistor T2 and the data line may be connected through a contact electrode formed in a contact hole (see CH2 of FIG. 8 ). At the node N4 , the source electrode of the emission control transistor M5 and the DC voltage line DCL9 are connected. Specifically, the source electrode of the emission control transistor M5 and the DC voltage line DCL9 may be connected through the contact electrode formed in the contact hole (CH3 of FIG. 8 ). At the node N5 , one electrode of the initialization transistor T4 and the initialization voltage line VIN2 are connected. Specifically, one electrode of the initialization transistor T4 and the initialization voltage line VIN2 may be connected through a contact electrode formed in a contact hole (see CH41 and CH42 of FIG. 8 ).

The other electrode of the switching transistor T2 is connected to the source electrode of the driving transistor T1 and the drain electrode of the emission control transistor T5 . The compensation transistor T3 is connected between the gate electrode and the drain electrode of the driving transistor T1 . The other electrode of the initialization transistor T4 is connected to one electrode of the compensation transistor T3 , the gate electrode of the driving transistor T1 , and the other electrode of the capacitor C2 . The emission control transistor T6 is connected between the drain electrode of the driving transistor T1 and the anode electrode of the organic light emitting diode OLED. The gate electrode of the emission control transistors T5 and T6 is the emission control line E2. A voltage ELVSS is supplied to the cathode electrode of the organic light emitting diode (OLED).

8 is a plan view illustrating a layout of four pixels illustrated in FIG. 6 .

As shown in Fig. 8, D9, DCL9, and G9 and G10, DCL10, and D10 are arranged in a flip arrangement. Then, D9, DCL9, and G9 and G10, DCL10, and D10 are symmetrical with respect to the reference line RL1. The pixel PX21 and the pixel PX22 are also symmetrical with respect to the reference line RL1 .

Further, G10, DCL10, and D10 and D11, DCL11, and G11 are arranged in a flip arrangement. Then, with respect to the reference line RL2, G10, DCL10, and D10 and D11, DCL11, and G11 are symmetrical to each other. The pixel PX22 and the pixel PX23 are also symmetrical with respect to the reference line RL2 .

Further, D11, DCL11, and G11 and G12, DCL12, and D12 are arranged in a flip arrangement. Then, with respect to the reference line RL3, D11, DCL11, and G11 and G12, DCL12, and D12 are symmetrical to each other. The pixel PX23 and the pixel PX24 are also symmetrical with respect to the reference line RL3 .

Compared to the pixel PX21 , the pixel PX22 and the pixel PX24 are symmetrical, and the pixel PX23 has the same structure. For example, the pixel PX21 will be described in detail.

In the contact hole CH1, the second signal line G9 and the third signal line S2 are connected through a contact electrode. Each of the transistors T1-T6 of the pixel circuit shown in FIG. 7 is indicated by a dotted line box as shown in FIG. 8 .

A channel region, a source electrode, and a drain electrode are formed in the semiconductors 201 , 202 , 203 , and 204 . A channel region, a source electrode, and a drain electrode of the compensation transistor T3 and the emission control transistor T6 are formed in the semiconductor 201 . A channel region, a source electrode, and a drain electrode of the driving transistor T1 are formed in the semiconductor 202 . The semiconductor 201 is formed in an S-shape, but the present invention is not limited thereto.

A channel region, a source electrode, and a drain electrode of the switching transistor T2 and the emission control transistor T5 are formed in the semiconductor 203 . A channel region, a source electrode, and a drain electrode of the initialization transistor T4 are formed in the semiconductor 204 .

The scan line S1 is formed on the channel region of the initialization transistor T4 of the semiconductor 204 in a direction crossing the semiconductor 204 . The scan line S2 is also formed in a direction crossing the semiconductor 201 and the semiconductor 203 over the channel region of the switching transistor T2 of the semiconductor 203 and the channel region of the compensation transistor T3 of the semiconductor 201 . . The emission control line E2 also crosses the semiconductor 201 and the semiconductor 203 on the channel region of the emission control transistor T6 of the semiconductor 201 and the channel region of the emission control transistor T5 of the semiconductor 203 . is formed with

The gate electrode 301 of the driving transistor T1 and the other electrode (lower electrode) of the capacitor C2 are the electrodes 301 . One electrode (upper electrode) of the DC voltage line DCL9 and the capacitor C2 is connected to the contact electrode through the contact holes CH51 and CH52.

One electrode of the switching transistor T2 is connected to the first signal line D9 through the contact hole CH2. One electrode of the compensation transistor T3 is connected to the other electrode of the initialization transistor T4 through the contact hole CH6. The electrode 303 is connected to the other electrode 301 of the capacitor C2 through a contact hole CH7, and one electrode of the compensation transistor T3 and the other electrode of the initialization transistor T4 through the contact hole CH6. connected to the electrode. One electrode 302 of the capacitor C2 is connected to the DC voltage line DCL9 through the contact holes CH51 and CH52, and the voltage ELVDD is supplied to one electrode of the capacitor C2.

9 is a view showing a cross-section taken along line A-A' in the plan view of FIG. 8 .

As shown in FIG. 9 , the buffer layer 102 is formed on the substrate 101 . Semiconductors 201 , 202 , 203 are formed on the buffer layer 102 , and a gate insulating layer 103 is formed on the semiconductors 201 , 202 , 203 .

An electrode 301 is formed on the gate insulating layer 103 , and an interlayer insulating layer 104 is formed thereon. The plurality of third signal lines S1 - S20 may be formed on the same layer as the electrode 301 . For example, the third signal line S1 illustrated in FIG. 8 may be formed on the same layer as the electrode 301 and may be connected to the second signal line G9 through the contact hole CH1 . An electrode 302 is formed on the interlayer insulating layer 104 , and an interlayer insulating layer 105 is formed thereon.

A first signal line D9 , a DC voltage line DCL9 , and a second signal line G9 are formed on the interlayer insulating layer 105 , and a contact hole CH51 is formed in the middle of the interlayer insulating layer 105 . The DC voltage line DCL9 and the electrode 302 are connected.

Up to now, embodiments of a non-rectangular display panel including a first signal line, a DC voltage line, and a second signal line arranged according to a flip arrangement have been described. Distortion of the signal transmitted to each of the first and second signal lines is reduced by locating the DC voltage line between the first and second signal lines to prevent a parasitic capacitor from occurring between the first and second signal lines. can be blocked

In the embodiment so far, it has been described that the DC voltage line formed between the first signal line and the second signal line supplies the ELVDD voltage, but the present invention is not limited thereto. It may be another voltage required for driving the pixel.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. is within the scope of the right.

D1-D20: a plurality of first signal lines
G1-G20: a plurality of second signal lines
DCL1-DCL20: Multiple DC voltage lines
10: driver IC
20: display panel
30, 40: display
P1-P20: multiple contact points
PX1, PX11-PX14, PX21-PX24: Pixel
M1, M2, T1-T6: Transistors
C1, C2: capacitors

Claims (20)

a plurality of first signal lines formed in a first direction;
a plurality of DC voltage lines formed in the first direction;
a plurality of second signal lines formed in the first direction; and
a plurality of pixels in which a plurality of signals transmitted through the plurality of first signal lines in synchronization with each of the plurality of signals transmitted through the plurality of second signal lines are written;
A first DC voltage line of the plurality of DC voltage lines is positioned between a first line of the plurality of first signal lines and a second line of the plurality of second signal lines, and a third of the plurality of first signal lines is disposed. A second DC voltage line among the plurality of DC voltage lines is positioned between a line and a fourth line among the plurality of second signal lines, and a fifth line among the plurality of first signal lines and the plurality of second signal lines A third DC voltage line among the plurality of DC voltage lines is positioned between the sixth line,
In a second direction intersecting the first direction, the second line and the fourth line are adjacent and the third line and the fifth line are adjacent;
The plurality of DC voltage lines are not located between the second line and the fourth line, and the plurality of DC voltage lines are not located between the third line and the fifth line,
The separation distance in the second direction between the second line and the fourth line is shorter than the separation distance in the second direction between the third line and the fifth line,
The plurality of first signal lines, the plurality of DC voltage lines, and the plurality of second signal lines are located on the same layer. According to claim 1,
The non-rectangular display is arranged in the order of the fourth line, the second DC voltage line, the third line, the fifth line, the third DC voltage line, and the sixth line. 3. The method of claim 2,
the third line and the fifth line, the second line and the fourth line, the fourth line and the sixth line, the first DC voltage line and the second DC voltage line, and the second DC voltage line and the third line A non-rectangular display in which at least one pair of DC voltage lines is in a symmetrical relationship with respect to a reference line. According to claim 1,
The non-rectangular display is arranged in the order of the first line, the first DC voltage line, the second line, the fourth line, the second DC voltage line, and the third line. delete delete According to claim 1,
and a plurality of third signal lines connected to the plurality of second signal lines through a plurality of contact points and formed in the second direction. 8. The method of claim 7,
The plurality of pixels is a non-rectangular display in which a plurality of data signals transmitted through the plurality of first signal lines are written in synchronization with each of the plurality of scan signals transmitted through the plurality of third signal lines. 9. The method of claim 8,
The plurality of pixels,
a plurality of switching transistors including one electrode connected to the plurality of first signal lines and the plurality of third signal lines as gate electrodes; and
A plurality of driving transistors including a gate electrode connected to the other electrodes of the plurality of switching transistors, one electrode supplied with a voltage supplied through the plurality of DC voltage lines, and the other electrode connected to the organic light emitting diode. A non-rectangular display comprising a. 9. The method of claim 8,
The plurality of pixels,
A non-rectangular display in which an initialization voltage is supplied in synchronization with a plurality of scan signals transmitted through a plurality of third signal lines corresponding to the immediately preceding pixel row among the plurality of third signal lines. 11. The method of claim 10,
and a plurality of initialization voltage lines configured to supply the initialization voltage and formed in the second direction. 11. The method of claim 10,
The plurality of pixels,
a plurality of switching transistors including one electrode connected to the plurality of first signal lines and the plurality of third signal lines as gate electrodes;
A plurality of driving transistors including one electrode connected to the other electrode of the plurality of switching transistors, and the other electrode connected to the organic light emitting diode, and
and a plurality of compensating transistors connected between the gate electrodes and the other electrodes of the plurality of driving transistors and including the plurality of third signal lines as gate electrodes. 13. The method of claim 12,
The plurality of pixels,
The non-rectangular display further comprising: a plurality of initialization transistors including one electrode connected to the gate electrodes of the plurality of driving transistors and a plurality of third signal lines corresponding to the immediately preceding pixel row as gate electrodes. 11. The method of claim 10,
A non-rectangular display further comprising a plurality of light emission control lines transmitting a plurality of light emission control signals. a plurality of semiconductors,
a gate insulating layer over the plurality of semiconductors;
a first electrode over the gate insulating layer;
a first interlayer insulating layer over the first electrode;
a second electrode on the first interlayer insulating layer;
a second interlayer insulating layer over the second electrode;
a plurality of first signal lines, a plurality of DC voltage lines, and a plurality of second signal lines overlying the second interlayer insulating layer, and
A pixel in which a data signal supplied through the first signal line is written in synchronization with a scan signal supplied through the second signal line, and a driving voltage is supplied through the DC voltage line
including,
the DC voltage line is positioned between the first signal line and the second signal line;
The plurality of DC voltage lines are not positioned between two adjacent first signal lines among the plurality of first signal lines,
A non-rectangular display, wherein a distance between two adjacent first signal lines of the plurality of first signal lines is greater than a distance between adjacent two second signal lines of the plurality of second signal lines. 16. The method of claim 15,
The DC voltage line is connected to the second electrode through a contact hole. delete 16. The method of claim 15,
and a third signal line formed on the same layer as the first electrode and connected to the second signal line through a contact hole. a plurality of first signal lines formed in a first direction;
a plurality of second signal lines formed in the first direction;
a plurality of DC voltage lines formed in the first direction;
a plurality of third signal lines connected to the plurality of second signal lines through a plurality of contact holes and formed in a second direction crossing the first direction; and
A pixel in which a data signal supplied through the first signal line is written in synchronization with a scan signal supplied through the second signal line, and a driving voltage is supplied through the DC voltage line
including,
The plurality of first signal lines or the plurality of second signal lines are located between two adjacent DC voltage lines among the plurality of DC voltage lines;
the plurality of first signal lines, the plurality of DC voltage lines, and the plurality of second signal lines are located on the same layer;
a distance between two adjacent first signal lines of the plurality of first signal lines is greater than a distance between two adjacent second signal lines of the plurality of second signal lines;
non-rectangular display. delete

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