KR102349479B1 - Pixel circuit and method for driving the same - Google Patents

Abstract

An object of the present invention is to realize image quality improvement by suppressing changes in luminance, flickering, and the like while achieving high-definition by suppressing the number of elements or wirings per pixel. The pixel circuit is arranged in each of the pixels arranged in a matrix shape, and is connected in series between a data storage capacitor for storing a voltage for controlling a gray level of each of the pixels according to an applied data signal, and a data signal line and the data storage capacitor. a switch transistor including a plurality of transistors, each transistor including a gate electrode connected to a first gate control signal line, and at least one node between the plurality of transistors of the switch transistor of a first pixel among the pixels; and a connection transistor connected between at least one node between the plurality of transistors of the switch transistor of a second pixel adjacent to the first pixel and including a gate electrode connected to a second gate control signal line.

Description

Pixel circuit and its driving method

The present invention relates to a pixel circuit and a method for driving the same.

In recent years, as a display device, for example, an organic light emitting display device using a self-luminous element such as a liquid crystal display device (LCD) or an organic light emitting element has been widely adopted. A pixel of the liquid crystal display includes a switching transistor, a liquid crystal capacitor, and a data storage capacitor. A pixel of an organic light emitting diode display includes a light emitting element, a driving transistor for driving the self-luminous element, a switching transistor, and a data storage capacitor. The display device includes a plurality of pixels arranged in a matrix form.

Grayscale data for controlling luminance is written in pixels of the display device. The gradation data once written must be maintained for a certain period until the gradation data is written next. Here, when an off-leak current is generated in the switch transistor of the pixel to which the grayscale data is applied, the voltage applied to the pixel changes with time (with the lapse of time). Accordingly, a problem such as a flicker phenomenon or a change in the luminance of the pixel occurs.

Patent Documents 1 and 2 disclose a configuration in which the switch transistors are connected in series for the purpose of reducing the off-leak current of the switch transistor of the pixel to which the grayscale data is applied. With this configuration, the off-resistance of the switch transistor can be increased and the off-leakage current can be reduced.

However, even if the number of the switch transistors connected in series is increased, the electric charge accumulated in the parasitic capacitance of the switch transistor moves due to off-leakage of the switch transistor. Accordingly, the grayscale data written in the pixel is changed.

Japanese Patent Laid-Open No. 2007-010872 Japanese Patent Laid-Open No. 2008-175945

SUMMARY OF THE INVENTION An object of the present invention is to provide a detailed pixel circuit with improved image quality.

Another object of the present invention is to provide a method of driving the pixel circuit.

A pixel circuit according to an embodiment of the present invention includes: a data storage capacitor, a data signal line, arranged in each of the pixels arranged in a matrix shape, and storing a voltage for controlling a gray level of each of the pixels according to an applied data signal; a switch transistor connected in series between the data storage capacitors and including a plurality of transistors each including a gate electrode connected to a first gate control signal line; a gate electrode connected between at least one node between transistors and at least one node between the plurality of transistors of the switch transistor of a second pixel adjacent to the first pixel, and connected to a second gate control signal line It includes a connection transistor comprising a.

According to the pixel circuit, it is possible to suppress the off-leak current of the switch transistor connected to the data storage capacitor for adjusting the gray level of the pixel by using a smaller number of additional elements and wiring compared to the related art. In addition, since the influence of the voltage fluctuation of the data signal line on the gray level can be reduced, the number of elements or wirings in each of the pixels can be reduced to realize a detailed pixel. It is possible to suppress a change in luminance and a flicker phenomenon due to the off-leak current of the switch transistor connected to the gate electrode of the driving transistor.

According to another preferred embodiment of the pixel circuit, the at least one node may be connected to a power line of a predetermined voltage through the connection transistor.

According to this pixel circuit, the potential of the at least one node is stabilized. Accordingly, it is possible to further suppress the off-leak current of the switch transistor connected to the data storage capacitor for adjusting the gray level of the pixel. In addition, it is possible to further reduce the influence of the voltage fluctuation of the data signal line on the gradation.

According to another preferred embodiment of the pixel circuit, a voltage applied to the data storage capacitor is applied to a gate electrode, and a driving transistor for controlling a magnitude of the supplied current of a light emitting device that emits light according to the supplied current; The light emitting device may further include an emission transistor connected between the transistor and the light emitting device, the emission transistor being controlled together with the connection transistor, and controlling the current supplied to the light emitting device. The switch transistor may include a first switch transistor connected between the first signal line and the data storage capacitor and a second switch transistor connected between the second signal line and the data storage capacitor. The first switch transistor and the second switch transistor are connected at the at least one node. In the turn-on period of the switch transistor, the connection transistor is turned off, and the connection transistor is turned on in at least a partial period after the switch transistor is turned off.

According to this pixel circuit, in the pixel circuit of the organic light emitting diode display, the control lines of the connection transistor and the emission transistor are shared, so that there is no need to add a new control signal line. Therefore, since the voltage fluctuation of the gate electrode of the driving transistor can be suppressed while the number of wirings is suppressed, it is possible to provide a high-definition pixel, and the change in luminance and the flicker phenomenon can be suppressed.

A method of driving a pixel circuit according to an embodiment of the present invention includes the pixel circuit described above. In the driving method of the pixel circuit, the switch transistor is turned on after the connection transistor is turned off, and the connection transistor is turned on after the switch transistor is turned off.

According to this pixel circuit, it is possible to suppress the off-leak current of the switch transistor connected to the data storage capacitor for adjusting the gradation of the pixel with a smaller number of additional elements and wiring compared to the conventional one. In addition, it is possible to reduce the influence of the voltage fluctuation of the data signal line on the gradation.

According to another preferred embodiment of the pixel circuit, the at least one node may be connected to a power supply line of a predetermined voltage during a turn-on period of the connection transistor.

According to this pixel circuit, the potential of the at least one node is more stable. Compared to the related art, it is possible to further suppress voltage fluctuations due to the transfer of charges accumulated in the data storage capacitor due to the off-leak current of the switch transistor with fewer additional elements and wiring. In addition, it is possible to further suppress voltage fluctuations due to transfer of charges accumulated in the data storage capacitor due to voltage fluctuations of the data signal lines.

According to another preferred embodiment of the pixel circuit, the at least one node may be connected to a power line of a predetermined voltage through the connection transistor.

According to this pixel circuit, since the potential of the at least one node is more stable, the off-leak current of the switch transistor connected to the data storage capacitor for adjusting the gradation of the pixel can be suppressed with fewer additional elements and wiring compared to the prior art. can In addition, it is possible to further reduce the influence of the voltage fluctuation of the data signal line on the gradation.

According to another preferred embodiment of the pixel circuit, each of the pixels applies a voltage applied to the data storage capacitor to a gate electrode, and controls the amount of the supplied current of the light emitting device that emits light according to the supplied current. It may further include a driving transistor and an emission transistor connected between the driving transistor and the light emitting device to control a current supplied to the light emitting device. The emission transistor may be turned on together with the switch transistor, and may be turned off together with the switch transistor.

According to this pixel circuit, in the organic light emitting display device, it is possible to suppress the off-leakage rate of the switch transistor connected to the data storage capacitor for adjusting the gradation of the pixel with fewer additional elements and wiring compared to the prior art. Further, since it is possible to reduce the influence of the voltage fluctuation of the data signal line on the gray level, it is possible to suppress the voltage fluctuation of the gate electrode of the driving transistor.

According to another preferred embodiment of this pixel circuit, the switch transistor comprises a first switch transistor connected between the first signal line and the data storage capacitor and a second switch transistor connected between the second signal line and the data storage capacitor. may include The first switch transistor and the second switch transistor may be connected at the at least one node. After the connection transistor is turned off, the first switch transistor is turned on, and after the first switch transistor is turned off, the second switch transistor is turned on, and the second switch transistor is After being turned off, the connection transistor may be turned on.

According to this pixel circuit, it is possible to suppress the off-leakage of the switch transistor connected to the data storage capacitor that adjusts the gradation of the pixel with fewer additional elements and wiring compared to the prior art, and also, the voltage fluctuation of the data signal line is reduced to the gradation. impact can be reduced.

According to the present invention, it is possible to provide a refined pixel circuit by reducing the number of elements and wirings included in each of the pixel circuits. In addition, by preventing a change in the threshold voltage of the driving transistor, it is possible to prevent a change in luminance and a flicker phenomenon of the pixel circuit. Accordingly, the pixel circuit may provide an image with improved image quality.

1 is a block diagram of a light emitting display device according to an exemplary embodiment.
2 is a circuit diagram of a pixel circuit according to an exemplary embodiment.
3 is a circuit diagram of a pixel according to an exemplary embodiment of the present invention.
4 is a timing chart of signals according to an embodiment of the present invention.
5A is a diagram illustrating a conventional pixel operation.
5A is a diagram illustrating a voltage change occurring during a conventional pixel operation.
6A is a diagram illustrating an operation of a pixel circuit according to an exemplary embodiment.
6B is a diagram illustrating a voltage change occurring during an operation of a pixel circuit according to an exemplary embodiment of the present invention.
7 is a block diagram of a light emitting display device according to an exemplary embodiment.
8 is a circuit diagram of a pixel according to an embodiment of the present invention.
9 is a timing chart of signals according to an embodiment of the present invention.
10 is a block diagram of a light emitting display device according to an exemplary embodiment.
11 is a circuit diagram of a pixel according to an embodiment of the present invention.
12 is a timing chart of signals according to an embodiment of the present invention.
13 is a circuit diagram of a pixel according to an exemplary embodiment.

Hereinafter, a pixel circuit for driving a light emitting element according to the present invention and a display device using the same will be described with reference to the drawings. However, the pixel circuit for driving the light emitting element of the present invention and the display device using the same can be implemented in many other embodiments, and should not be interpreted as being limited to the description of the embodiments shown below. In addition, in the drawings referred to in this embodiment, the same code|symbol is attached|subjected to the same part or the part which has the same function, and the repetition description is abbreviate|omitted.

(Example 1)

The configuration and operation method of the light emitting display device according to the first exemplary embodiment will be described with reference to FIGS. 1 to 4 . 1 is a block diagram illustrating an example of the configuration of a light emitting display device according to a first embodiment. The pixels 10 of the light emitting display device are arranged in a matrix of n rows and m columns. The pixels 10 are controlled by a scan driver 20 , an emission driver 30 , and a data driver 40 . Here, n is a natural number greater than or equal to 1, and m is a natural number greater than or equal to 1. For example, when n=3, it refers to a group of pixel circuits arranged in the third row, and when m=3, it refers to a group of pixel circuits arranged in a third column. In addition, although the pixel circuit 10 is arrange|positioned in the matrix shape of 3rd row and 3rd column in FIG. 1, it is not limited to this arrangement|positioning.

The scan driver 20 is a driving circuit that selects a row in which a data signal is written (or applied), and a gate control signal ( SCAN(n)) is supplied. In this example, each row is sequentially and exclusively selected in a predetermined order.

The emission driver 30 controls the timing of supplying a signal to the light emitting device, and transmits the emission control signals ( EM(n)) is supplied. When the gate control signal lines 21 , 22 , and 23 are defined as a first gate control signal line, the emission control signal lines 31 , 32 , and 33 may be defined as a second gate control signal line.

The data driver 40 determines a gray level based on input image data, supplies a data signal according to the determined gray level to the pixels 10 , and uses data signal lines 41 corresponding to the pixels 10 in each column. The data signal DT(m) is supplied to 42 and 43 , and the data value VDATA(n) is written into the pixels 10 .

In addition, in the present embodiment, the pixels 10 arranged in each row direction are connected to the reference power supply VDM, and are connected to the emission control signal EM(n) supplied from the emission driver 30 . Connection transistors M3(m) (transistors connected between adjacent pixels, hereinafter referred to as connection transistors) controlled by is connected to

2 is a circuit diagram illustrating an example of a more detailed circuit configuration of a pixel circuit in an nth row. 2 illustrates a case in which all of the transistors constituting the pixels 10 are p-channel type. One pixel 10 includes an anode power supply ELVDD, a cathode power supply ELVSS, a driving transistor M1(m), a switch transistor M21(m) and M22(m), a capacitor Cst(m), or a storage capacitor) and a light emitting device D1(m). Here, the capacitance (data storage capacitor) for storing the voltage corresponding to the data signal may include a capacitor Cst(m), a parasitic capacitance of a switch transistor, and a parasitic capacitance between wires. As such, one pixel may include four transistors and one capacitor.

A connection relationship between the elements of each of the pixels 10 will be described using the pixels 10 in the first column (m=1). One of the source electrode and the drain electrode of the driving transistor M1 ( 1 ) is connected to the anode power supply ELVDD, and the other is connected to the anode electrode of the light emitting element D1 ( 1 ). The gate electrode of the driving transistor M1(1) is connected to one electrode of the capacitor Cst(1). Switch transistors M21 ( 1 ) and M22 ( 1 ) are connected in series between the gate electrode of the driving transistor M1 ( 1 ) and the data signal line 41 . The other electrode of the capacitive element Cst(1) is connected to the anode power supply ELVDD. Further, the cathode electrode of the light emitting element D1 ( 1 ) is connected to the cathode power supply ELVSS.

The switch transistors M21 ( 1 ) and M22 ( 1 ) are controlled by the gate control signal SCAN(n) supplied by the gate control signal line 24 . The switch transistor M21(1) M22(1) includes two transistors M21(1) and M22(1), and the two transistors M21(1) and M22(1) are gated It is simultaneously controlled by the gate control signal SCAN(n) supplied by the control signal line 24 . Also, the node SM(1) between the two transistors M21( 1 ) and M22( 1 ) is connected to the switch transistor M21( ) of the adjacent pixel 10 through the connection transistor M3( 1 ) 2) and M22(2), connected to the node SM(2) between the two transistors M21(1) and M22(1). The nodes are connected to the reference power supply (VDM) at the end of the pixel circuit. Further, the connection transistors M3( 1 ), M3( 2 ), and M3( 3 ) are simultaneously controlled by the emission control signal EM(n) supplied by the emission control signal line 34 .

Fig. 3 shows a circuit configuration of one pixel, and Fig. 4 shows a timing chart of circuit operation. An operation of the pixel circuit will be described with reference to FIGS. 3 and 4 .

Hereinafter, various signals for operating the pixel circuit will be described as voltage signals representing logic levels of “low level” and “high level”. Incidentally, hereinafter, it is indicated that the transistor conducts as “the transistor is turned on” or “the transistor turns on”, and that the transistor does not conduct is “the transistor turns off” or “the transistor turns-on” It goes off."

Fig. 4 shows a timing chart. First, after the emission control signal EM supplied to the emission control signal line 35 becomes high level and the connection transistor M3 is turned off, the gate control signal SCAN supplied to the gate control signal line 25 is turned off. ) to a low level, so that the switch transistors M21 and M22 are turned on. The data signal DT is supplied to the gate electrode of the driving transistor M1 through the data line 45 and the data value VDATA corresponding to the data signal is charged in the capacitor Cst, so that the pixel 10 is gradation data is written in Here, at least a data write period (a period in which the gate control signal SCAN is at a low level and M21 and M22 is turned on) is a period in which the emission control signal EM is at a high level, and the connection transistor M3 is turned off.

In Fig. 4, the timing at which the emission control signal EM changes to the high level (turning off the connection transistor M3) is the timing at which the gate control signal SCAN changes to the low level (switch transistors M21 and M22) Although a case is shown that is earlier than the timing of turning on , the two timings may be the same.

When the gate control signal SCAN is changed to a high level, the switch transistors M21 and M22 are turned off, so that the supply of the data signal DT is stopped. That is, writing of the gradation data is completed. After the writing of the grayscale data is completed, the emission control signal EM is changed to a low level, so that the connection transistor M3 is turned on, and the nodes SM of the adjacent pixels 10 are connected; It is also connected to the reference power supply (VDM).

In this embodiment, the potential of the reference power supply VDM is set to the average value of the maximum and minimum values of data values written in the same row, but the potential of the reference power supply VDM is the average value of all data values written in the same row , or may be set to be an average value of all data written in all pixels.

In the present embodiment, the nodes SM of the adjacent pixels 10 are connected to each other as well as to the reference power supply VDM, so that any one of the unselected switch transistors M21 and M22 is connected to the transistor M22. Even when an off-leakage current is generated due to a voltage change of the connected data signal DT, the influence on the potential of the gate electrode of the driving transistor M1 can be alleviated. As a result, image quality deterioration due to crosstalk or the like is also improved.

As described above, since the node SM between the two transistors of the switch transistors M21 and M22 is connected to the reference power supply VDM, the charge of the node SM is immediately transferred to the reference power supply VDM after writing of grayscale data is finished. VDM) is fixed. As a result, the potential difference between the source electrode and the drain electrode of the other transistor M21 of the switch transistors M21 and M22 becomes small, and the off-leakage current of any one of the transistors M21 of the switch transistors M21 and M22 becomes small. seldom occurs. Accordingly, the driving transistor M1 may operate stably.

In addition, in the operation of the pixel, when either one of the switch transistors M21 and M22 is unselected, the voltage fluctuation of the data signal DT affects the gate electrode of the driving transistor M1 can be suppressed. Accordingly, the driving transistor M1 may operate stably.

Next, the effect of this invention is demonstrated in detail compared with a prior art example. 5A is a diagram illustrating a conventional pixel operation. 5A is a diagram illustrating a voltage change occurring during a conventional pixel operation.

As shown in FIG. 5A , the node SM between the two transistors of the switch transistors M21 and M22 is not connected to the node MS and the reference power supply VDM of the adjacent pixel. When the gate control signal SCAN is at a high level, the switch transistors M21 and M22 are turned off, and the switch transistors M21 and M22 may The potential of the node SM between the two transistors rises. For example, the potential VSM of the node SM may be greater than the potential VGATE of the gate electrode of the driving transistor M1 . In this case, a current flows from the node SM to the gate electrode of the driving transistor M1 by the off-leak current of the switch transistor M21, and the potential of the gate electrode of the driving transistor M1 changes. Also, when a data signal is supplied to any one of the transistors M22 of the non-selection switch transistors M21 and M22, the potential VSM of the node SM is generated by the off-leak current of the one of the transistors M22. However, the potential VGATE of the gate electrode of the driving transistor M1 may be changed.

6A is a diagram illustrating an operation of a pixel circuit according to an exemplary embodiment. 6B is a diagram illustrating a voltage change occurring during an operation of a pixel circuit according to an exemplary embodiment of the present invention.

In this embodiment, the node SM between the two transistors M21 and M22 of the switch transistors M21 and M22 is connected to the reference power supply VDM through the connection transistor M3. The reference power source VDM is fixed at a potential substantially equal to the potential VGATE of the gate electrode of the driving transistor M1. After the emission control signal EM is changed to a high level to turn off the connection transistor M3, the gate control signal SCAN is changed to a low level to turn on the switch transistors M21 and M22 . Thereafter, after the gate control signal SCAN is changed to a high level and the switch transistors M21 and M22 are turned off, the emission control signal EM is changed to a low level so that the connection transistor M3 is turned-off. comes on When the switch transistors M21 and M22 are turned off, the potential of the node SM rises due to the effect of the electric charge accumulated in the parasitic capacitance of the switch transistors M21 and M22, but the connection transistor M3 turns off By being turned on, the node SM is connected to the reference power supply VDM. Accordingly, the potential of the node SM is fixed to the potential of the gate electrode of the driving transistor M1 supplied from the reference power VDM.

Since there is almost no potential difference between the source and drain electrodes of the other transistor M21 of the switch transistors M21 and M22, most of the off-leak current does not flow. Also, even when an off-leak current occurs in any one of the switch transistors M21 and M22, the node SM between the two transistors M21 and M22 of the switch transistors M21 and M22 is Since it is fixed to the reference power supply VDM, the data signal does not affect the potential of the gate electrode of the driving transistor M1.

As described above, according to Embodiment 1 of the present invention, it is possible to suppress the voltage fluctuation of the gate electrode of the driving transistor due to the off-leak current of the switch transistor with a small number of additional elements and wirings. In addition, it is possible to suppress the voltage fluctuation of the gate electrode of the driving transistor due to the voltage fluctuation of the data signal line. As a result, since the size of the capacitive element of the data storage capacitor can be significantly reduced, the aperture ratio can be raised, and high-definition is realized.

(Example 2)

The configuration and operation method of the light emitting display device according to the second embodiment will be described with reference to FIGS. 7 to 9 . 7 is a schematic diagram illustrating an example of the configuration of a light emitting display device according to a second embodiment. In a configuration different from the first embodiment, the emission control signal (EM) (n) is connected to the connection transistor M3 through the emission control signal lines 31 , 32 , 33 connected to the emission driver 30 . The point is that it is supplied to each pixel. Configurations other than that are substantially the same as those described with reference to FIG. 1 , and thus a detailed description thereof will be omitted. Emission control signal (EM(n)). The connection relationship between the emission control signal lines 31 , 32 , 33 and the pixel will be described in detail with reference to FIG. 8 .

Fig. 8 shows a circuit diagram of one pixel 10, and Fig. 9 shows a timing chart of circuit operation. An operation of the corresponding pixel will be described with reference to FIGS. 8 and 9 . Since the basic circuit operation is the same as that of the first embodiment, the description will be focused on points different from those of the first embodiment.

In the circuit diagram of the pixel illustrated in FIG. 8 , an emission transistor M4 is added to the circuit diagram of the pixel illustrated in FIG. 3 . The source electrode and the drain electrode of the emission transistor M4 are respectively connected to the driving transistor M1 and the light emitting element D1, and the gate electrode of the emission transistor M4 is connected to the emission control signal line 35, have. The connection transistor M3 and the emission transistor M4 are simultaneously controlled by the emission control signal EM. According to this second embodiment, it is possible to perform light emission control without adding a new control signal line.

9 is a timing chart of signals applied to a pixel. First, when the emission control signal EM is at a high level, the connection transistor M3 and the emission transistor M4 are turned off. Thereafter, the gate control signal SCAN is changed to a low level so that the switch transistors M21 and M22 and the two transistors M21 and M22 of the switch transistors M21 and M22 are simultaneously turned on. The data signal DT is supplied to the gate electrode of the driving transistor M1 through the data signal line 45 . By charging the data value VDATA corresponding to the data signal DT in the capacitor Cst, grayscale data is written into the pixel PX. Here, the emission control signal EM has a high level at least during a data writing period (a period in which the gate control signal SCAN is at a low level and the switch transistors M21 and M22 are turned on). The connection transistor M3 and the emission transistor M4 are turned off, the nodes SM of the adjacent pixels are blocked, and the light emission of the light emitting device D1 is stopped.

In FIG. 9 , the timing at which the emission control signal EM is changed to the high level (the timing when the connection transistor M3 and the emission transistor M4 are turned off) is when the gate control signal SCAN is changed to the low level Although the case where the timing is earlier than the timing (the timing at which the switch transistors M21 and M22 are turned on) is shown, the two timings may be the same.

As the gate control signal SCAN is changed to a high level and the switch transistors M21 and M22 are turned off, the supply of the data signal DT is stopped, and writing of grayscale data is completed. After writing of grayscale data is completed, the emission control signal EM is changed to a low level, so that the connection transistor M3 and the emission transistor M4 are turned on, and the node SM between adjacent pixels is turned on. are connected, and also connected to the reference power supply (VDM). At the same time, the anode power supply ELVDD is supplied to the light emitting device D1 so that the light emitting device D1 emits light.

In FIG. 9 , the timing at which the emission control signal EM is changed to the low level (the timing at which the connection transistor M3 and the emission transistor M4 are turned on) is when the gate control signal SCAN is changed to the high level Although the case where the timing is slower than the timing (the timing at which the switch transistors M21 and M22 are turned off) is shown, the two timings may be the same.

As such, in order to control ON/OFF of the connection transistor M3 and the emission transistor M4 at the same timing, the connection transistor M3 and the emission transistor M4 may receive a gate control signal in common. According to the above, since it is not necessary to newly add a control signal line, a high-definition pixel can be provided and the aperture ratio of the pixel is improved. In another embodiment of the present invention, each of the connection transistor M3 and the emission transistor M4 may be controlled with an independent gate control signal.

As described above, according to the second embodiment of the present invention, there is no need to add a new control signal line in the case of stopping light emission during light emission duty control or data writing operation. can provide Also, like the first embodiment, the pixel circuit according to this embodiment has an off-leak current reduction effect.

(Example 3)

The configuration and operation method of the light emitting display device according to the third embodiment will be described with reference to FIGS. 10 to 12 . 10 is a block diagram illustrating an example of the configuration of a light emitting display device according to a third embodiment. In the third embodiment, the emission control signal EM(n) is supplied to the connection transistor M3 and the pixels through the emission control signal lines 301, 302, 303 connected to the emission driver 300, respectively, The gate control signals SCAN(n-1) and SCAN(n) are supplied to each of the pixels through the gate control signal lines 201 , 202 , 203 , 211 , 212 and 213 connected to the scan driver 200 . The configuration is different from the first embodiment. Other points are the same as in FIG. 1 , and thus detailed description thereof will be omitted. The connection relationship between the emission control signal EM(n), the gate control signals SCAN(n-1), and SCAN(n) and the pixel will be described in detail with reference to FIG. 11 .

Fig. 11 shows a circuit diagram of one pixel, and Fig. 12 shows a timing chart of pixel operation. The operation of the pixel will be described with reference to FIGS. 11 and 12 .

11 , the pixel 10 includes a driving transistor M1 , switch transistors M21 , M22 , M5 , M71 , M72 , emission transistors M4 and M6 , and the pixel 10 . A connection connecting a node SM1 (hereinafter referred to as a first node) and a node SM1 of an adjacent pixel, and connecting a node SM2 (hereinafter referred to as a second node) of the pixel 10 and a node SM2 of an adjacent pixel It includes a transistor M3, a capacitor Cst, and a light emitting device D1. The pixel 10 is connected to an anode power supply ELVDD, a cathode power supply ELVSS, a data signal line 405 , gate control signal lines 205 and 215 , an initialization signal line 2 , and an emission control signal line 305 . Here, the data storage capacitor includes a capacitor Cst(m), a parasitic capacitance of a switch transistor, and a parasitic capacitance between wirings.

The anode power supply ELVDD shown in FIG. 11 is the anode power supply of the light emitting element D1 in the light emission period, and the cathode power supply ELVSS is the cathode power supply of the light emitting element D1. An initialization signal VINIT for initializing the gate potential of the driving transistor M1 to a predetermined potential is supplied to the initialization signal line 2 connected to the switch transistors M71 and M72. Further, the gate electrodes of the switch transistors M71 and M72 are connected to the gate control signal line 205 and are simultaneously controlled by the gate control signal (SCAN)(n-1). The gate electrodes of the switch transistors M21, M22 and M5 are connected to the gate control signal line 215, and are simultaneously controlled by the gate control signal (SCAN)(n). Further, the switch transistors M21 and M22 are connected in series between the gate electrode and the source electrode or the drain electrode (between M1 and M4) of the driving transistor M1, for example, a diode connection.

The connection transistor M3 and the gate electrodes of the emission transistors M4 and M6 are connected to the emission control signal line 305 and are simultaneously controlled by the emission control signal EM(n). According to the third embodiment, threshold compensation and light emission control are possible. Such a circuit configuration is generally referred to as a threshold value compensation circuit, and the influence of variations in the threshold voltage Vth of the driving transistor M1 may be reduced.

In addition, in FIG. 11 , each of the transistors M1 , M21 , M22 , M3 , M4 , M5 , M6 , M71 , and M72 is configured as a P-channel transistor. Each of the transistors M1, M21, M22, M3, M4, M5, M6, M71, and M72 includes a control signal (gate control signal SCAN(n-1), SCAN(n)) applied to a gate electrode, an EMI It is selectively turned on/off by the option control signal EM(n) As described above, it is composed of six transistors and one capacitive element.

First, after the emission control signal EM(n) is changed to a high level, the connection transistor M3 and the emission transistors M4 and M6 are turned off, the gate control signal SCAN(n-1) )) is changed to a low level and the switch transistors M71 and M72 are turned on, so that the gate potential of the driving transistor M1 is initialized to the potential of the initialization signal line VINIT.

Then, the gate control signal SCAN(n-1) is changed to a high level, the gate control signal SCAN(n) is changed to a low level, and the switch transistors M71 and M72 are turned off and At the same time, the switch transistors M21, M22, and M5 are turned on. Some of the transistors M21, M22, and M5 are turned on, so that the data signal DT through the data signal line 405 is transferred to the switch transistor M5, the driving transistor M1, and the switching transistors M21 and M22. ) and applied to the gate electrode of the driving transistor M1. At this time, looking at the connection relationship between the driving transistor M1 and the switch transistors M21 and M22 , the switch transistors M21 and M22 have a gate electrode of the driving transistor M1 and a source electrode or a drain electrode of the driving transistor M1 . It is connected in series between (between M1 and M4), so-called diode connection. In the present embodiment, a case has been described where the timing at which the gate control signal SCAN(n-1) goes to the high level and the timing at which the gate control signal SCAN(n) goes to the low level coincide with each other. After SCAN(n-1) is changed to a high level, the gate control signal SCAN(n) may be changed to a low level after a certain period of time.

Subsequently, the gate control signal SCAN(n) is changed to a high level, and the switch transistors M21, M22, and M5 are turned off. Thereafter, the emission control signal EM(n) is changed to a low level, so that the connection transistor M3 and the emission transistors M4 and M6 are turned on. As the connection transistor M3 is turned on, the first nodes SM1 between adjacent pixels are connected, and the second nodes SM2 are connected. In addition, the first nodes SM1 and the second nodes SM2 are connected to a reference power source VDM.

In addition, as the emission transistors M4 and M6 are turned on, a current biased by a voltage corresponding to the data value VDATA accumulated in the capacitor Cst is transferred from the anode power source ELVDD to the emission transistor It is supplied to the light emitting element D1 via M6, the driving transistor M1, and the emission transistor M4. Accordingly, the light emitting device D1 emits light.

Here, at least the initialization period and the data writing period (the period in which any one of the gate control signals SCAN(n-1) and SCAN(n)) is at a low level, or any one of the transistors M21, M22, M71, and M72 During the period in which is turned on), the emission control signal EM(n) has a high level, thereby turning off the connection transistor M3. Accordingly, the first nodes SM1 of the adjacent pixels are cut off and the second nodes SM2 are cut off.

In Fig. 11, the timing at which the emission control signal EM(n) changes to the high level is earlier than the timing at which the gate control signal SCAN(n-1) changes to the low level, and the emission control signal Although the timing at which (EM(n)) is changed to the low level is slower than the timing when the gate control signal SCAN(n) is changed to the high level, this is only an example. The timing at which the emission control signal EM(n) changes to the high level and the timing at which the gate control signal SCAN(n-1) changes to the low level are the same, or the emission control signal EM(n) The timing at which is changed to the low level may be the same as the timing at which the gate control signal SCAN(n) is changed to the high level. As described above, according to the third embodiment of the present invention, all switch transistors connected to the gate electrode of the driving transistor M1 are affected by the off-leak current, but the first node SM1 and the second node SM1 of the pixel 10 are To short-circuit two nodes SM2 to each other or to short-circuit the first node SM1 and the second node SM2 of the pixel 10 to corresponding nodes of an adjacent pixel through a connection transistor M3 can Accordingly, even when there are a plurality of switch transistors connected to the gate electrode of the driving transistor M1 , it is possible to provide a high-definition pixel and an improved aperture ratio without adding control signal lines and transistors.

(Example 4)

13 is a circuit diagram of a pixel according to the fourth embodiment. The circuit diagram of the pixel shown in Fig. 13 is an example of the LCD pixel. A data signal line 45, a gate control signal line 25, a capacitor Cst having one electrode connected to a common electrode COMMON, and a liquid crystal capacitor having one electrode connected to a common electrode COMMON LC, the other electrode of the capacitor Cst and the other electrode of the liquid crystal capacitor LC, and the switch transistors M81 and M82 connected in series between the data signal line 45, and the node of the pixel a connection transistor M3 connecting the node SM of the pixel adjacent to the SM, a reference power supply VDM, and an emission control signal line 35 connected to the gate electrode of the connection transistor M3 . One pixel is composed of three transistors and one capacitor. Here, the data-retaining capacitance includes the capacitor Cst(m), the parasitic capacitance of the switch transistor, and the parasitic capacitance between wirings.

Also in the LCD, when a leakage current occurs in the switch transistors M81 and M82, the potential accumulated in the capacitor Cst changes, and the voltage applied to the liquid crystal capacitor LC fluctuates. As a result, the transmittance of the liquid crystal capacitor LC changes, which causes luminance fluctuations.

As described above, according to the fourth embodiment of the present invention, it is possible to suppress the potential fluctuation of the capacitor Cst due to the off-leak current of the switch transistor with a small number of additional elements and wirings in the LCD. As a result, since the capacitive element size of the data storage capacitor can be significantly reduced, the aperture ratio can be increased, and high-definition is realized. Here, since the detailed operation method of the fourth embodiment is extremely similar to the operation shown in the first embodiment, the operation method is omitted here.

In the operation of the pixel circuit described in Embodiments 1 to 4 of the present invention, only the nodes SM and the node between M21 and M22 of the switching transistors of adjacent pixels are connected or nodes of the switching transistors of adjacent pixels (SM, between M21 and M22) are connected. SM, the node between M71 and M72) is connected, or only the nodes of the switching transistors of adjacent pixels (the node between M81 and M82) are connected, and when not connected to the reference power supply (VDM), the node ( SM) is averaged with the potentials of all nodes between the connected adjacent pixels. Also in such a configuration, the potential difference between the source electrode and the drain electrode of the switch transistor directly connected to the gate electrode of the driving transistor M1 can be reduced compared to the conventional example. As a result, the voltage fluctuation of the gate electrode of the driving transistor M1 is suppressed, and the change in luminance and the flicker phenomenon caused by the threshold value fluctuation of the driving transistor can be suppressed.

Further, in the pixel circuits described in Embodiments 1 to 3 of the present invention, although it has been described that nodes between adjacent pixels arranged in the gate control signal line direction are connected, adjacent pixels arranged in the data signal line direction Nodes between them may be connected. In that case, driving is divided into a writing (non-emission) period and a light emission period of one frame, so-called simultaneous driving is operated, and at least during the non-emission period, the connection transistor M3 is turned off, and the subsequent light emission period is At least a portion of the connection transistor M3 may be turned on.

Further, in the pixel circuits described in Embodiments 1 to 4 of the present invention, although the pixel includes a P-channel transistor, the pixel is constituted by an N-channel transistor or both (CMOS type) of an N-channel type and a P-channel type. It may include a transistor.

Further, in the pixel circuits described in Embodiments 1 to 4 of the present invention, a data signal line and an initialization signal line are given as examples of the signal lines connected to the data storage capacitor via the switch transistor, but for example, in at least a part of the period. In this case, the same effect can be obtained if a signal line to which a voltage different from the voltage applied to the data storage capacitor is supplied.

As described above, according to the invention described in the first to fourth embodiments, it is possible to suppress the gradation fluctuation of the pixel due to the off-leak current of the switch transistor with a small number of additional elements and wirings. As a result, since the size of the capacitive element of the data storage capacitor can be greatly reduced, the layout size in the display area can be reduced, and high definition and improvement of the aperture ratio are realized.

In addition, this invention is not limited to the said embodiment, It is possible to change suitably in the range which does not deviate from the meaning.

1: Reference power line 2: Initialization signal line
10: pixel circuit 20, 200: scan driver
21, 22, 23, 24, 25: gate control signal line
201, 202, 203, 205: gate control signal lines
211, 212, 213, 215: gate control signal lines
30, 300: Emission Driver
31, 32, 33, 34, 35: Emission control signal line
301, 302, 303, 305: emission control signal line
40, 400: data driver
41, 42, 43, 45: data signal line
401, 402, 403, 405: data signal line

Claims (8)

a first pixel;
a second pixel disposed adjacent to the first pixel;
a third pixel disposed adjacent to the second pixel; and
Including first to third connection transistors,
Each of the first pixel, the second pixel, and the third pixel,
light emitting element;
a data storage capacitor configured to store a voltage for controlling grayscale according to an applied data signal;
a driving transistor including a first electrode receiving a power supply voltage, a second electrode connected to the light emitting device, and a gate electrode connected to the capacitor;
a first switch transistor including a first electrode connected to a data signal line, a second electrode connected to a first node, and a gate electrode connected to a first gate control signal line; and
a second switch transistor including a first electrode connected to the first node, a second electrode connected to a gate electrode of the driving transistor, and a gate electrode connected to the first gate control signal line,
The first connection transistor includes the first node between the first switch transistor and the second switch transistor of the first pixel, and the second node between the first switch transistor and the second switch transistor of the second pixel. a gate electrode connected between the first nodes and connected to a second gate control signal line;
The second connection transistor includes the first node between the first switch transistor and the second switch transistor of the second pixel, and the second connection transistor between the first switch transistor and the second switch transistor of the third pixel. a gate electrode connected between one node and connected to the second gate control signal line;
the third connection transistor is connected between the first node between the first switch transistor and the second switch transistor of the third pixel and a reference power source, and includes a gate electrode connected to the second gate control signal line; ,
When the first to third connection transistors are turned on, the reference power is supplied to the first node of the first pixel, the first node of the second pixel, and the first node of the third pixel; The reference power is a pixel circuit having a voltage level based on the data signal. The method of claim 1,
The first to third connection transistors are electrically connected to the pixel circuit. 3. The method of claim 2,
Each of the first pixel, the second pixel and the third pixel,
and an emission transistor connected between the driving transistor and the light emitting element, connected to the second gate control signal line, and controlling a current supplied to the light emitting element,
After the first to third connection transistors are turned off, the first switch transistor and the second switch transistor of each of the first to third pixels are turned on,
The pixel circuit, characterized in that after the first switch transistor and the second switch transistor of each of the first to third pixels are turned off, the first to third connection transistors are turned on. a data storage capacitor configured to store a voltage for controlling grayscale according to a data signal applied to each of the first pixel, the second pixel, and the third pixel; a driving transistor including a first electrode receiving a power supply voltage, a second electrode connected to the light emitting device, and a gate electrode connected to the capacitor; a first switch transistor including a first electrode connected to a data signal line, a second electrode connected to a first node, and a gate electrode connected to a first gate control signal line; and a second switch transistor including a first electrode connected to the first node, a second electrode connected to a gate electrode of the driving transistor, and a gate electrode connected to the first gate control signal line. In the method of driving,
After the first to third connection transistors are turned off, the first switch transistor and the second switch transistor of the first pixel, the first switch transistor and the second switch transistor of the second pixel, and the second the first switch transistor and the second switch transistor of 3 pixels are turned on;
The first switch transistor and the second switch transistor of the first pixel, the first switch transistor and the second switch transistor of the second pixel, and the first switch transistor and the second switch transistor of the third pixel After is turned off, the first to third connection transistors are turned on,
The first connection transistor includes the first node between the first switch transistor and the second switch transistor of the first pixel and the first node between the first switch transistor and the second switch transistor of the second pixel a gate electrode connected between the nodes and connected to a second gate control signal line;
The second connection transistor includes the first node between the first switch transistor and the second switch transistor of the second pixel, and the second connection transistor between the first switch transistor and the second switch transistor of the third pixel. a gate electrode connected between one node and connected to the second gate control signal line;
the third connection transistor is connected between the first node between the first switch transistor and the second switch transistor of the third pixel and a reference power source, and includes a gate electrode connected to the second gate control signal line; ,
When the first to third connection transistors are turned on, the reference power is supplied to the first node of the first pixel, the first node of the second pixel, and the first node of the third pixel; The reference power source has a voltage level based on the data signal. 5. The method of claim 4,
The first to third connection transistors are electrically connected to each other. 5. The method of claim 4,
At least one of the first node of the first pixel and the first node of the second pixel is connected to a power line of the reference power source through the connection transistor. 5. The method of claim 4,
Each of the first pixel, the second pixel and the third pixel,
Further comprising an emission transistor connected between the driving transistor and the light emitting device, and controlling the current supplied to the light emitting device,
The emission transistor is turned on together with the first switch transistor and the second switch transistor of each of the first to third pixels, and the first switch transistor and the first switch transistor of each of the first to third pixels A method of driving a pixel circuit, characterized in that it is turned off together with the second switch transistor.
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