KR102345132B1 - Display device having bridge line and method for fabricaging the same - Google Patents

Abstract

The present invention relates to an upper insulating film having a first contact hole and a second contact hole exposing a portion of the first wiring and the second wiring provided with a lower insulating film disposed therebetween, and the first contact hole and the second wiring. Provided is a display device having a bridge wire including a bridge wire filling the inside of two contact holes and an upper insulating layer between the contact holes and connecting the first wire and the second wire.

Description

Display device having bridge wiring and manufacturing method thereof

The present invention relates to a display device, and more particularly, to a display device having a bridge wiring structure and a method of manufacturing the same.

A display device displaying an image includes a substrate, and wirings for transmitting various signals necessary for driving the display device are formed on the substrate. The wirings may be formed in a multi-layered structure belonging to different layers.

An insulating film is provided between the wirings in each layer to insulate the wirings belonging to different layers from each other. However, in some cases, wirings belonging to different layers need to be electrically connected, and in this case, wirings of different layers are electrically connected using a bridge wiring.

A conventional bridge wiring structure having such a bridge wiring will be described with reference to FIG. 1 as follows.

1 is a schematic cross-sectional view of a bridge wiring structure according to the prior art.

Referring to FIG. 1 , a first wiring 13 is formed on a substrate 11 , and an interlayer insulating layer 15 is formed on the substrate 11 including the first wiring 13 .

A second wiring 17 is formed on the interlayer insulating film 15 , and a protective film 19 is formed on the interlayer insulating film 15 including the second wiring 17 .

In addition, a first contact hole (not shown, see 23 of FIG. 3E ) exposing the first wiring 13 is formed in the passivation layer 19 and the interlayer insulating layer 15 , and the passivation layer 19 has the A second contact hole (not shown, see 21 of FIG. 3E ) exposing the second wiring 17 is formed.

On the passivation layer 19 , it is electrically connected to the first wiring 13 through the first contact hole 23 , and is electrically connected to the second wiring 17 through the second contact hole 21 . A bridge wiring 25 to be connected is formed.

Processes of forming the bridge wiring configured as described above will be briefly described with reference to FIG. 2 as follows.

2 is a flowchart of a process for forming a bridge wiring according to the prior art.

Referring to FIG. 2 , the process of forming a bridge wiring according to the prior art includes a process of forming a first wiring on a substrate ( S10 ), and a process of forming an interlayer insulating film on the entire surface of the substrate including the first wiring ( S12 ). ), forming a second wiring on the interlayer insulating film (S14), forming a protective film on the entire surface of the interlayer insulating film including the second wiring (S16), and the first wiring in the protective film and the interlayer insulating film and a step (S18) of forming contact holes exposing the second wiring and the second wiring, and a bridge wiring electrically connecting the first wiring and the second wiring through the first contact hole and the second contact hole on the passivation layer It consists of a step (S20) of forming.

A method of forming a bridge wiring according to the prior art comprising such processes will be described with reference to FIGS. 3A to 3F as follows.

3A to 3F are cross-sectional views schematically illustrating a method of forming a bridge wiring according to the related art.

As shown in FIG. 3A , after depositing a first metal layer (not shown) on the substrate 11 , it is selectively patterned to form the first wiring 13 .

Thereafter, as shown in FIG. 3B , an interlayer insulating layer 15 is deposited on the entire surface of the substrate 11 including the first wiring 13 .

Next, as shown in FIG. 3C , a second metal layer (not shown) is deposited on the entire surface of the substrate 11 including the interlayer insulating film 15 and then selectively patterned to form a second wiring 17 . do.

Thereafter, as shown in FIG. 3D , a protective film 19 is formed on the entire surface of the interlayer insulating film 15 including the second wiring 17 .

Next, as shown in FIG. 3E , the protective film 19 and the interlayer insulating film 15 are selectively patterned to form the first contact hole 23 exposing the first wiring 13 , and the second A second contact hole 21 exposing the second wiring 17 is formed.

Thereafter, as shown in FIG. 3F , after depositing a third metal layer (not shown) on the entire surface of the passivation layer 19 including the first contact hole 23 and the second contact hole 21 , this is selectively A bridge wiring is formed by patterning to form a bridge wiring 25 that electrically connects the first wiring 13 and the second wiring 17 through the first contact hole 23 and the second contact hole 21 . Complete the process.

4 is a cross-sectional view schematically illustrating a single-line structure of a bridge wiring according to the prior art.

As shown in “A” of FIG. 4 , the bridge wiring 25 may be exposed to excessive heat during operation of the display device and may be disconnected. For example, when the protective film 19 under the bridge wiring 25 is formed to have a step difference, the stepped portion has a large resistance and is easily overheated. Accordingly, when the bridge wiring 25 is disconnected due to overheating of the stepped portion, the flow of electrical signals is blocked between the wiring of the upper layer and the wiring of the lower layer connected by the bridge wiring 25 .

As such, when the flow of the electrical signal is blocked, a problem in that the display device is stopped may occur.

In addition, the thickness of the metal layer for the bridge wiring may be formed in various shapes according to the depth or width of the first contact hole of the protective film and the second contact hole of the protective film and the interlayer insulating film.

However, if the taper of the contact hole is not good due to the step difference in the shape and structure of the contact hole, the bridge wiring may be broken as in “A” of FIG. 4, and the bridge wiring may be formed with a thin metal layer thickness. If so, the line resistance will inevitably increase.

Therefore, the resistance uniformity of the bridge wiring is not good, and it is greatly affected by the step difference in the process structure.

In addition, if the size of the contact hole formed to connect the bridge wiring to the wiring is too large, the deposition process may take a lot of time.

Furthermore, since a photo process and an etching process for defining the bridge interconnection region must be additionally performed after depositing the metal layer for the bridge interconnection, the manufacturing process becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bridge wiring capable of not only improving the high-speed driving and current capability of a display device, but also improving the aperture ratio and luminance uniformity by reducing the resistance of the bridge wiring by forming the bridge wiring connecting the wirings thick. An object of the present invention is to provide a display device having the same and a method for manufacturing the same.

Another object of the present invention is to simplify the manufacturing process of the display device by omitting the mask photo process of the metal layer for forming the bridge wiring and forming the bridge wiring using the halftone mask process and the damascene technique. An object of the present invention is to provide a display device having a bridge wiring that can be used and a method for manufacturing the same.

In order to solve the above problems, in one aspect, the present invention provides a first contact hole and a second contact hole for exposing a portion of a first wiring and a second wiring provided with a lower insulating film on a substrate therebetween, respectively. A display device having a bridge wiring including an upper insulating layer provided therein, and a bridge wiring filling the inside of the first contact hole and the second contact hole and the upper insulating layer between the contact holes to connect the first wiring and the second wiring can provide

In a display device having such a bridge line, a first region of the upper insulating layer between the first and second contact holes may have a thickness smaller than a second region of the upper insulating layer outside the first and second contact holes. .

In a display device having such a bridge wiring, the bridge wiring may have the same layer height as a layer height of the second region of the upper insulating layer.

In another aspect, the present invention provides a first thin film transistor on a substrate comprising a first active layer, a first gate electrode and a first source/drain electrode, on the substrate, a second active layer, a second A second thin film transistor including a gate electrode and a second source/drain electrode, the first thin film transistor and the second thin film transistor are disposed on a substrate, the first drain electrode of the first thin film transistor and the second thin film transistor A passivation layer having a first contact hole and a second contact hole exposing the second gate electrode, respectively, and a passivation layer filled on the first and second contact holes and a passivation layer therebetween, the first drain electrode and the second gate electrode It is possible to provide an organic light emitting display device including a bridge wiring for connecting them.

In the organic light emitting display device having such a bridge wiring, the first region of the passivation layer between the first and second contact holes may have a thickness smaller than that of the second region of the passivation layer outside the first and second contact holes. have.

In the organic light emitting display device having such a bridge wiring, the bridge wiring may have the same layer height as the layer height of the second region of the passivation layer.

In another aspect, in the present invention, a lower insulating film interposed between the first and second wirings on a substrate and an upper insulating film disposed on the second wiring are full-ton and half-ton etched through a halftone mask process to obtain the Forming a first contact hole and a second contact hole exposing the first wiring and the second wiring, respectively, and etching a portion of a thickness of an upper insulating layer between the first and second contact holes; and forming a seed metal layer on the upper insulating layer including the second contact hole and then growing the seed metal layer to form a bridge metal layer filling the first and second contact holes; A method of manufacturing a display device having a bridge wire may be provided, comprising forming a bridge wire electrically connecting the first wire and the second wire through the first and second contact holes.

In the method of manufacturing a display device having such a bridge wiring, the forming of the bridge metal layer may be performed by growing the seed metal layer through an electroplating method.

In the method of manufacturing a display device having such a bridge wiring, the step of planarizing the bridge metal layer may be performed through a chemical mechanical polishing (CMP) process.

According to the present invention, by forming thick bridge wires connecting the wires, the resistance of the bridge wires can be reduced to improve high-speed driving and current capability of the display device, as well as improve aperture ratio and luminance uniformity.

The present invention can simplify the manufacturing process of the display device because the bridge wiring can be formed using a halftone mask process and a damascene technique even without the mask photo process of the metal layer for forming the bridge wiring. have.

1 is a schematic cross-sectional view of a bridge wiring structure according to the prior art.
2 is a flowchart of a process for forming a bridge wiring according to the prior art.
3A to 3F are cross-sectional views schematically illustrating a method of forming a bridge wiring according to the related art.
4 is a cross-sectional view schematically illustrating a single-line structure of a bridge wiring according to the prior art.
5 is a plan view illustrating a bridge wiring structure of a display device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5 , and is a cross-sectional view of a bridge wiring of a display device according to an exemplary embodiment of the present invention.
7 is a flowchart illustrating a process of forming a bridge wiring of a display device according to an exemplary embodiment.
8A to 8K are cross-sectional views schematically illustrating a method of forming a bridge wiring of a display device according to an exemplary embodiment.
9 is a schematic circuit configuration diagram of one pixel of an organic light emitting display device according to another embodiment of the present invention.
10 is a schematic plan view of an organic light emitting display device according to another embodiment of the present invention.
11 is a cross-sectional view taken along line XII-XI of FIG. 10 , and is a schematic cross-sectional view of an organic light emitting display device according to another exemplary embodiment of the present invention.
12A to 12K are cross-sectional views schematically illustrating a method of forming a bridge wiring of a display device according to another exemplary embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as much as possible even though they are indicated on different drawings. In addition, in describing the embodiments of the present invention, if it is determined that a detailed description of a related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

In addition, in describing the components of the invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, or order of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but another component is formed between each component. It should be understood that elements may also be “connected,” “coupled,” or “connected.” In the same vein, when it is described that a component is formed "on" or "below" another component, the component is both formed directly on the other component or indirectly through another component. should be understood as including

5 is a plan view illustrating a bridge wiring structure of a display device according to an embodiment of the present invention.

6 is a cross-sectional view taken along line VI-VI of FIG. 5 , and is a schematic cross-sectional view of a display device according to an exemplary embodiment.

Referring to FIG. 5 , a first wiring 103 is formed on a substrate 101 , and an interlayer insulating layer 105 is formed on the substrate 101 including the first wiring 103 .

A second wiring 107 is formed on the interlayer insulating film 105 , and a protective film 109 is formed on the interlayer insulating film 105 including the second wiring 107 .

A first contact hole (not shown, refer to 115 of 8f) for exposing the first wiring 103 is formed in the passivation layer 109 and the interlayer insulating layer 105, and the passivation layer 109 has the A second contact hole (not shown, refer to 117 of FIG. 8F ) exposing the second wiring 107 is formed. In this case, the first region 109a of the passivation layer between the first and second contact holes 115 and 117 is larger than the second region 109b of the passivation layer outside the first and second contact holes 115 and 117 . It has a thin thickness. Accordingly, by forming the first region 109a thinner than the second region 109b, the bridge wiring connecting the wirings in different layers can be formed thickly on the first region 109a, so the resistance of the bridge wiring It is possible to improve the high-speed driving and current capability of the display device by reducing , and also improve the aperture ratio and luminance uniformity.

On the passivation layer 109 , it is electrically connected to the first wiring 103 through the first contact hole 115 , and is electrically connected to the second wiring 107 through the second contact hole 117 . A bridge wiring 121b to be connected is formed. In this case, the bridge wiring 121b has the same layer height as the layer height of the second region 109b of the passivation layer. Accordingly, the film uniformity of the bridge wiring 121b and the passivation layer is improved, so that the aperture ratio and the luminance uniformity can also be improved.

In addition, the bridge wiring 121b is filled only on the first region 109a of the first and second contact holes 115 and 117 and the passivation layer between the first and second contact holes 115 and 117 . have. Accordingly, it is possible to form a thick bridge wire connecting wires in different layers, thereby reducing the resistance of the bridge wire.

The bridge wiring 121b is a wiring used to connect wirings in different layers, and is a display device having a bridge wiring, for example, a liquid crystal display device, an organic light emitting display device, an electrophoretic display device, and a plasma display device. Applicable to devices, etc.

Accordingly, according to the present invention, the high-speed driving and current capability of the display device can be improved by reducing the resistance of the bridge wiring by forming a thick bridge wiring connecting the wirings in different layers, and the aperture ratio and luminance uniformity are also improved. can do it

Processes of forming a bridge wiring of a display device according to an exemplary embodiment of the present invention configured as described above will be described with reference to FIG. 7 .

7 is a flowchart illustrating a process of forming a bridge wiring of a display device according to an exemplary embodiment.

Referring to FIG. 7 , in the bridge wiring forming process of the display device according to an embodiment of the present invention, the first wiring is formed on a substrate ( S110 ), and an interlayer insulating film is formed on the entire surface of the substrate including the first wiring. A process of forming ( S120 ) is performed.

Thereafter, a process of forming a second wiring on the interlayer insulating film ( S130 ) and a process of forming a protective film on the entire surface of the interlayer insulating film including the second wiring ( S140 ) are performed.

Next, a process ( S150 ) of forming a photoresist pattern defined by a full-ton region and a half-ton region on the upper insulating layer through a halftone mask process is performed.

Thereafter, the upper insulating layer and the lower insulating layer are etched using the photoresist pattern as an etch mask to form first and second contact holes exposing the first and second wires, respectively ( S160 ). .

Next, after removing the halftone region of the photoresist pattern, a portion of the thickness of the protective film between the first and second contact holes is etched, and then a seed metal layer is formed on the entire surface of the protective film including the first and second contact holes. The process (S170) proceeds.

Thereafter, a process ( S180 ) of growing the seed metal layer to form a bridge metal layer filling the first and second contact holes is performed.

Next, after planarizing the bridge metal layer (S190), a process (S200) of electrically connecting the first wiring and the second wiring through the first and second contact holes is performed in an embodiment of the present invention. Accordingly, the bridge wiring forming process of the display device is completed.

A method of forming a bridge wiring of a display device according to an exemplary embodiment of the present invention, which is made through these processes, will be described in detail with reference to FIGS. 8A to 8K .

8A to 8K are cross-sectional views schematically illustrating a method of forming a bridge wiring of a display device according to an exemplary embodiment.

As shown in FIG. 8A , after depositing a first metal layer (not shown) on the substrate 101 , the first metal layer is selectively patterned through a photolithography process to form a first wiring 13 . . In this case, as the first metal layer, an aluminum-based metal such as aluminum (Al) or an aluminum alloy (Al alloy), a silver-based metal such as silver (Ag) or a silver alloy (Ag), copper (Cu) or a copper alloy (Cu) alloy), a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy (Mo alloy), and a low-resistance opaque conductive material such as chromium (Cr), tantalum (Ta), or titanium (Ti) may be used. .

Thereafter, as shown in FIG. 8B , an interlayer insulating layer 105 is deposited on the entire surface of the substrate 101 including the first wiring 103 . In this case, a silicon nitride film or a silicon oxide film may be used as the interlayer insulating film 105 .

Next, as shown in FIG. 8C , after depositing a second metal layer (not shown) on the entire surface of the substrate 101 including the interlayer insulating layer 105, the second metal layer is selectively patterned through a photolithography process. Thus, the second wiring 107 is formed. At this time, as the second metal layer, an aluminum-based metal such as aluminum (Al) or an aluminum alloy (Al alloy), a silver-based metal such as silver (Ag) or a silver alloy (Ag), copper (Cu) or a copper alloy (Cu) alloy), a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy (Mo alloy), and a low-resistance opaque conductive material such as chromium (Cr), tantalum (Ta), or titanium (Ti) may be used. .

Thereafter, as shown in FIG. 8D , a protective film 109 is formed on the entire surface of the interlayer insulating film 105 including the second wiring 107 . In this case, a silicon nitride film or a silicon oxide film may be used as the protective film 109 .

Next, a photoresist layer 111 is coated on the passivation layer 109 , and a half-ton mask 113 having a diffraction characteristic is disposed on the photoresist layer 111 . In this case, the halftone mask 113 includes a light blocking part 113a, a semi-transmissive part 113b, and a transmissive part 113c.

Thereafter, as shown in FIG. 8E , the photoresist layer 111 is selectively patterned through a photolithography process using the halftone mask 113 to form a full-ton region 113a and a halftone region. A photoresist pattern composed of (half-ton region) 113b is formed. In this case, the halftone region 113b of the photoresist layer has a thickness smaller than that of the fulltone region 113a. As described above, by using the halftone mask, a separate mask process is not required for additional etching of the first region of the passivation layer to be formed in a subsequent process, thereby simplifying the process of manufacturing the bridge wiring of the display device.

Next, as shown in FIG. 8F , the protective film 109 and the interlayer insulating film 105 are etched using the full-tone region 113a and the half-tone region 113b of the photoresist film as an etch mask to form the first wiring. A first contact hole 115 exposing the 103 and a second contact hole 117 exposing the second wiring 107 are formed. In this case, the first contact hole 115 is formed in the interlayer insulating layer 105 and the passivation layer 109 , and the second contact hole 117 is formed in the passivation layer 109 .

Thereafter, as shown in FIG. 8G , the halftone region 111b on the first region 109a of the passivation layer is etched through an ashing process to expose the first region 109a of the passivation layer. make it In this case, when the halftone region 111b is etched, a portion of the thickness of the fulltone region 111a of the photoresist layer is also etched.

Next, as shown in FIG. 8H , a portion of the exposed thickness of the first region 109a of the passivation layer is etched using the fulltone region 111a of the photoresist layer as an etch mask. In this case, the first region 109a of the passivation layer has a thickness smaller than the thickness of the second region 109b of the passivation layer. Accordingly, by forming the first region 109a thinner than the second region 109b, the bridge wiring connecting the wirings in different layers can be formed thickly on the first region 109a, so the resistance of the bridge wiring It is possible to improve the high-speed driving and current capability of the display device by reducing , and also improve the aperture ratio and luminance uniformity.

Thereafter, as shown in FIG. 8I , a seed metal layer 121 is formed over the first and second regions 109a and 109b of the passivation layer including the first and second contact holes 115 and 117 . In this case, before forming the seed metal layer 121 , a diffusion barrier layer (not shown) may be formed.

Next, as shown in FIG. 8J , the first and second contact holes 115 and 117 and the first region ( A bridge metal layer 121a filling the 109a is formed. In this way, the bridge metal layer can be formed thickly by electroplating without a separate mask process to form the bridge wiring connecting the wirings in different layers, thereby reducing the resistance of the bridge wiring.

Thereafter, as shown in FIG. 8K , by planarizing the bridge metal layer 121a through a chemical mechanical polishing (CMP) process, the first wiring 103 and the second wiring 107 are electrically connected. By forming the bridge wiring 121b, the bridge wiring forming process of the display device according to an embodiment of the present invention is completed. In this case, the chemical mechanical polishing (CMP) process is performed until the second region 109b of the passivation layer is exposed. In this way, since the bridge wiring can be formed even when the mask photo process of the bridge metal layer is omitted to form the bridge wiring, the manufacturing process of the display device can be simplified.

Accordingly, according to the present invention, by forming thick bridge wires connecting the wires, the resistance of the bridge wires can be reduced, thereby improving the high-speed driving and current capability of the display device, as well as improving the aperture ratio and luminance uniformity.

The present invention can simplify the manufacturing process of the display device because the bridge wiring can be formed using a halftone mask process and a damascene technique even without the mask photo process of the metal layer for forming the bridge wiring. have.

Meanwhile, a bridge wiring structure of an organic light emitting display device according to another embodiment of the present invention will be described below.

9 is a schematic circuit configuration diagram of one pixel of an organic light emitting display device according to another embodiment of the present invention.

10 is a schematic plan view of an organic light emitting display device according to another embodiment of the present invention.

9 and 10, the pixels of the active matrix organic light emitting display device according to another embodiment of the present invention include an organic light emitting diode (OLED), a gate line (GL) and a data line (DL) crossing each other; A switching element Ts, a driving element Td, and a storage capacitor Cst are provided.

The switching element Ts is turned on in response to a scan pulse from the gate wiring GL, thereby conducting a current path between its source electrode and its drain electrode. During the on-time period of the switching device Ts, the data voltage from the data line DL passes through the source electrode and drain electrode of the switching device Ts to the gate electrode and the storage of the driving device Td. is applied to the capacitor Cst.

The driving device Td controls a current flowing through the organic light emitting diode OLED according to a data voltage applied to its gate electrode. In addition, the storage capacitor Cst stores a voltage between the data voltage and the high potential power voltage Vdd and then maintains it constant for one frame period.

The organic light emitting display device configured in this way is driven by current, and therefore a compensation circuit is required for fine current value correction. ) may be needed.

11 is a cross-sectional view taken along line XI-XI of FIG. 10, and is a schematic cross-sectional view of an organic light emitting display device according to another exemplary embodiment of the present invention.

11, in the organic light emitting display device according to another embodiment of the present invention, a buffer layer 203 is formed on a substrate 201 made of an insulating material such as transparent glass or plastic, and polycrystalline silicon or polycrystalline silicon or A first active layer 205 and a second active layer 206 made of an oxide semiconductor are formed.

Although not shown in the drawing, the first active layer 205 includes a first source region (not shown) and a first drain region (not shown) spaced apart from each other, and a first channel region (not shown) interposed therebetween. The second active layer 206 includes a second source region (not shown) and a second drain region (not shown) spaced apart from each other, and a second channel region (not shown) interposed therebetween.

In addition, a gate insulating film 207 made of a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ) is formed on the first active layer 205 and the second active layer 206 , and a first gate electrode is formed thereon. 209 and a second gate electrode 210 are formed.

On the buffer layer 203 including the first and second gate electrodes 209 and 210 and the first and second active layers 205 and 206, an interlayer insulation layer 211 made of a silicon nitride film or a silicon oxide film is formed. is formed

In addition, although not shown in the drawing, a first source region contact exposing a first source region (not shown) and a first drain region (not shown) of the first active layer 205 to the interlayer insulating layer 211 , respectively. A hole (not shown), a first drain region contact hole (not shown), and a second second exposing a second source region (not shown) and a second drain region (not shown) of the second active layer 206 , respectively A source region contact hole (not shown) and a second drain region contact hole (not shown) are formed.

A first source electrode 215a and a first drain electrode 215b connected to a first source region (not shown) and a first drain region (not shown) of the first active layer 205 are formed on the interlayer insulating layer 211 . ), a second source electrode 217a and a second drain electrode 217b connected to a second source region (not shown) and a second drain region (not shown) of the second active layer 206 are formed. has been

Accordingly, the first active layer 205 , the first gate electrode 209 , the first source electrode 215a , and the first drain electrode 215b constitute the first thin film transistor, that is, the switching device Ts. In addition, the second active layer 206 , the second gate electrode 210 , the second source electrode 217a , and the second drain electrode 217b constitute a second thin film transistor, that is, the driving device Td.

In addition, a protective layer 219 is formed on the entire surface of the substrate including the first source electrode 215a and the first drain electrode 215b, and the second source electrode 217a and the second drain electrode 217b. In the passivation layer 219 , a second gate contact hole (not shown; see 225 of 12d ) exposing a portion of the second gate electrode 210 and a first drain contact hole exposing a portion of the first drain electrode 215b ( not shown; see 227 of 12d) is formed. In this case, the first region 219a between the contact holes 225 and 227 of the passivation layer 219 is thinner than the thickness of the second region 219b outside the contact holes 225 and 227 . have Accordingly, by forming the first region 219a thinner than the second region 219b, a bridge interconnection connecting interconnections in different layers can be formed thicker on the first region 219a, so the resistance of the bridge interconnection It is possible to improve the high-speed driving and current capability of the display device by reducing , and also improve the aperture ratio and luminance uniformity.

A bridge wiring 229b for interconnecting the second gate electrode 210 and the first drain electrode 215b through the contact holes 225 and 227 is formed on the passivation layer 219 . In this case, the bridge wiring 229b is filled on the first region 219a of the passivation layer including the contact holes 225 and 227 and has the same layer height as the layer height of the second region 219b of the passivation layer. have Accordingly, the film uniformity of the bridge wiring 229b and the passivation layer is improved, and thus the aperture ratio and the luminance uniformity can also be improved. In addition, the bridge wiring connecting the wirings in different layers can be formed to be thick, so that the resistance of the bridge wiring can be reduced.

A planarization film 231 is formed on the passivation film 219 including the bridge wiring 229b, and the second drain electrode 217b is formed with the passivation film 219 in the planarization film 231. A second drain contact hole (not shown) to be exposed is formed.

An anode electrode 235 electrically connected to the second drain electrode 217b through the second drain contact hole (not shown) is formed on the planarization layer 231 .

A pixel defining layer 237 that separates and defines each light emitting region is formed on the planarization layer 231 . In this case, the pixel defining layer 237 is formed to cover the edge of the anode electrode 235 .

An organic light emitting layer 239 is formed on the anode electrode 235 . The organic light emitting layer 239 may have a multilayer structure including an auxiliary layer for improving the luminous efficiency of the light emitting layer in addition to the light emitting layer emitting light. The auxiliary layer includes an electron transport layer and a hole transport layer for balancing electrons and holes, and an electron injection layer and a hole injection layer for enhancing electron and hole injection.

A cathode electrode 241 is formed on the entire surface of the substrate including the organic light emitting layer 239 and the pixel defining layer 237 . At this time, the cathode electrode 241 receives a common voltage, and is made of a reflective conductive material including calcium (Ca), barium (Ba), magnesium (Mg), aluminum, silver, etc. or a transparent conductive material such as ITO or IZO. can be done

Accordingly, the anode electrode 235 , the organic light emitting layer 239 , and the cathode electrode 241 form an organic light emitting diode 240 (OLED).

As described above, the anode electrode 235 is connected to the second drain electrode 217b of the second switching element Td, so that when a driving voltage is applied to the anode electrode 235 from the second drain electrode 217b, The organic light emitting layer 239 generates light in a predetermined wavelength region in response to electrons and holes injected through the anode electrode 235 and the cathode electrode 241 . That is, the light emitting area of each pixel corresponds to the area in which the organic light emitting layer 239 is formed.

The switching element Ts, the driving element Td, and the anode electrode 235 may be formed to correspond to each of the plurality of pixels, and the cathode electrode 241 may be formed to correspond to the plurality of pixels in common.

Accordingly, according to the present invention, the high-speed driving and current capability of the organic light emitting display device can be improved by reducing the resistance of the bridge wiring by forming the bridge wiring connecting the wirings in different layers to be thick, as well as the aperture ratio and luminance. Uniformity can also be improved.

In the present invention, a method for manufacturing an organic light emitting display device is described below, but it is not limited thereto, and it is also applicable to other display device manufacturing methods including a liquid crystal display device manufacturing method and an electrophoretic display device manufacturing method. do it with

A method of manufacturing an organic light emitting display device according to another embodiment of the present invention configured as described above will be described with reference to FIGS. 12A to 12K .

12A to 12K are cross-sectional views schematically illustrating a method of forming a bridge wiring of a display device according to another exemplary embodiment of the present invention.

As shown in FIG. 12A , a buffer layer 203 is formed on a substrate 201 made of an insulating material such as transparent glass or plastic. At this time, the buffer layer 203 serves to block impurities such as sodium (Na) existing in the substrate 201 from penetrating into the upper layer during the process, and may be formed of a silicon oxide film.

Then, although not shown in the drawings, a semiconductor thin film (not shown) is formed on the substrate 201 on which the buffer layer 203 is formed. The semiconductor thin film may be formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

At this time, the polycrystalline silicon may be formed using various crystallization methods after depositing amorphous silicon on the substrate 201. When an oxide semiconductor is used as a semiconductor thin film, a predetermined heat treatment process may be performed after depositing the oxide semiconductor. have.

Thereafter, the first active layer 205 and the second active layer 207 made of the semiconductor thin film are formed by selectively removing the semiconductor thin film through a photolithography process. At this time, the first active layer 205 and the second active layer 206 are formed to be positioned in a region corresponding to the light blocking layer in order to block the characteristics of the thin film transistor TFT from being affected by external light. .

Next, an insulating layer (not shown) and a first metal layer (not shown) are formed on the substrate 101 on which the first active layer 205 and the second active layer 206 are formed.

The first metal layer is an aluminum-based metal such as aluminum or an aluminum alloy, a silver-based metal such as silver or a silver alloy, a copper-based metal such as copper or a copper alloy, a molybdenum-based metal such as molybdenum or a molybdenum alloy, chromium, tantalum to form a gate wiring , a low-resistance opaque conductive material such as titanium may be used. However, they may have a multilayer film structure comprising two conductive films having different physical properties. One of these conductive layers may be made of a metal having low resistivity, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal, to reduce signal delay or voltage drop. Alternatively, the other conductive layer may be made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with ITO and IZO, for example, molybdenum-based metals, chromium, titanium, tantalum, and the like.

Thereafter, the first gate electrode 209 and the second gate electrode 210 are formed on the first active layer 205 and the second active layer 206 by selectively removing the insulating layer and the first metal layer through a photolithography process. ) to form That is, the first gate electrode 209 is positioned on the first active layer 205 , and the second gate electrode 210 is positioned on the second active layer 206 . In this case, a gate insulating layer 207 made of an insulating layer is formed between the first active layer 205 and the first gate electrode 209 and between the second active layer 206 and the second gate electrode 210 .

In addition, when the gate insulating layer 207, the first gate electrode 209, and the second gate electrode 210 are formed, the first active layer 205 and the second active layer 206 below the gate insulating layer 207, respectively First and second source regions (not shown) and first and second drain regions (not shown) spaced apart from each other are defined, and first and second channel regions (not shown) are defined therebetween. In this case, when an oxide semiconductor is used as the semiconductor thin film, predetermined regions exposed of the first and second active layers 205 and 206 are made conductive by plasma when the insulating film is etched, so that the first and second source regions (not shown) and first and second drain regions (not shown) are formed.

Next, an interlayer insulating film 211 made of a silicon nitride film or a silicon oxide film is formed on the entire surface of the substrate 201 including the first gate electrode 209 and the second gate electrode 210 .

Thereafter, the first source region (not shown) and the first drain region (not shown) of the first active layer 205 are exposed, respectively, by selectively patterning the interlayer insulating layer 211 through a photolithography process. a first source contact hole (not shown) and a first drain contact hole (not shown), and a second source region (not shown) and a second drain region (not shown) for exposing the second active layer 206 , respectively. 2 A source contact hole (not shown) and a second drain contact hole (not shown) are formed.

Next, although not shown in the drawings, a second metal layer (not shown) is formed on the entire surface of the substrate 201 on which the interlayer insulating film 211 is formed, and then the second metal layer is selectively removed through a photolithography process, A first source electrode 215a and a first drain electrode 215b, and a second source electrode 217a and a second drain electrode 217b are respectively formed.

At this time, each of the first source electrode 215a and the first drain electrode 215b passes through a first source contact hole (not shown) and a first drain contact hole (not shown) in a first source region (not shown). and a first drain region (not shown), and each of the second source electrode 217a and the second drain electrode 217b has a second source contact hole (not shown) and a second drain contact hole ( It is electrically connected to the second source region (not shown) and the second drain region (not shown) through the (not shown).

Thereafter, as shown in FIG. 12B , an interlayer insulating layer 211 including the first source electrode 215a and the first drain electrode 215b, and the second source electrode 217a and the second drain electrode 217b. ) to form a protective film 219 on the entire surface. In this case, a silicon nitride film or a silicon oxide film may be used as the protective film 219 .

Next, a photoresist layer 221 is applied on the passivation layer 219 , and a half-ton mask 223 having a diffraction characteristic is disposed on the photoresist layer 211 . In this case, the halftone mask 223 includes a light blocking part 223a, a semi-transmissive part 223b, and a transmissive part 223c.

Thereafter, as shown in FIG. 12C , the photoresist layer 221 is selectively patterned through a photolithography process using the halftone mask 223 to form a full-ton region 221a and a halftone region. A photoresist pattern composed of (half-ton region) 221b is formed. In this case, the halftone region 221b of the photoresist layer has a thickness smaller than the thickness of the fulltone region 221a. Accordingly, by forming the first region 219a thinner than the second region 219b, a bridge interconnection connecting interconnections in different layers can be formed thicker on the first region 219a, so the resistance of the bridge interconnection It is possible to improve the high-speed driving and current capability of the display device by reducing , and also improve the aperture ratio and luminance uniformity.

Next, as shown in FIG. 12D , the protective film 219 and the interlayer insulating film 211 are etched using the full-tone region 221a and the half-tone region 221b of the photosensitive film as an etch mask to form a first wiring, That is, a second gate contact hole 225 exposing the second gate electrode 210 and a first drain contact hole 227 exposing a second wiring, that is, the first drain electrode 215b are formed. In this case, the second gate contact hole 225 is formed in the interlayer insulating layer 211 and the passivation layer 219 , and the first drain contact hole 227 is formed in the passivation layer 219 .

Thereafter, as shown in FIG. 12E , the halftone region 221b on the first region 219a of the passivation layer is etched through an ashing process to expose the first region 219a of the passivation layer. make it In this case, when the halftone region 221b is etched, a portion of the thickness of the fulltone region 221a of the photoresist layer is also etched.

Next, as shown in FIG. 12F , a portion of the exposed thickness of the first region 219a of the passivation layer is etched using the fulltone region 221a of the photoresist layer as an etch mask. In this case, the first region 219a of the passivation layer has a thickness smaller than the thickness of the second region 219b of the passivation layer.

Thereafter, as shown in FIG. 12G , a seed metal layer 229 is formed over the first and second regions 219a and 219b of the passivation layer including the contact holes 225 and 227 . In this case, before forming the seed metal layer 229 , a diffusion barrier layer (not shown) may be formed.

Next, as shown in FIG. 12H , a bridge filling the contact holes 225 and 227 and the first region 219a of the passivation layer by growing the seed metal layer 229 using electroplating. A metal layer 229a is formed.

Thereafter, as shown in FIG. 12I , the second gate electrode 203 and the first drain electrode 215b are electrically connected by planarizing the bridge metal layer 229a through a chemical mechanical polishing (CMP) process. The bridge wiring forming process of the display device according to another exemplary embodiment of the present invention is completed by forming the bridge wiring 229b. In this case, the chemical mechanical polishing (CMP) process is performed until the second region 219b of the passivation layer is exposed.

Next, as shown in FIG. 12J , the upper portion of the passivation layer 219 including the bridge wiring 229b is planarized using an organic insulating material, for example, polyimide or photo-acryl. A film 231 is formed.

Thereafter, as shown in FIG. 4H , the planarization layer 231 is selectively removed through a photolithography process to form a second drain contact hole 233 exposing a portion of the second drain electrode 217b. .

Next, although not shown in the drawings, a conductive layer (not shown) is formed on the entire surface of the planarization layer 231 and then the conductive layer (not shown) is selectively removed through a photolithography process, whereby the second drain An anode electrode 235 electrically connected to the second drain electrode 217b through the contact hole 233 is formed. In this case, a transparent conductive material such as ITO or IZO or a reflective conductive material such as aluminum, silver or an alloy thereof may be used as the conductive film (not shown).

In addition, as the conductive film (not shown), an aluminum-based metal such as aluminum or an aluminum alloy, a silver-based metal such as silver or a silver alloy, a copper-based metal such as copper or a copper alloy, a molybdenum-based metal such as molybdenum or a molybdenum alloy, chromium, tantalum, A low-resistance opaque conductive material such as titanium may be used. However, they may have a multilayer structure including two conductive films having different physical properties. One of these conductive layers may be made of a low resistivity metal, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal, to reduce signal delay or voltage drop. Alternatively, the other conductive layer may be made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with ITO and IZO, for example, molybdenum-based metals, chromium, titanium, tantalum, and the like.

Thereafter, as shown in FIG. 12K , a pixel defining layer 237 defining each pixel area is formed on the planarization layer 231 on which the anode electrode 235 is formed. In this case, the pixel defining layer 237 defines a light emitting region exposing the anode electrode 235 by enclosing the edge of the anode electrode 235 like a weir, and is made of an organic insulating material or an inorganic insulating material. The pixel defining layer 237 may also be made of a photosensitive material including a black pigment. In this case, the pixel defining layer 237 serves as a light blocking member. In addition, the opening 230 may be defined as a light emitting area.

Next, an organic light emitting layer 239 is formed on the anode electrode 235 between the pixel defining layers 237 . In this case, the organic light-emitting layer 239 may be formed of any self-luminous material such as a light-emitting organic material.

Thereafter, by forming the cathode electrode 241 on the entire surface of the substrate 201 including the organic light emitting layer 239 and the pixel defining layer 237 , the organic light emitting display device manufacturing process according to another embodiment of the present invention is completed. do. At this time, the cathode electrode 241 is applied with a common voltage, and is formed of a reflective conductive material including calcium, barium, magnesium, aluminum, silver, or the like, or a transparent conductive material such as ITO or IZO.

Next, the anode electrode 235 , the cathode electrode 241 , and the organic light emitting layer 239 interposed between the electrodes 235 and 241 form an organic light emitting diode 140 (OLED).

As described above, according to the present invention, by forming thick bridge wires connecting the wires, the resistance of the bridge wires can be reduced, thereby improving the high-speed driving and current capability of the display device, as well as improving the aperture ratio and luminance uniformity.

The present invention can simplify the manufacturing process of the display device because the bridge wiring can be formed using a halftone mask process and a damascene technique even without the mask photo process of the metal layer for forming the bridge wiring. have.

Although the embodiments have been described with reference to the drawings above, the present invention is not limited thereto.

Terms such as "include", "comprise" or "have" described above mean that the corresponding component may be embedded unless otherwise stated, so it does not exclude other components. It should be construed as being able to further include other components. All terms, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs, unless otherwise defined. Terms commonly used, such as those defined in the dictionary, should be interpreted as being consistent with the contextual meaning of the related art, and are not interpreted in an ideal or excessively formal meaning unless explicitly defined in the present invention.

The above description is merely illustrative of the technical spirit of the present invention, and various modifications and variations will be possible without departing from the essential characteristics of the present invention by those skilled in the art to which the present invention pertains. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

103: first wiring 105: interlayer insulating film
107: second wiring 109: protective film
121b: bridge wiring

Claims (12)

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a gate line and a data line disposed on the substrate and intersecting each other;
a first thin film transistor disposed on the substrate and including a first active layer, a first gate electrode, and a first source/drain electrode;
a second thin film transistor disposed on the substrate and including a second active layer, a second gate electrode, and a second source/drain electrode;
a passivation layer formed on the first thin film transistor and the second thin film transistor and having a first contact hole and a second contact hole exposing the first drain electrode and the second gate electrode, respectively;
a bridge line filling the first and second contact holes and a passivation layer therebetween to connect the first drain electrode and the second gate electrode;
a planarization layer disposed on the passivation layer and exposing the second drain electrode;
a first electrode disposed on the planarization layer and connected to the second drain electrode;
an organic light emitting layer disposed on the first electrode; and
a second electrode disposed on the organic light emitting layer;
the first source/drain electrode and the second source/drain electrode are disposed adjacent to the gate line and parallel to the gate line;
the second contact hole is disposed between the second source electrode and the second drain electrode to overlap the second active layer and the second gate electrode;
The bridge wiring is disposed in parallel with the second source electrode to overlap a central portion of the second source electrode. 5. The method of claim 4,
A first region of the passivation layer between the first and second contact holes has a thickness smaller than that of a second region of the passivation layer outside the first and second contact holes,
and the first region completely overlaps the bridge line and is disposed adjacent to the gate line and parallel to the gate line. The organic light emitting display device of claim 5 , wherein a top surface of the bridge wiring is on the same plane as a top surface of the second region of the passivation layer.
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