KR102332357B1 - Thermoelectric moudule and device using the same - Google Patents

Abstract

Embodiments of the present invention relate to a thermoelectric element and a thermoelectric module used for cooling, and by forming different areas of the first substrate and the second substrate to increase heat dissipation efficiency, the thermoelectric module can be thinned. .

Description

Thermoelectric module and thermal conversion device including same

Embodiments of the present invention relate to a thermoelectric module.

In the method of manufacturing a thermoelectric element, the material in the form of an ingot is heat-treated, crushed into a powder (Ball Mill), sieved to a fine size, and then again sintered to the size of the required thermoelectric element. It is manufactured through a cutting process. In the process of manufacturing such a bulk type thermoelectric element, a large portion of material loss occurs during cutting after sintering of the powder. There was a problem in that it was difficult to apply to products requiring slimming.

In particular, in the case of a thermoelectric module using such an existing thermoelectric element, equipment such as a heat sink and a fan must be installed at the bottom, and the size and thickness of the thermoelectric module increase rapidly. In order to apply it, there is also the problem of being subject to spatial restrictions.

Embodiments of the present invention are intended to solve the above-described problem, and by forming different areas of the first substrate and the second substrate to increase heat dissipation efficiency, the thermoelectric module can be thinned, and in particular, the first When the area of the substrate and the second substrate are formed differently, the area of the substrate on the heat dissipation side is increased to increase the heat transfer rate, thereby removing the heat sink to provide a thermoelectric module that can reduce the size and thickness of the cooling device. do.

A thermoelectric module according to an embodiment of the present invention includes a first substrate; a first dielectric layer disposed on the first substrate; a first electrode layer disposed on the first dielectric layer; at least one unit cell disposed on the first electrode layer and including a P-type semiconductor device and an N-type semiconductor device electrically connected to each other; a second electrode layer disposed on the P-type semiconductor device and the N-type semiconductor device; a second dielectric layer disposed on the second electrode layer; a second substrate disposed on the second dielectric layer, wherein the first substrate and the second substrate face each other, the first substrate and the second substrate are metal substrates, the first substrate and the second substrate The volumes of the two substrates are different from each other, the area of the second substrate is larger than the area of the first substrate, and the area ratio of the first substrate and the second substrate is 1:1.2 to 5.

A volume of the second substrate may be greater than a volume of the first substrate.

The thickness of the first substrate and the second substrate may be different from each other.

A thickness of the second substrate may be greater than a thickness of the first substrate.

An uneven pattern may be formed on one surface of the second substrate.

The concave-convex pattern may be a plurality of concavo-convex patterns disposed between the second substrate and the second dielectric layer.

The one surface of the second substrate may be disposed toward the P-type semiconductor device and the N-type semiconductor device.

Thermal conductivity of the first dielectric layer and the second dielectric layer may be 5 to 10 W/mK.

The first substrate and the second substrate may include at least one of Cu, a Cu alloy, and a Cu-Al alloy.

A thickness of the first dielectric layer and the second dielectric layer may be 0.01 mm to 0.1 mm.

The first electrode layer and the second electrode layer may include at least one of Cu, Ag, and Ni.

The thickness of the first electrode layer and the second electrode layer may be 0.01 to 0.3 mm.

The P-type semiconductor device and the N-type semiconductor device may be a mixture in which Bi or Te is mixed with a BiTe-based main raw material.

The height of the P-type semiconductor device and the N-type semiconductor device may be 0.01 mm to 0.5 mm.

A volume of the P-type semiconductor device may be different from a volume of the N-type semiconductor device.

A volume of the N-type semiconductor device may be greater than a volume of the P-type semiconductor device.

A thermoelectric module according to another embodiment of the present invention includes a first substrate; a first dielectric layer disposed on the first substrate; a first electrode layer disposed on the first dielectric layer; at least one unit cell disposed on the first electrode layer and including a P-type semiconductor device and an N-type semiconductor device electrically connected to each other; a second electrode layer disposed on the P-type semiconductor device and the N-type semiconductor device; a second dielectric layer disposed on the second electrode layer; a second substrate disposed on the second dielectric layer, wherein the first substrate and the second substrate face each other, the first substrate and the second substrate are metal substrates, the first substrate and the second substrate The volumes of the two substrates are different from each other, the areas of the first substrate and the second substrate are different from each other, and at least one of the P-type semiconductor device and the N-type semiconductor device includes two or more unit members stacked on each other, each The unit member includes a substrate and a semiconductor layer on the substrate, a conductive layer is disposed between adjacent unit members, and each unit member is disposed parallel to the first substrate and the second substrate.

According to an embodiment of the present invention, the area of the first substrate and the second substrate are formed differently to increase heat dissipation efficiency, so that the thermoelectric module can be made thinner.

In particular, when the area of the first substrate and the second substrate are formed differently, the heat transfer rate is increased by forming a large area of the substrate on the heat dissipation side, thereby eliminating the heat sink to realize the miniaturization and thinness of the cooling device. do.

In addition, according to an embodiment of the present invention, by stacking unit members including a semiconductor layer on a sheet substrate to implement a thermoelectric element, the thermal conductivity is lowered and the electrical conductivity is increased, so that the cooling capacity (Qc) and the temperature change rate (ΔT) ) can provide a thermoelectric element and a thermoelectric module that are remarkably improved.

In addition, it is possible to maximize the electrical conductivity by including a conductive pattern layer between the unit members of the stacked structure, and there is an effect that the thickness is significantly reduced compared to the overall bulk-type thermoelectric element.

1 is a conceptual diagram illustrating a main part of a thermoelectric module according to an embodiment of the present invention.
2 is an exemplary diagram illustrating an embodiment of a thermoelectric module according to an embodiment of the present invention.
3 is an exemplary view showing an embodiment of a heat dissipation pattern according to an embodiment of the present invention.
4 and 5 illustrate an embodiment of a thermoelectric element constituting a thermoelectric module according to an embodiment of the present invention.
6 shows various modifications of the conductive layer (C) according to an embodiment of the present invention.

Hereinafter, the configuration and operation according to the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same components are given the same reference, regardless of the reference numerals, and redundant description thereof will be omitted. Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

1 is a conceptual diagram illustrating a main part of a thermoelectric module according to an embodiment of the present invention, and FIG. 2 is an exemplary view showing an embodiment of a thermoelectric module according to an embodiment of the present invention to which the thermoelectric module of FIG. 1 is applied.

1 and 2 , in the thermoelectric module according to an embodiment of the present invention, a first substrate 140 and a second substrate 150, the first substrate 140 and the second substrate 150 are opposed to each other. at least one unit cell including a second semiconductor device 130 electrically connected to the first semiconductor device 120 therebetween, and in particular, the volumes of the first substrate and the second substrate are different from each other. to allow it to be formed. In an embodiment of the present invention, 'volume' is defined as an internal volume formed by the outer circumferential surface of the substrate.

In this case, in the case of the thermoelectric element constituting the unit cell, one side may be composed of a P-type semiconductor as the first semiconductor element 120 and an N-type semiconductor as the second semiconductor element 130 , and the first semiconductor and the second semiconductor The semiconductor is connected to the metal electrodes 160a and 160b, and a plurality of such structures are formed, and the Peltier effect is realized by circuit lines 181 and 182 through which a current is supplied to the semiconductor device through the electrodes.

In particular, in the present invention, the area of the second substrate 150 forming the heat dissipation area (Hot side) can be formed wider than the area of the first substrate 140 forming the cooling area (Cold side) by the Peltier effect, It is possible to remove the heat sink in the conventional thermoelectric module by increasing the thermal conductivity and heat dissipation efficiency.

Specifically, for the first substrate 140 and the second substrate 150, an insulating substrate, such as an alumina substrate, may be used in the case of a thermoelectric module for cooling, or a metal substrate may be used in the embodiment of the present invention. It is possible to realize heat dissipation efficiency and thickness reduction. Of course, in the case of forming a metal substrate, dielectric layers 170a and 170b are further included between the electrode layers 160a and 160b formed on the first and second substrates 140 and 150 as shown. desirable.

In the case of a metal substrate, Cu or Cu alloy, Cu-Al alloy, etc. can be applied, and the thickness that can be reduced in thickness can be formed in the range of 0.1mm to 0.5mm.

In the embodiment according to the present invention, the area of the second substrate 150 may be formed in a range of 1.2 to 5 times the area of the first substrate 140 to form different volumes. Also in the drawing shown in FIG. 1 , the width b1 of the first substrate 140 is narrower than the width b2 of the second substrate 150 , and in this case, the areas of the substrates of the same thickness are formed to be different from each other. volume will change.

In this case, when the area of the second substrate 150 is formed to be less than 1.2 times that of the first substrate 140, there is no significant difference from the existing heat conduction efficiency, so there is no meaning of thinning, and when it exceeds 5 times, the thermoelectric module It is difficult to maintain the shape (eg, opposing structures facing each other), and the heat transfer efficiency is significantly reduced.

In addition, in the case of the second substrate 150, as shown in FIG. 3, heat dissipation patterns 151 and 152, such as uneven patterns, are formed on the surface of the second substrate to maximize the heat dissipation characteristics of the second substrate. Thus, it is possible to secure more efficient heat dissipation characteristics even though the configuration of the existing heat sink is deleted. In this case, the heat dissipation pattern may be formed on one or both of the surfaces of the second substrate. In particular, when the heat dissipation pattern is formed on a surface in contact with the first and second semiconductor devices, heat dissipation characteristics and bonding characteristics between the thermoelectric device and the substrate may be improved. The shape of the heat dissipation pattern is not limited to that shown in FIG. 3 and may be modified into various shapes and structures.

In addition, the thickness a1 of the first substrate 140 is formed thinner than the thickness a2 of the second substrate 150 to facilitate the inflow of heat from the cold sied and to increase the heat transfer rate. can

In addition, in the case of the dielectric layers 170a and 170b, as a dielectric material having high heat dissipation performance, considering the thermal conductivity of the thermoelectric module for cooling, a material having a thermal conductivity of 5 to 10 W/mK is used, and the thickness is 0.01 mm to 0.1 It can be formed in the range of mm.

The electrode layers 160a and 160b electrically connect the first semiconductor element and the second semiconductor element using electrode materials such as Cu, Ag, and Ni, and when a plurality of the illustrated unit cells are connected (see FIG. 2 ), they are adjacent. to form an electrical connection with the unit cell. The thickness of the electrode layer may be formed in the range of 0.01mm to 0.3mm.

Hereinafter, various types of thermoelectric elements that can be applied to a thermoelectric module according to an embodiment of the present invention will be described.

1) A semiconductor device formed in a bulk type

The first semiconductor device 120 and the second semiconductor device 130 according to the present invention may be a semiconductor device formed in a bulk type by applying a P-type semiconductor or an N-type semiconductor material. The bulk type refers to a structure formed by pulverizing an ingot, which is a semiconductor material, followed by a miniaturization ball-mill process, and then cutting the sintered structure. Such a bulk-type device may be formed as one integrated structure.

Such a P-type semiconductor or N-type semiconductor material is that the N-type semiconductor device is selenium (Se), nickel (Ni), aluminum (Al), copper (Cu), silver (Ag), lead (Pb), boron (B) ), gallium (Ga), tellurium (Te), bismuth (Bi), and a main raw material consisting of bismuth telluride (BiTe) including indium (In), and 0.001 to 1.0 wt% of the total weight of the main raw material It can be formed using a mixture of Bi or Te corresponding to . For example, the main raw material may be a Bi-Se-Te material, and Bi or Te may be formed by adding a weight corresponding to 00.001 to 1.0 wt% of the total weight of Bi-Se-Te. That is, Bi When the weight of -Se-Te is 100 g, it is preferable to add Bi or Te to be added in the range of 0.001 g to 1.0 g. As described above, the weight range of the material added to the above-mentioned main raw material is significant in that, outside the range of 0.001 wt % to 0.1 wt %, the thermal conductivity does not decrease and the electrical conductivity cannot be expected to improve the ZT value. have

The P-type semiconductor material is antimony (Sb), nickel (Ni), aluminum (Al), copper (Cu), silver (Ag), lead (Pb), boron (B), gallium (Ga), tellurium ( Te), bismuth (Bi), a mixture of a main raw material consisting of bismuth telluride (BiTe) including indium (In), and Bi or Te corresponding to 0.001 to 1.0 wt% of the total weight of the main raw material It is preferable to form using . For example, the main raw material may be a Bi-Sb-Te material, and Bi or Te may be formed by further adding a weight corresponding to 0.001 to 1.0 wt% of the total weight of Bi-Sb-Te. That is, when 100 g of Bi-Sb-Te is added, the additionally mixed Bi or Te may be added in the range of 0.001 g to 1 g. The weight range of the material added to the above-mentioned main raw material is significant in that, outside the range of 0.001 wt% to 0.1 wt%, the thermal conductivity does not decrease and the electrical conductivity does not decrease, so that the improvement of the ZT value cannot be expected.

2) Unit thermoelectric element with stacked structure

In another embodiment of the present invention, the structure of the above-described semiconductor device may be implemented as a structure of a stacked structure instead of a bulk type structure, thereby making it possible to further improve the thickness and cooling efficiency.

Specifically, the structure of the first semiconductor device 120 and the second semiconductor device 130 in FIG. 1 is formed as a unit member in which a plurality of structures coated with a semiconductor material are stacked on a sheet-shaped substrate, and then cut. It is possible to prevent material loss and improve electrical conductivity.

Referring to FIG. 4 in this regard, FIG. 4 is a conceptual diagram illustrating a process for manufacturing the unit member having the above-described stacked structure. According to FIG. 4 , a material including a semiconductor material is prepared in the form of a paste, and the paste is applied on a substrate 111 such as a sheet or film to form a semiconductor layer 112 to form one unit member 110 . to form The unit member 110 is formed by stacking a plurality of unit members 100a, 100b, and 100c as shown in FIG. 2 to form a stacked structure, and then cutting the stacked structure to form a unit thermoelectric element 120 . That is, the unit thermoelectric element 120 according to the present invention may be formed in a structure in which a plurality of unit members 110 in which a semiconductor layer 112 is laminated on a substrate 111 are laminated.

In the above-described process, the process of applying the semiconductor paste on the substrate 111 may be implemented using various methods, for example, tape casting, that is, a very fine semiconductor material powder in an aqueous or non-aqueous solvent ( solvent) and a binder, plasticizer, dispersant, defoamer, and surfactant to prepare a slurry, and then use a moving blade or moving carrier It can be implemented as a process of molding according to a desired purpose with a constant thickness above. In this case, the thickness of the substrate can use a film or sheet in the range of 10um to 100um, and the applied semiconductor material is the P-type material and the N-type material for manufacturing the bulk-type device described above. Of course.

The process of arranging and stacking the unit members 110 in multiple layers can be formed into a stacked structure by pressing at a temperature of 50° C. to 250° C., and in the embodiment of the present invention, the number of stacking of these unit members 110 is 2 It can be done in the range of ~50. Thereafter, a cutting process may be performed to a desired shape and size, and a sintering process may be added.

The unit thermoelectric element formed by stacking a plurality of unit members 110 manufactured according to the above-described process can ensure uniformity in thickness and shape size. That is, the conventional bulk-shaped thermoelectric element cuts the sintered bulk structure after ingot pulverization and miniaturization ball-mill processes. It is difficult to cut to one size, and there was a problem in that it was difficult to reduce the thickness due to the thickness of 3 mm to 5 mm. There is almost no material loss, the material has a uniform thickness, so the uniformity of the material can be secured, and the thickness of the entire unit thermoelectric element can be reduced to 1.5 mm or less, and it can be used in various shapes. application becomes possible.

In particular, in the manufacturing process of the unit thermoelectric element according to the embodiment of the present invention, a process of forming a conductive layer on the surface of each unit member 110 during the process of forming the stacked structure of the unit member 110 is further included. can make it happen

That is, the conductive layer having the structure of FIG. 5 may be formed between the unit members of the stacked structure of FIG. 4C . The conductive layer may be formed on the opposite surface of the substrate on which the semiconductor layer is formed. This can increase the electrical conductivity compared to the case where the entire surface is applied, and at the same time improve the bonding force between each unit member, and realize the advantage of lowering the thermal conductivity. That is, what is shown in FIG. 5 shows various modifications of the conductive layer (C) according to the embodiment of the present invention, and the pattern in which the surface of the unit member is exposed is shown in FIGS. 5(a) and (b). As shown in, a mesh-type structure including a closed opening pattern (c ₁ , c _{2 ) or an open opening pattern (c 3} , c ₄ ) as shown in (c) and (d) of FIG. 5 ) It can be designed by variously deforming into a line type including The above conductive layer not only increases the adhesive force between the unit members inside the unit thermoelectric element formed in a stacked structure of unit members, but also lowers the thermal conductivity between the unit members and improves the electrical conductivity. The cooling capacity (Qc) and ΔT (°C) are improved compared to the bulk type thermoelectric element, and in particular, the power factor is increased by 1.5 times, that is, the electrical conductivity is increased by 1.5 times. The increase in electrical conductivity is directly related to the improvement of thermoelectric efficiency, and thus the cooling efficiency is improved. The conductive layer may be formed of a metal material, and any metal-based electrode material made of Cu, Ag, Ni, or the like may be applied.

When the unit thermoelectric element of the stacked structure described above in Fig. 4 is applied to the thermoelectric module shown in Figs. 1 and 2, that is, between the first substrate 140 and the second substrate 150 in the embodiment of the present invention. When a thermoelectric module according to the following is disposed and a thermoelectric module is implemented as a unit cell having a structure including an electrode layer and a dielectric layer, the overall thickness (Th) can be formed in the range of 1.mm to 1.5mm. It becomes possible to realize a significant reduction in thickness compared to that used.

In addition, as shown in FIG. 6 , the thermoelectric elements 120 and 130 described above in FIG. 4 are horizontally arranged in an upper direction (X) and a lower direction (Y), as shown in FIG. 6A . Thus, a thermoelectric module can be formed in a structure in which the first and second substrates and the semiconductor layer and the surfaces of the substrate are adjacent to each other, but as shown in (b), the thermoelectric element itself is vertically erected, A structure in which a side portion of the device is disposed adjacent to the first and second substrates is also possible. In such a structure, the distal end of the conductive layer is exposed on the side surface than in a horizontally arranged structure, and it is possible to lower the heat conduction efficiency in the vertical direction and improve the electric conductivity characteristics, thereby further increasing the cooling efficiency.

As described above, in the thermoelectric element applied to the thermoelectric module of the present invention that can be implemented in various embodiments, the shape and size of the first semiconductor element and the second semiconductor element that form a unit cell and face each other are the same. However, in this case, considering that the electrical conductivity of the P-type semiconductor device and the electrical conductivity characteristics of the N-type semiconductor device are different from each other and act as a factor impeding the cooling efficiency, one volume of the other semiconductor device facing each other is It is also possible to form different from the volume to improve the cooling performance. In other words, differently forming the volumes of the semiconductor elements of the unit cells disposed opposite to each other can form a largely different overall shape, widen the diameter of one of the cross-sections in a semiconductor element having the same height, or have the same shape. In a semiconductor device, it is possible to implement a method of varying the height or diameter of the cross section. In particular, the diameter of the N-type semiconductor device can be formed to be larger than that of the P-type semiconductor device to increase the volume, thereby improving the thermoelectric efficiency.

The thermoelectric element of various structures and the thermoelectric module including the same according to an embodiment of the present invention described above take heat from a medium such as water or liquid according to the characteristics of the heat generating and heat absorbing portion on the surface of the substrate at the upper and lower portions of the unit cell. It can be used to implement cooling or to heat by transferring heat to a specific medium. That is, in the thermoelectric module of various embodiments of the present invention, the configuration of a cooling device implemented by improving cooling efficiency is described as an embodiment, but the substrate on the opposite side of which cooling is performed is used for heating a medium using heat generation characteristics. It can be applied to the device being used. That is, it can be applied to equipment that implements cooling and heating functions in one device at the same time.

In the detailed description of the present invention as described above, specific embodiments have been described. However, various modifications are possible without departing from the scope of the present invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, and should be defined by the claims as well as the claims and equivalents.

110: unit member
111: description
112: semiconductor layer
120: unit thermoelectric element
130: unit thermoelectric element
140: first substrate
150: second substrate
160a, 160b: electrode layer
170a, 170b: dielectric layer
181, 182: circuit line

Claims (18)

a first metal substrate;
a first insulating layer disposed on the first metal substrate;
a first electrode layer disposed on the first insulating layer;
a semiconductor device disposed on the first electrode layer;
a second electrode layer disposed on the semiconductor device;
a second insulating layer disposed on the second electrode layer; and
a second metal substrate disposed on the second insulating layer;
An area of the first surface of the first metal substrate facing the first insulating layer is larger than an area of the second surface of the second metal substrate facing the second insulating layer,
A horizontal width of the first insulating layer parallel to the first surface is less than or equal to a horizontal width of the second insulating layer parallel to the second surface,
The thickness of the second metal substrate is smaller than the thickness of the first metal substrate,
A thermoelectric module in which a plurality of concave-convex patterns are formed on the first metal substrate, and at least a portion of the plurality of concavo-convex patterns has a polygonal shape with curved corners. delete delete The method of claim 1
The plurality of concave-convex patterns are formed on the first surface, and the concave-convex patterns are in direct contact with the first insulating layer. 5. The method of claim 4,
The semiconductor device includes a plurality of semiconductor devices disposed to be spaced apart from each other,
At least a portion of the plurality of concavo-convex patterns is disposed between the plurality of semiconductor devices. delete According to claim 1,
The thermoelectric module has a thermal conductivity of 5 to 10 W/mK of the first insulating layer and the second insulating layer. According to claim 1,
wherein the first metal substrate and the second metal substrate include at least one of Cu, a Cu alloy, and a Cu-Al alloy. According to claim 1,
A thermoelectric module having a thickness of 0.01 mm to 0.1 mm, respectively, of the first insulating layer and the second insulating layer. According to claim 1,
The first electrode layer and the second electrode layer include at least one of Cu, Ag, and Ni. 11. The method of claim 10,
The first electrode layer and the second electrode layer have a thickness of 0.01 to 0.3 mm. According to claim 1,
The semiconductor device is
A thermoelectric module that is a mixture of Bi or Te with BiTe-based main raw material. 13. The method of claim 12,
The height of the semiconductor element is 0.01 mm to 0.5 mm thermoelectric module. According to claim 1,
The semiconductor device includes a P-type semiconductor device and an N-type semiconductor device,
A volume of the P-type semiconductor device and a volume of the N-type semiconductor device are different from each other. 15. The method of claim 14,
A volume of the N-type semiconductor device is greater than a volume of the P-type semiconductor device. delete According to claim 1,
The size of some of the plurality of uneven patterns is different from the size of some of the other uneven patterns. 18. The method of claim 17,
A thermoelectric module in which the partial concave-convex pattern and the other partial concave-convex pattern are alternately disposed along a predetermined direction.

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