KR102291397B1 - Reverse engineering system of PCB and method thereof - Google Patents

Abstract

Provided is a printed circuit board reverse engineering system including: an image photographing part photographing ten first images about a plane, a bottom side, a front upper side, a front lower side, a rear upper side, a rear lower side, a left upper side, a left lower side, a right upper side, and a left lower side of a printed circuit board having a guide hole, multiple layers of circuit patterns, and a via hole; a coordinate value input part creating a second image by inputting a three-dimensional coordinate value into the ten first images photographed by the image photographing part, with respect to a position of the guide hole; a magnification adjustment part adjusting the magnification of ten second images, into which the coordinate value has been inputted, based on the coordinate value to create a third image in which the ten second images have the same magnification; a circuit pattern separation part identifying the circuit patterns of the printed circuit board by number of layers based on ten third images, of which the magnification has been adjusted, and separating the circuit patterns to create a fourth image on each plane by layer from which the circuit patterns have been separated; a via hole separation part identifying the position and depth of the via hole of the printed circuit board based on the ten third images, of which the magnification has been adjusted, and separating the via hole to create fifth images for the plane, the bottom side, the rear side, the left side and the right side from which the via hole has been separated; and an image conversion part providing drawing data by matching and overlapping the fourth image, from which the circuit patterns have been separated, with the fifth image, from which the via hole has been separated. Therefore, the present invention is capable of enabling accurate reverse engineering on circuit patterns of a printed circuit board.

Description

Printed circuit board reverse engineering system and method thereof

The present invention relates to a printed circuit board reverse engineering system and method, and more particularly, to a top surface, a fixed surface, a top surface, a rear surface, a top surface, a top surface, a bottom surface, a left surface, a right surface and a right surface as well as the flat surface and the bottom surface of the printed circuit board. Reverse engineering of a printed circuit board that can accurately reverse engineer a circuit pattern of a printed circuit board by accurately identifying the number of stacked circuit patterns of a printed circuit board and the location of a via hole between circuit patterns based on each image It relates to a system and a method therefor.

In general, reverse engineering is a series of operations of acquiring digitized information from the shape of an actual product that cannot be manufactured due to the absence of design data and generating design data so that a product that performs the same function can be manufactured based on this information.

In particular, reverse engineering of printed circuit boards (PCBs) is widely used when printed circuit boards used in military equipment and weapon systems become obsolete due to long-term use or need replacement due to malfunction.

This is to respond to a situation in which the operation of the relevant equipment and weapon system must be stopped or completely disposed of when it is impossible to replace the printed circuit board due to difficulties in supplying the same printed circuit board due to problems such as bankruptcy, closure of the printed circuit board manufacturer, or discontinuation of parts. am.

The printed circuit board includes a part hole for fixing an electronic part and a wiring (pattern) which is a thin copper film connected to enable the flow of an electric signal between the parts.

Reverse engineering of a printed circuit board may cause problems such as insufficient current capacity, signal interference, signal reflection, electromagnetic noise, etc. It is important to accurately restore the pattern in that it can be

In the prior art, the pattern of the printed circuit board was checked manually by the operator, but this manual operation made it difficult to accurately identify the pattern due to the insulating ink and recognition mark applied on the pattern to prevent conduction with other conductors. It is difficult, and in the case of a printed circuit board including a multi-layer pattern, it is difficult to accurately separate and identify the overlapping layer-by-layer pattern.

Accordingly, although the elements inhibiting analysis of the printed circuit board are removed by methods such as removing the adhesive using chemicals or forcibly separating the multilayer printed circuit board using a mechanical device, these methods damage or deform the configuration of the printed circuit board. When generating design data, the error rate is high, and it may take a lot of time and money to analyze the printed circuit board. In addition, the multi-layer printed circuit board separated by layers by a mechanical device has a high risk in that it cannot be reused.

On the other hand, in order to solve the above problems, in Patent Publication No. 10-2015-0027929 No., etc., after X-ray imaging of the plane and bottom of the printed circuit board, overlapping and correcting, the pattern of the multilayer is identified and separated, and A printed circuit board reverse engineering apparatus for converting drawing data has been disclosed.

However, since the conventional printed circuit board reverse engineering device simply takes pictures of the plane and the bottom surface of the printed circuit board, when the circuit pattern on the printed circuit board is composed of four layers, for example, the first floor and the bottom surface located on the plane Separation and recognition of the circuit pattern of the 4th layer located in the There is a problem in that it is difficult to accurately recognize the number of stacked circuit patterns.

In addition, when the circuit patterns of the second and third layers are partially electrically connected to the via hole, it is difficult to accurately grasp the plane and the bottom of the printed circuit board by X-ray imaging as described above. Accordingly, there is a problem in that the extraction accuracy of the circuit pattern is lowered.

Therefore, it is an object of the present invention to take images of not only the flat surface and the bottom surface of the printed circuit board, but also the top surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface. An object of the present invention is to provide a printed circuit board reverse engineering system and method capable of accurately reverse engineering the circuit pattern of the printed circuit board by accurately identifying the number of stacked circuit patterns and the position of the via hole between the circuit patterns.

On the other hand, the object of the present invention is not limited to the above-mentioned objects, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

According to the present invention, ten first for the flat surface, bottom surface, top surface, fixed surface, upper surface, lower surface, upper left surface, left lower surface, upper right surface and right lower surface of a printed circuit board having a guide hole and a multi-layered circuit pattern and via hole an image recording unit that takes an image; a coordinate value input unit for generating a second image by inputting three-dimensional coordinate values based on the position of the guide hole in the ten first images photographed by the image capturing unit; a magnification unit adjusting the magnification of the ten second images to which the coordinate values are input based on the coordinate values to generate a third image in which all ten second images have the same magnification; a circuit pattern separating unit that identifies and separates the circuit patterns of the printed circuit board by the number of stacks based on the ten third images whose magnification is adjusted to generate a fourth image in the plane of each layer from which the circuit patterns are separated; Via hole that identifies the position and depth of the via hole of the printed circuit board based on the 10 third images with the magnification adjusted and separates each to create a fifth image in the plane, bottom, front, back, left and right surfaces in which the via holes are separated. separator; And there is provided a printed circuit board reverse engineering system including an image conversion unit for providing drawing data by matching and overlapping the fourth image in which the circuit pattern is separated and the fifth image in which the via hole is separated.

Here, the image photographing unit, the plane and the bottom of the printed circuit board are taken at an angle of 0 degrees with respect to the center of the printed circuit board, the top surface of the printed circuit board, if it is determined, if it is the upper surface, the lower surface, the upper left side, the left side, the right side , it is preferable to photograph the right side at an angle of 2 degrees to 5 degrees with respect to the center of the printed circuit board, respectively.

In addition, the circuit pattern separation unit compares and contrasts the third images of the top surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface based on the third image of the flat surface and the bottom surface, and the brightness between the circuit patterns It is preferable to generate the shape of the pattern for each layer of the circuit pattern as a fourth image viewed from a plane through contrast.

In addition, the via hole separation unit compares and contrasts the third images of the top surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface based on the third image of the plane and the bottom surface, while comparing and contrasting the third images between the via hole and the circuit patterns. It is preferable to generate the position and depth of the via hole that partially conducts the circuit pattern for each layer through the brightness contrast as a fifth image viewed from the plane, bottom, front, back, left and right sides.

On the other hand, according to the present invention, 10 pieces for the flat surface, the bottom surface, the top surface, the front surface, the upper surface, the rear surface, the upper left surface, the left surface, the right surface and the right surface of a printed circuit board having a guide hole and a multi-layered circuit pattern and via holes photographing a first image; generating a second image by inputting a three-dimensional coordinate value based on the position of the guide hole in the ten first images photographed by the image capturing unit; generating a third image in which all ten second images have the same magnification by adjusting the magnification of the ten second images to which the coordinate values are input based on the coordinate values; identifying and separating circuit patterns of the printed circuit board by the number of stacks on the basis of the ten third images whose magnification is adjusted, and generating a fourth image in the plane of each layer from which the circuit patterns are separated; Identifying the position and depth of the via hole of the printed circuit board based on the ten third images whose magnification is adjusted and separating each to generate a fifth image in the plane, bottom, front, back, left and right surfaces in which the via holes are separated. Wow; There is provided a printed circuit board reverse engineering method comprising the step of providing drawing data by matching and overlapping a fourth image in which a circuit pattern is separated and a fifth image in which a via hole is separated.

Therefore, according to the present invention, after taking images of not only the flat surface and the bottom surface of the printed circuit board, but also the top surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface, based on each image, the It is possible to accurately reverse engineer the circuit pattern of the printed circuit board by accurately grasping the number of stacked circuit patterns and the position of the via hole between the circuit patterns.

On the other hand, the effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a view showing the configuration of a printed circuit board reverse engineering system according to a preferred embodiment of the present invention;
Figure 2 is a view showing the state of the circuit pattern stacking and via holes of the printed circuit board in the reverse engineering system of Figure 1;
3A and 3B are views showing a first image in the reverse engineering system of FIG. 1;
Figure 4 is a view showing a fourth image in the reverse engineering system of Figure 1;
Figure 5 is a view showing a fifth image in the reverse engineering system of Figure 1; and
6 is a view showing drawing data in the reverse engineering system of FIG. 1 .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, as shown in FIGS. 1 to 6 , a printed circuit board reverse engineering system according to a preferred embodiment of the present invention is printed having a guide hole 10 , a multilayer circuit pattern 20 , and a via hole 30 . An image projection unit 110 for photographing ten first images 1 for the flat surface, the bottom surface, the top surface, the front surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface of the circuit board 40, The X-axis, Y-axis, and Z-axis lengths are measured based on the position of the guide hole 10 in the ten first images 1 taken by the image capturing unit 110 and input as three-dimensional coordinate values to input the second The coordinate value input unit 120 for generating an image, the ten second images to which the three-dimensional coordinate values are input, the magnification is adjusted based on the coordinate values, and the ten second images are all magnified to generate a third image having the same magnification. The adjustment unit 130 identifies and separates the circuit patterns 20 of the printed circuit board 40 by the number of stacks on the basis of the ten third images whose magnification is adjusted, and separates the circuit patterns 20 in the plane of each layer from which the circuit patterns 20 are separated. Based on the circuit pattern separating unit 140 generating the fourth image 4 and the ten third images whose magnification is adjusted, the position and depth of the via hole 30 of the printed circuit board 40 are identified and separated, respectively, to separate the via hole. A fourth image 4 in which the via hole separation unit 150 and the circuit pattern 20 are separated to generate a fifth image 5 in the plane, bottom, front, back, left and right surfaces in which 30 is separated The via hole 30 includes an image conversion unit 160 that matches and overlaps the separated fifth image 5 to provide drawing data 6 , and the like.

The printed circuit board 40 may have a guide hole 10 , a multi-layered circuit pattern 20 , and a via hole 30 as a reverse engineering object.

Here, the printed circuit board 40 may include, for example, circuit patterns 20 of four layers by printing circuits on both sides of two substrates, respectively, and bonding the two substrates through a base layer, and The circuit patterns 21, 22, 23, 24 of the first, second, third and fourth layers and the circuit patterns 21, 22, 23, and 24 of the first to fourth layers are selectively perpendicular to the bottom in order. It may include a plurality of via holes 30 for conducting to the .

The image photographing unit 110, 10 first images 1 for the flat surface, the bottom surface, the top surface, the front surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface of the printed circuit board 40 As a photographing means, the inside of the printed circuit board 40 is photographed through an X-ray or the like, so that the multi-layered circuit pattern 20 and the via hole 30 can be checked.

Here, the image capturing unit 110, the plane and the bottom surface of the printed circuit board 40 are photographed at an angle of 0 degrees with respect to the center of the printed circuit board 40, and the top surface of the printed circuit board 40, if determined, It is preferable that the back surface, the lower surface, the upper left surface, the left lower surface, the upper right surface, and the right lower surface are photographed at an angle of 2 degrees to 5 degrees with respect to the center of the printed circuit board 40 , respectively.

Therefore, in the first image 1, for example, when the number of stacked circuit patterns 20 of the printed circuit board 40 is 4 layers, the first image 1 - 1 of the first layer shows the circuit patterns 21 of the first layer. ) and the guide hole 10, and through the first image 1-2 of the bottom, the circuit pattern 24 and the guide hole 10 of the four layers are shown, and the top surface, the fixed surface, the upper surface, the lower surface, the upper left Through the first images (1-3,1-4,1-5,1-6,1-7,1-8,1-9, 1-10) The circuit pattern 21 of the first layer, the circuit pattern 22 of the second layer, the circuit pattern 23 of the third layer, the circuit pattern 24 of the fourth layer, the via hole 30 and the guide hole 10 of each layer are shown. .

On the other hand, in the present invention, when the image capturing unit 110 photographs the top surface, the fixed surface, the upper surface, the rear surface, the upper left surface, the left surface, the right surface, the right lower surface of the printed circuit board 40, the photographing angle is 2 It is preferable to shoot at an angle of 5 to 5 degrees.

That is, when the photographing angle is less than 2 degrees, as the area of the image photographed at an oblique angle increases, the projected brightness becomes brighter when the photographing distance approaches, even though the circuit patterns 20 are stacked in multiple layers. All of them are photographed with bright brightness, so their classification and separation and extraction become very complicated, and when the shooting distance increases, the projected brightness becomes dark. Since division and separation and extraction become very complicated, this problem can be prevented through the angle limitation as described above.

In addition, when the photographing angle exceeds 5 degrees, as the area of the image photographed at an oblique angle is reduced, the circuit patterns 20 overlap with the same thickness and finely spaced apart, or the circuit patterns 20 of each layer are partially In spite of the fact that the circuit patterns 20 are overlapped in spite of being configured with a predetermined depth or thickness to allow mutual conduction with each other, the separation and separation of the location and depth of the via hole 30 and separation and extraction become very complicated, so the angle limitation as described above This problem can be prevented through

Therefore, according to the image capturing unit 110, ten first images (1) for the flat surface, the bottom surface, the top surface, the front surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface of the printed circuit board 40 ) can be photographed, and through this, the number of stacked circuit patterns 20 of the printed circuit board 40 and the via hole 30 can be confirmed.

The coordinate value input unit 120 calculates an X-axis length, a Y-axis length, and a Z-axis length based on the position of the guide hole 10 in the ten first images 1 photographed by the image capturing unit 110 . And as a means for generating a second image by measuring and inputting three-dimensional coordinate values, the lengths of the width, length and thickness of the printed circuit board 40 photographed in the ten first images 1 are measured in the guide hole 10 . The thickness, stacking height and shape of the circuit pattern 20 photographed in each of the first images (1-1 to 1-10) after calculation and measurement as the X-axis length, Y-axis length, and Z-axis length based on the position of and 3D coordinate values for the position and depth of the via hole 30 are input.

Here, the coordinate value input unit 120, based on the position of the guide hole 10, each of the width, length and thickness of the printed circuit board 40 photographed in each of the ten first images 1, respectively. It can be composed of a program that calculates and measures the X-axis length, Y-axis length, and Z-axis length, and inputs the values.

Therefore, according to the coordinate value input unit 120 , information on the thickness, stacking height and shape of the circuit pattern 20 photographed in the first image 1 , and the position and depth of the via hole 30 is accurately obtained as a three-dimensional coordinate value. may be specified or expressed.

The magnification unit 130 adjusts the magnification of the ten second images to which the coordinate values are input based on the three-dimensional coordinate value to generate a third image in which all ten second images have the same magnification. Based on the coordinate values of the images, the magnification of the second images is uniformly corrected and distortion is compensated for.

Here, the magnification unit 130 may be a graphic editing application program, such as a known Photoshop or Illustrator, so that the X-axis length, Y-axis length, and Z-axis length of each of the ten second images have the same scale. is adjusted

Therefore, according to the magnification adjustment unit 130, even if a distorted image or a magnification error image of the photographed images of the printed circuit board 40 is generated, it is corrected, the number or shape of the circuit pattern 20 appearing in the third image, and The position and depth of the via hole 30 may all have the same coordinate value and size.

The circuit pattern separating unit 140 identifies and separates the circuit patterns 20 of the printed circuit board 40 by the number of stacks based on the ten third images whose magnification is adjusted, and separates each of the circuit patterns 20 As a means for generating the fourth image 4 in the floor plan, based on the third image of the flat surface and the bottom surface, the third image of the top surface, the fixed surface, the upper surface, the lower surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface The shape of each layer pattern of the circuit pattern 20 is generated as a fourth image 4 viewed from a plane through the brightness contrast between the circuit patterns 20 while comparing and contrasting.

Here, the circuit pattern separation unit 140 can determine the presence and shape of a pattern for each layer through brightness contrast by using the characteristic that the brightness becomes darker as the distance increases when the printed circuit board 40 is photographed. It may be a graphic editing application such as Photoshop or Illustrator.

In addition, the fourth image 4 is, for example, when the number of stacked circuit patterns 20 of the printed circuit board 40 is four, the circuit patterns 20 of the first to fourth layers are viewed in a plan view of the first layer. It includes a fourth image 4-1, a fourth image 4-2 of the second layer, a fourth image 4-3 of the third layer, and a fourth image 4-4 of the fourth layer.

Accordingly, according to the circuit pattern separation unit 140 , an image of the circuit pattern 20 for each layer of the printed circuit board 40 may be generated as a plurality of fourth images 4 .

The via hole separation unit 150 identifies the position and depth of the via hole 30 of the printed circuit board 40 based on the ten third images whose magnification is adjusted, and separates each to separate the via hole 30 from the plane, the bottom surface. , a means for generating a fifth image 5 from the front, rear, left and right surfaces, based on the third image of the flat surface and the bottom surface. The position and depth of the via hole 30 that partially conducts the circuit pattern 20 for each layer through the brightness contrast between the via hole 30 and the circuit patterns 20 while comparing and contrasting the third image of the right lower surface is measured on the plane and the bottom surface. , a fifth image (5) viewed from the front, rear, left and right sides is created.

Here, the via hole separation unit 150 uses the characteristic that the brightness becomes darker as the distance increases when the printed circuit board 40 is photographed. The separation distance of the patterns) and the location (the contact point of the circuit patterns for each layer) can be grasped, and it may be a graphic editing application program such as a well-known photoshop or illustrator.

In addition, in the fifth image 5, for example, when the printed circuit board 40 is a rectangle or a rectangle, the position information of the via hole 30 having a depth for partially conducting the circuit patterns 20 of a plurality of layers is displayed on each side. 5 images of the plane viewed from (5-1), the 5th image of the bottom (5-2), the 5th image of the front (5-3), the 5th image of the back (5-4), the 5th of the left side It includes an image 5-5 and a fifth image 5-6 of the right side.

That is, the via hole 30 connects the circuit pattern 21 of the first layer and the circuit pattern 22 of the second layer to the first via hole 31 , the circuit pattern 22 of the second layer and the circuit pattern of the third layer. In the case of having a second via hole 32 connecting 23 and a third via hole 33 connecting the circuit pattern 23 of the third layer and the circuit pattern 24 of the fourth layer, the fifth image (5) ), the position and depth of each via hole 30 can be confirmed.

Therefore, according to the via hole separator 150 , the position and depth of the via hole 30 can be generated as the fifth image 5 viewed from each of the six sides of the printed circuit board 40 .

The image conversion unit 160 matches and overlaps the fourth image 4 in which the circuit pattern 20 of each layer is separated and the fifth image 5 in which the via hole 30 is separated to generate the drawing data 6 . As a means of providing, drawing data 6 having coordinate values of the circuit patterns 21, 22, 23, 24 for each layer, the via hole 30 and the guide hole 10 by converting the pixel-type images into a vector-type image ) is converted to

Here, the image conversion unit 160 may be a well-known vectorizing program for converting pixel-type images into a vector-type image, or a drawing program such as a CAD program.

In addition, in the drawing data 6 , for example, the number of stacked circuit patterns 20 of the printed circuit board 40 is four, and the circuit patterns 21 , 22 , 23 , and 24 for each layer are partially through the via hole 30 . In the case of conduction, four fourth images (4-1 to 4-4) showing the circuit patterns 21, 22, 23, and 24 for each of the four layers and six fifth images (5) showing a plurality of via holes 30 1 to 5-6), the circuit pattern 21 of the first layer, the circuit pattern 22 of the second layer, the circuit pattern 23 of the third layer, the circuit pattern 24 of the fourth layer, and the via hole 30 of each layer and the drawing data 6-1 of the plane viewed from each side of the guide hole 10, the drawing data 6-2 of the bottom, the drawing data 6-3 of the front, and the drawing data 6-4 of the rear surface , including drawing data 6-5 on the left side and drawing data 6-6 on the right side.

Therefore, according to the image conversion unit 160, the circuit pattern 21 of the first layer, the circuit pattern 22 of the second layer, the circuit pattern 23 of the third layer, the circuit pattern 24 of the fourth layer, and the via hole ( 30) and the guide hole 10 viewed from each side of the plane drawing data 6-1, the bottom drawing data 6-2, the front drawing data 6-3, the rear drawing data 6- 4), the drawing data 6-5 of the left side and the drawing data 6-6 of the right side can be generated, and the circuit of the printed circuit board 40 can be restored based on the drawing data 6 .

That is, the fourth image (4) of four and the fifth image (5) of six have a state in which coordinate values are input by the coordinate value input unit 120 and magnification and distortion are corrected by the magnification adjustment unit 130. Accordingly, since the reference point of each coordinate value has the same state, it is possible to convert the drawing data 6 only by a simple process of superimposing and matching images based on the coordinate value, and a plurality of drawing data 6 is 3D in a known manner. PCBs can be reverse engineered or restored by matching and synthesizing with

Hereinafter, a printed circuit board reverse design method according to a preferred embodiment of the present invention will be described.

First, the flat surface, the bottom surface, the top surface of the printed circuit board 40 having the guide hole 10 and the multi-layered circuit pattern 20 and the via hole 30 by the image capturing unit 110. Ten first images 1 for the upper left surface, the lower left surface, the upper right surface and the right lower surface are photographed.

Here, the first images 1-1 and 1-2 of the flat surface and the bottom surface are taken at an angle of 0 degrees with respect to the center of the printed circuit board 40, and the top surface, the fixed surface, the upper surface, the rear surface, the upper left surface, It is preferable that the first images 1-3 to 1-10 of the left side, the right side, and the right side are taken at an angle of 2 to 5 degrees with respect to the center of the printed circuit board 40 , respectively.

Thereafter, a three-dimensional coordinate value based on the position of the guide hole 10 is inputted to the ten first images 1 photographed by the image capturing unit 110 by the coordinate value input unit 120 to obtain a second image. is created

Thereafter, the magnification of the ten second images to which the coordinate values are inputted by the magnification adjustment unit 130 is adjusted based on the coordinate values, so that the ten second images are all generated as third images having the same magnification.

Thereafter, among the ten third images whose magnification is adjusted by the circuit pattern separating unit 140 , based on the third image of the flat surface and the bottom surface, the normal surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right surface As the third image of the lower surface is compared and contrasted, the shape of the pattern for each layer of the circuit pattern 20 is generated as the fourth image 4 viewed from the plane through the brightness contrast between the circuit patterns 20 .

Then, among the ten third images whose magnification is adjusted by the via hole separation unit 150, the top surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right surface based on the third image of the plane and the bottom surface. The position and depth of the via hole 30 that partially conducts the circuit pattern 20 for each layer through the brightness contrast between the via hole 30 and the circuit patterns 20 while comparing and contrasting the third image of , a fifth image 5 viewed from the back, left and right sides is generated.

Thereafter, the fourth image 4 in which the circuit pattern 20 is separated by the image conversion unit 160 and the fifth image 5 in which the via hole 30 is separated are matched and overlapped to form a circuit pattern 20 for each layer. The via hole 30 and the guide hole 10 are converted into drawing data 6 having coordinate values.

Therefore, according to the above-mentioned bar, images of the top surface, the fixed surface, the upper surface, the rear surface, the upper left surface, the left surface, the right surface and the right surface as well as the flat surface and the bottom surface of the printed circuit board 40 are photographed and printed based on each image. The circuit of the printed circuit board 40 can be accurately reverse-engineered by accurately determining the number of stacked circuit patterns 20 of the circuit board 40 and the positions of the via holes 30 between the circuit patterns 20 .

Although preferred embodiments of the present invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains may substitute variously within the scope without departing from the technical spirit or essential characteristics of the present invention. and variations are possible, so it will be understood that the embodiments may be implemented in other specific forms. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (5)

A flat surface, a bottom surface, a top surface, a fixed surface, an upper surface, a lower surface, an upper left surface, a left lower surface, a right upper surface and a right surface of the printed circuit board 40 having the guide hole 10 and the multilayer circuit pattern 20 and the via hole 30 . an image projection unit 110 for photographing ten first images 1 for the lower surface; a coordinate value input unit 120 for generating a second image by inputting three-dimensional coordinate values based on the position of the guide hole 10 in the ten first images 1 photographed by the image capturing unit 110; a magnification unit 130 that adjusts the magnification of the ten second images to which the coordinate values are input based on the coordinate values to generate a third image in which all ten second images have the same magnification; Based on the ten third images whose magnification has been adjusted, the circuit patterns 20 of the printed circuit board 40 are identified by the number of stacked layers, and the fourth image 4 on the plane of each layer from which the circuit patterns 20 are separated by separating each. ) a circuit pattern separating unit 140 to generate; The position and depth of the via hole 30 of the printed circuit board 40 are identified and separated based on the ten third images whose magnification is adjusted, respectively, to separate the plane, bottom, front, rear, left and right surfaces from which the via holes 30 are separated. a via hole separation unit 150 for generating a fifth image 5 in the ; and an image conversion unit 160 providing drawing data 6 by matching and superimposing the fourth image 4 in which the circuit pattern 20 is separated and the fifth image 5 in which the via hole 30 is separated do,
The image photographing unit 110,
The plane and the bottom of the printed circuit board 40 are photographed at an angle of 0 degrees with respect to the center of the printed circuit board 40,
The top surface of the printed circuit board 40, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the right upper surface, the right lower surface of the printed circuit board 40, respectively, based on the center of the printed circuit board 40 to photographing at an angle of 2 to 5 degrees Printed circuit board reverse engineering system. delete According to claim 1, wherein the circuit pattern separation unit 140,
Based on the third image of the flat surface and the bottom surface, the third image of the normal surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface is compared and contrasted while comparing the third images of the circuit patterns 20 through the brightness contrast between the circuit patterns. A printed circuit board reverse engineering system, characterized in that the shape of the pattern for each layer of the pattern (20) is generated as a fourth image (4) viewed from a plane. The method of claim 3, wherein the via hole separation unit 150,
Between the via hole 30 and the circuit patterns 20 while comparing and contrasting the third images of the top surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the upper right surface and the right lower surface based on the third image of the plane and the bottom surface The position and depth of the via hole 30 that partially conducts the circuit pattern 20 for each layer through the brightness contrast is generated as a fifth image 5 viewed from the plane, bottom, front, back, left and right sides. printed circuit board reverse engineering system. A flat surface, a bottom surface, a top surface, a fixed surface, an upper surface, a lower surface, an upper left surface, a left lower surface, a right upper surface and a right surface of the printed circuit board 40 having the guide hole 10 and the multilayer circuit pattern 20 and the via hole 30 . photographing ten first images (1) for the lower surface;
generating a second image by inputting a three-dimensional coordinate value based on the position of the guide hole 10 in the ten first images 1;
generating a third image in which all ten second images have the same magnification by adjusting the magnification of the ten second images to which the coordinate values are input based on the coordinate values;
Based on the ten third images whose magnification has been adjusted, the circuit patterns 20 of the printed circuit board 40 are identified by the number of stacked layers, and the fourth image 4 on the plane of each layer from which the circuit patterns 20 are separated by separating each. );
The position and depth of the via hole 30 of the printed circuit board 40 are identified and separated based on the ten third images whose magnification is adjusted, respectively, to separate the plane, bottom, front, rear, left and right surfaces from which the via holes 30 are separated. generating a fifth image (5) in
Comprising the step of providing drawing data (6) by matching and overlapping the fourth image (4) in which the circuit pattern (20) is separated and the fifth image (5) in which the via hole (30) is separated,
The plane and the bottom of the first image 1 are taken at an angle of 0 degrees with respect to the center of the printed circuit board 40,
The top surface, the fixed surface, the upper surface, the lower surface, the upper left surface, the left lower surface, the right upper surface, and the right lower surface of the first image (1) are taken at an angle of 2 to 5 degrees with respect to the center of the printed circuit board 40, respectively. Printed circuit board reverse engineering method characterized.

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