KR102279274B1 - thin film transistor array panel for digital X-ray detector - Google Patents

Abstract

The present invention includes a thin film transistor, a protective film, a reflective electrode, and a photodiode. The thin film transistor is positioned on a substrate and has a coplanar structure having a first semiconductor layer of oxide, a gate electrode, a first electrode, and a second electrode. The protective film covers the thin film transistor. The reflective electrode is positioned on the passivation layer and covers a region corresponding to the channel region of the thin film transistor. The photodiode is positioned on the passivation layer and has a lower electrode connected to the second electrode of the thin film transistor, a second semiconductor layer positioned on the lower electrode, and an upper electrode positioned on the second semiconductor layer.

Description

Thin film transistor array panel for digital X-ray detector

The present invention relates to a thin film transistor array substrate for a digital X-ray detector.

X-rays can easily pass through a subject with a short wavelength, and the amount of X-ray transmission is determined according to the density of the inside of the subject. That is, the internal state of the subject may be indirectly observed through the amount of X-rays transmitted through the subject.

The X-ray detector is a device for detecting the amount of X-rays passing through a subject. The X-ray detector may detect a transmission amount of X-rays and display the internal state of the subject to the outside through the display device.

In general, the X-ray detector may be used as a medical inspection device, a non-destructive testing device, and the like. Currently, a digital X-ray detector using a digital radiation (DR) method that does not use a film as an X-ray detector is widely used.

The digital X-ray detector includes a thin film transistor array substrate. A thin film transistor array for digital X-ray detectors is a photo-diode (PIN diode) that receives X-rays, converts them into visible light, and converts visible light back into an electrical signal, and a thin film for outputting data converted from the photodiode into an electrical signal. It consists of transistors.

Conventionally, when implementing a transistor array substrate for a digital X-ray detector, a method of implementing a thin film transistor based on amorphous silicon (a-Si) has been proposed. However, the conventionally proposed method has many difficulties in securing device characteristics due to off current and current crowding issues of thin film transistors, as well as problems due to high parasitic capacitance generation. Improvement is required.

The present invention for solving the problems of the above-described background technology reduces power consumption by reducing the generation factor of the parasitic capacitance (Cgs), improves the signal detection ability and improves the current crowding issue to improve the device characteristics. is to improve In addition, the present invention is to reduce the effect of hydrogen (possibility of deterioration of the oxide thin film transistor) during the semiconductor layer process of the photodiode and block the incident path of visible light from the top.

As a means for solving the above problems, the present invention includes a thin film transistor, a protective film, a reflective electrode, and a photodiode. The thin film transistor is positioned on a substrate and has a coplanar structure having a first semiconductor layer of oxide, a gate electrode, a first electrode, and a second electrode. The protective film covers the thin film transistor. The reflective electrode is positioned on the passivation layer and covers a region corresponding to the channel region of the thin film transistor. The photodiode is positioned on the passivation layer and has a lower electrode connected to the second electrode of the thin film transistor, a second semiconductor layer positioned on the lower electrode, and an upper electrode positioned on the second semiconductor layer.

The reflective electrode may extend from the lower electrode.

In another aspect, the present invention includes a thin film transistor, a first passivation film, a planarization film, a second passivation film, a lower connection electrode, a reflective electrode, and a photodiode. The thin film transistor is positioned on a substrate and has a coplanar structure having a first semiconductor layer of oxide, a gate electrode, a first electrode, and a second electrode. The first passivation layer covers the thin film transistor. The planarization layer is positioned on the first passivation layer and planarizes the surface. The second passivation layer is positioned on the planarization layer. The lower connection electrode is located on the second passivation layer and is connected to the first electrode of the thin film transistor. The reflective electrode is positioned on the second passivation layer and covers a region corresponding to the channel region of the thin film transistor. The photodiode has a lower electrode positioned on the second passivation layer and connected to the second electrode of the thin film transistor, a second semiconductor layer positioned on the lower electrode, and an upper electrode positioned on the second semiconductor layer.

In another aspect, the present invention includes a photodiode, an insulating film, and a thin film transistor. The photodiode has a lower electrode positioned on the substrate, a second semiconductor layer positioned on the lower electrode, and an upper electrode positioned on the second semiconductor layer. The insulating film covers the photodiode. The thin film transistor is disposed on an insulating layer and has a coplanar structure having a first semiconductor layer of oxide, a gate electrode, a first electrode, and a second electrode electrically connected to the upper electrode.

The insulating layer may further include a planarization layer covering the photodiode and planarizing a surface thereof, and a first passivation layer disposed on the planarization layer.

The present invention has the following effects when manufacturing and implementing a thin film transistor array substrate for a digital X-ray detector. Since the present invention is implemented based on a thin film transistor having a coplanar structure, it is possible to reduce the generation factor of the parasitic capacitance (Cgs) (reduction of power consumption). In addition, since the semiconductor layer of the thin film transistor is formed of an oxide (eg, IGZO) with excellent off current characteristics, the present invention improves signal detection ability according to noise reduction and improves the current crowding issue. It is possible to improve the characteristics of the device. In addition, the present invention forms an electrode film that can serve as a hydrogen barrier and a light shield to reduce the effect of hydrogen (possibility of deterioration of the oxide thin film transistor) during the semiconductor layer process of the photodiode and from the top. It can block the incident path of visible light.

1 is a block diagram schematically illustrating a digital X-ray detector.
2 is an exemplary circuit configuration diagram of a photo-sensing sub-pixel formed in a thin film transistor array for a digital X-ray detector.
3 is an exemplary plan layout configuration diagram of a photo-sensing sub-pixel according to the first embodiment of the present invention;
4 is a cross-sectional view showing regions A1-A2, B1-B2 and C1-C2 of FIG. 3 according to the first embodiment of the present invention;
5 to 7 are cross-sectional views illustrating a process flow for the photo-sensing sub-pixel of FIG. 4 according to the first embodiment of the present invention;
8 is an exemplary plan layout configuration diagram of a photo-sensing sub-pixel according to a second embodiment of the present invention;
9 is a cross-sectional view showing a region A1-A2 of FIG. 8 according to a second embodiment of the present invention;
10 is a cross-sectional view showing a photo-sensing sub-pixel according to a third embodiment of the present invention;
11 is a cross-sectional view showing a photo-sensing sub-pixel according to a fourth embodiment of the present invention;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

A digital X-ray detector (DXD) to be described below is a device that takes an X-ray image and converts it into an electrical signal. In particular, the digital X-ray detector described below is implemented in a non-direct manner. In a non-direct type digital X-ray detector, a scintillator film is positioned on a thin film transistor array. The light converted into visible light by the scintillator film is incident (or absorbed) into the photodiode.

The digital X-ray detector has advantages such as improved diagnosis speed and easy data storage compared to an analog type X-ray film used in conventional medical X-ray diagnostic equipment.

However, the conventionally proposed method has many difficulties in securing device characteristics due to off current and current crowding issues of thin film transistors, as well as problems due to high parasitic capacitance. We propose a structure like

<First embodiment>

1 is a block diagram schematically illustrating a digital X-ray detector, and FIG. 2 is an exemplary circuit configuration diagram of a photo-sensing sub-pixel formed in a thin film transistor array for a digital X-ray detector.

1 and 2 , the digital X-ray detector includes a thin film transistor array 110 , a bias supply unit 140 , a gate driver 130 , a readout circuit unit 160 , a timing control unit 170 , and a power supply voltage. A supply unit 150 is included.

The thin film transistor array 110 detects X-rays emitted from the energy source, photoelectrically converts the sensed signal, and outputs an electrical detection signal. Light sensing sub-pixels SP are formed in the thin film transistor array 110 . A cell region of each of the photo-sensing sub-pixels SP is defined by gate lines GL arranged in a horizontal direction and data lines DL arranged in a vertical direction to intersect the gate lines GL.

A photodiode PIN that senses X-rays and outputs a detection signal, for example, a photodetection voltage, and a detection signal output from the photodiode PIN in response to the gate signal are transmitted to the photo-sensing sub-pixels SP Each of the thin film transistors (TFT) is included.

The photodiode PIN detects the X-ray emitted from the energy source, and outputs the detected signal as a detection signal. A photodiode (PIN) is a device that converts light incident by the photoelectric effect into an electrical detection signal, for example, PIN (P-type semiconductor layer/intrinsic (I) semiconductor layer/N-type semiconductor layer stacked structure) Diodes can be selected.

In the photodiode PIN, a first electrode is connected to a second electrode of the thin film transistor TFT, and a second electrode is connected to a bias line BL. The first electrode of the photodiode PIN becomes the anode electrode and the second electrode becomes the cathode electrode.

In the thin film transistor TFT, a gate electrode is connected to a gate line GL transmitting a scan signal, a first electrode is connected to a data line DL transmitting a detection signal, and a first electrode is connected to a first electrode of a photodiode PIN. Two electrodes are connected. The first electrode and the second electrode of the thin film transistor TFT become a source electrode and a drain electrode or a drain electrode and a source electrode depending on the type of the transistor. The data line DL and the bias line BL are formed parallel to each other between the cells.

The gate driver 130 sequentially outputs gate signals having a gate-on voltage level through the gate lines GL. The gate driver 130 may also output reset signals having a gate-on voltage level through the reset lines RL. The gate-on voltage level is a voltage level capable of turning on the thin film transistors of the photo-sensing sub-pixels SP. The thin film transistors of the light sensing sub-pixels SP may be turned on in response to a gate signal or a reset signal.

The gate driver 130 is formed in the form of an integrated circuit (IC) and mounted on the thin film transistor array 110 or an external substrate connected thereto, or on the thin film transistor array 110 through a thin film process (Gate In Panel; GIP). can be formed.

The bias supply unit 140 outputs a driving voltage through the bias lines BL. The bias supply unit 140 may apply a constant voltage to the photodiode PIN or selectively apply a reverse bias or a forward bias.

The power voltage supply unit 150 supplies a power voltage to the photo-sensing sub-pixels SP through the power voltage lines VL.

The readout circuit unit 160 reads out a detection signal output from the turned-on thin film transistor TFT in response to the gate signal. Accordingly, the detection signal output from the photodiode PIN is input to the readout circuit unit 160 through the data line DL.

The readout circuit unit 160 reads out the detection signal output from the photo-sensing sub-pixels SP in the offset readout section for reading out the offset image and the X-ray readout section for reading out the detection signal after the X-ray exposure .

The readout circuit unit 160 may include a signal detector and a multiplexer. The signal detection unit includes a plurality of amplifying circuit units corresponding to the data lines DL one-to-one, and each amplifying circuit unit includes an amplifier, a capacitor, and a reset device.

The timing controller 180 generates a start signal STV and a clock signal CPV and supplies them to the gate driver 130 to control the operation of the gate driver 130 . The timing controller 180 generates a readout control signal ROC, a readout clock signal CLK, and the like to control the operation of the readout circuit unit 160 , and supplies them to the readout circuit unit 160 .

3 is an exemplary plan layout configuration diagram of a photo-sensing sub-pixel according to a first embodiment of the present invention, and FIG. 4 is a view showing the configuration of a plane layout A1-A2, B1-B2 and C1-C2 of FIG. 3 according to the first embodiment of the present invention. 5 to 7 are cross-sectional views illustrating a process flow for the photo-sensing sub-pixel of FIG. 4 according to the first embodiment of the present invention.

As shown in FIG. 3 , the photo-sensing sub-pixel is defined by a data line DL, a gate line GL, and a bias line BL. The photo-sensing sub-pixel includes a photodiode (PIN) and a thin film transistor (TFT). A gate pad part GP is formed at one end of the gate line GL, and a data pad part DP is formed at one end of the data line DL.

The data line DL and the gate line GL are arranged in a vertical direction and a horizontal direction of the photo-sensing sub-pixels and are formed to cross vertically. The bias line BL is arranged to be parallel to the data line DL and is formed so that some sections are refracted. However, since the planar layout of the photo-sensing sub-pixels shown in FIG. 3 is only an example, the first embodiment of the present invention is not limited thereto.

4 , on the thin film transistor array substrate 110a, a data line area DLA, a thin film transistor area TFTA, a photodiode area PINA, a bias line area BLA, and a gate pad area GPA are provided. ) and a data pad area DPA are defined. The thin film transistor array substrate 110a may be selected as a non-flexible substrate (eg, glass) or a flexible substrate (eg, plastic). The thin film transistor array substrate 110a may be selected as a transparent substrate or an opaque high temperature substrate.

A data line DL is formed in the data line area DLA, a thin film transistor TFT is formed in the thin film transistor area TFTA, a photodiode PIN is formed in the photodiode area PINA, and a bias line The bias line BL is formed in the area BLA, the gate pad part GP is formed in the gate pad area GPA, and the data pad part DP is formed in the data pad area DPA.

Hereinafter, a manufacturing process of the photo-sensing sub-pixel will be described with reference to FIGS. 5 to 7 . The manufacturing process of the photo-sensing sub-pixel includes the buffer layer 111, the first semiconductor layer 112, the first insulating layers 113a and 113b, the gate metal layers 114a and 114b, the second insulating layer 115, the data metal layer 116a, 116b, 116c, 116d), a third insulating film 117, a lower electrode 118 and a reflective electrode 118R, a second semiconductor layer 119 and an upper electrode 120, a fourth insulating film 121 and an upper metal layer ( 122a, 122b, 122c, 122d) are formed in this order.

5 , a buffer layer 111 is formed on the thin film transistor array substrate 110a. The buffer layer 111 may be formed to protect a thin film transistor formed in a subsequent process from impurities such as alkali ions leaking from the thin film transistor array substrate 110a. The buffer layer 111 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like, and may be omitted.

A first semiconductor layer 112 is formed on the buffer layer 111 of the thin film transistor area TFTA. The first semiconductor layer 112 is made of an oxide such as indium gallium zinc oxide (IGZO) or TiO2, ZnO, WO3, SnO2, or the like.

First insulating layers 113a and 113b are formed on the first semiconductor layer 112 of the thin film transistor area TFTA and the buffer layer 111 of the gate pad area GPA. The first insulating layers 113a and 113b may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The first insulating layers 113a and 113b may be defined as gate insulating layers. The first insulating layers 113a and 113b are formed in an island shape.

Gate metal layers 114a and 114b are formed on the first insulating layers 113a and 113b of the thin film transistor area TFTA and the gate pad area GPA. The gate metal layers 114a and 114b are one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or these may be an alloy of , and may consist of a single layer or multiple layers. The gate metal layer 114a of the thin film transistor area TFTA becomes a gate electrode, which is the same as the gate line GL. The gate metal layer 114b of the gate pad area GPA becomes a gate pad electrode.

In the first embodiment of the present invention, a thin film transistor array for a digital X-ray detector is implemented based on a thin film transistor having a top gate coplanar structure, so that a factor of generating a parasitic capacitance (Cgs) can be reduced. In addition, in the first embodiment of the present invention, since the semiconductor layer of the thin film transistor is formed of an oxide (eg, IGZO) having excellent off current characteristics, the current crowding issue is improved and device characteristics are secured. can do.

As shown in FIG. 6 , a second insulating layer 115 is formed on the buffer layer 111 . The second insulating layer 115 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The second insulating layer 115 may be defined as an interlayer insulating layer. The second insulating layer 115 is formed to cover the gate metal layers 114a and 114b. The second insulating layer 115 has a contact hole exposing the source region and the drain region of the first semiconductor layer 112 and the gate metal layer 114b of the gate pad region GPA.

Data metal layers 116a, 116b, 116c, and 116d are formed on the second insulating layer 115 . The data metal layers 116a, 116b, 116c, and 116d are from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one selected or an alloy thereof, and may consist of a single layer or multiple layers.

The data metal layer 116a of the data line area DLA becomes a first electrode of the thin film transistor TFT, and the data metal layer 116b of the thin film transistor area TFTA becomes a second electrode of the thin film transistor TFT. The data metal layer 116c of the gate pad area GPA becomes a gate pad electrode, and the data metal layer 116d of the data pad area DPA becomes a data pad electrode.

7 , a third insulating layer 117 is formed on the second insulating layer 115 . The third insulating layer 117 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The third insulating layer 117 may be defined as a first passivation layer. The third insulating layer 117 is formed to cover the data metal layers 116a, 116b, 116c, and 116d. The third insulating layer 117 includes the data metal layer 116a of the data line area DLA, the data metal layer 116b of the thin film transistor area TFTA, the data metal layer 116c of the gate pad area GPA, and the data pad area. It has a contact hole exposing the data metal layer 116d of the area DPA.

A lower electrode 118 and a reflective electrode 118R are formed on the third insulating layer 117 of the photodiode area PINA and the thin film transistor area TFTA. The lower electrode 118 is electrically connected to the data metal layer 116b of the thin film transistor area TFTA. The lower electrode 118 becomes a cathode electrode of the photodiode PIN. The reflective electrode 118R covers a region corresponding to the channel region (a region between the first electrode and the second electrode of the thin film transistor) of the first semiconductor layer 112 . The reflective electrode 118R serves as a hydrogen barrier that blocks the effect of hydrogen (possibility of deterioration of the oxide thin film transistor) of the thin film transistor TFT and a light shield that blocks incident of visible light.

The lower electrode 118 and the reflective electrode 118R are selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one selected or an alloy thereof, and may consist of a single layer or multiple layers. The lower electrode 118 and the reflective electrode 118R may be formed of the same metal. In this case, the reflective electrode 118R becomes an electrode extending from the lower electrode 118 . Since the reflective electrode 118R acts as a physical and chemical barrier, it is preferable that the above-listed materials have superior light-blocking properties.

A second semiconductor layer 119 is formed on the lower electrode 118 of the photodiode region PINA. The second semiconductor layer 119 is formed in a structure in which PINs (P-type semiconductor layer/intrinsic (I) semiconductor layer/N-type semiconductor layer) are stacked.

The upper electrode 120 is formed on the second semiconductor layer 119 of the photodiode region PINA. The upper electrode 120 may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper electrode 120 becomes the anode electrode of the photodiode PIN.

A fourth insulating layer 121 is formed on the third insulating layer 117 . The fourth insulating layer 121 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The fourth insulating layer 121 may be defined as a second passivation layer. The fourth insulating layer 121 is formed to cover the reflective electrode 118R of the thin film transistor area TFTA and the upper electrode 120 of the photodiode area PINA.

The fourth insulating layer 121 includes the data metal layer 116a of the data line area DLA, the upper electrode 120 of the bias line area BLA, the data metal layer 116c of the gate pad area GPA, and the data pad part. It has a contact hole exposing the data metal layer 116d of the area DPA.

Upper metal layers 122a, 122b, 122c, and 122d are formed on the fourth insulating layer 121 of the data line area DLA, the bias line area BLA, the gate pad area GPA, and the data pad area DPA. do. The upper metal layers 122a, 122b, 122c, and 122d are from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu). It may be one selected or an alloy thereof, and may consist of a single layer or multiple layers.

The upper metal layer 122a of the data line area DLA is electrically connected to the data metal layer 116a of the data line area DLA, which becomes the data line DL. The upper metal layer 122b of the bias line area BLA is electrically connected to the upper electrode 120 of the photodiode PIN, which becomes the bias line BL. The upper metal layer 122c of the gate pad area GPA becomes the gate pad area GP, and the upper metal layer 122d of the data pad area DPA becomes the data pad area DP.

The first embodiment of the present invention forms an electrode film that can serve as a hydrogen barrier and a light shield as described above, so that hydrogen influences (possibility of deterioration of oxide thin film transistor) during semiconductor layer processing of photodiode. can be reduced and the incident path of visible light from the top can be blocked.

Hereinafter, another embodiment of the present invention will be described. However, in the following description, the part related to the photo-sensing sub-pixel will be mainly described and the part related to the pad part will be omitted.

<Second embodiment>

8 is an exemplary plan layout configuration diagram of a photo-sensing sub-pixel according to a second embodiment of the present invention, and FIG. 9 is a cross-sectional view illustrating areas A1-A2 of FIG. 8 according to the second embodiment of the present invention.

As shown in FIG. 8 , the photo-sensing sub-pixel is defined by a data line DL, a gate line GL, and a bias line BL. The photo-sensing sub-pixel includes a photodiode (PIN) and a thin film transistor (TFT). A gate pad part GP is formed at one end of the gate line GL, and a data pad part DP is formed at one end of the data line DL.

The data line DL and the gate line GL are arranged in a vertical direction and a horizontal direction of the photo-sensing sub-pixels and are formed to cross vertically. The bias line BL is formed to be parallel to the data line DL. However, since the planar layout of the photo-sensing sub-pixels shown in FIG. 8 is only an example, the second embodiment of the present invention is not limited thereto.

9 , a data line area DLA, a thin film transistor area TFTA, a photodiode area PINA, and a bias line area BLA are defined on the thin film transistor array substrate 110a.

A buffer layer 111 is formed on the thin film transistor array substrate 110a. The buffer layer 111 may be formed to protect a thin film transistor formed in a subsequent process from impurities such as alkali ions leaking from the thin film transistor array substrate 110a. The buffer layer 111 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like, and may be omitted.

A first semiconductor layer 112 is formed on the buffer layer 111 of the thin film transistor area TFTA. The first semiconductor layer 112 is made of an oxide such as indium gallium zinc oxide (IGZO) or TiO2, ZnO, WO3, SnO2, or the like.

First insulating layers 113a and 113b are formed on the first semiconductor layer 112 of the thin film transistor area TFTA and the buffer layer 111 of the gate pad area GPA. The first insulating layers 113a and 113b may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The first insulating layers 113a and 113b may be defined as gate insulating layers. The first insulating layers 113a and 113b are formed in an island shape.

Gate metal layers 114a and 114b are formed on the first insulating layers 113a and 113b of the thin film transistor area TFTA and the gate pad area GPA. The gate metal layers 114a and 114b are one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or these may be an alloy of , and may consist of a single layer or multiple layers. The gate metal layer 114a of the thin film transistor area TFTA becomes a gate electrode, which is the same as the gate line GL. The gate metal layer 114b of the gate pad area GPA becomes a gate pad electrode.

The second embodiment of the present invention implements a thin film transistor array for a digital X-ray detector based on a thin film transistor having a top gate coplanar structure as described above, so that a factor of generating a parasitic capacitance (Cgs) can be reduced. In addition, in the second embodiment of the present invention, since the semiconductor layer of the thin film transistor is formed of an oxide (eg, IGZO) having excellent off current characteristics, the current crowding issue is improved and device characteristics are secured. can do.

A second insulating layer 115 is formed on the buffer layer 111 . The second insulating layer 115 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The second insulating layer 115 may be defined as an interlayer insulating layer. The second insulating layer 115 is formed to cover the gate metal layers 114a and 114b. The second insulating layer 115 has a contact hole exposing the source region and the drain region of the first semiconductor layer 112 and the gate metal layer 114b of the gate pad region GPA.

Data metal layers 116a and 116b are formed on the second insulating layer 115 . The data metal layers 116a and 116b are one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or these may be an alloy of , and may consist of a single layer or multiple layers.

The data metal layer 116a of the data line area DLA becomes a first electrode of the thin film transistor TFT, and the data metal layer 116b of the thin film transistor area TFTA becomes a second electrode of the thin film transistor TFT.

A third insulating layer 117 is formed on the second insulating layer 115 . The third insulating layer 117 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The third insulating layer 117 may be defined as a first passivation layer.

A planarization layer 124 for planarizing a surface is formed on the third insulating layer 117 . The planarization layer 124 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The planarization layer 124 is used to reduce signal interference between the lower electrode 118 of the photodiode PIN formed thereon, the thin film transistor TFT, and signal lines connected thereto.

A fourth insulating layer 125 is formed on the planarization layer 124 . The fourth insulating layer 125 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The fourth insulating layer 125 may be defined as a second passivation layer. The fourth insulating layer 125 has a contact hole exposing the data metal layer 116a of the data line area DLA and the data metal layer 116b of the thin film transistor area TFTA.

A lower connection electrode 118a, a lower electrode 118b, and a reflective electrode 118R are formed on the fourth insulating layer 125 . The lower connection electrode 118a is electrically connected to the data metal layer 116a of the data line area DLA. The lower electrode 118b is electrically connected to the data metal layer 116b of the thin film transistor area TFTA. The lower electrode 118b becomes a cathode electrode of the photodiode PIN. The reflective electrode 118R covers a region corresponding to the channel region (a region between the first electrode and the second electrode of the thin film transistor) of the first semiconductor layer 112 . The reflective electrode 118R serves as a hydrogen barrier and a light shield of the thin film transistor TFT.

The lower connection electrode 118a, the lower electrode 118b, and the reflective electrode 118R are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper. It may be one selected from the group consisting of (Cu) or an alloy thereof, and may consist of a single layer or multiple layers. The lower electrode 118b and the reflective electrode 118R may be formed of the same metal. The reflective electrode 118R is an electrode that extends from the lower electrode 118 or extends from the lower connection electrode 118a.

A second semiconductor layer 119 is formed on the lower electrode 118b of the photodiode region PINA. The second semiconductor layer 119 is formed in a structure in which PINs (P-type semiconductor layer/intrinsic (I) semiconductor layer/N-type semiconductor layer) are stacked.

In the second embodiment of the present invention, due to the use of the planarization film 124, when the second semiconductor layer 119 of the photodiode PIN is formed, a thin film process (low temperature deposition ~ 230°C) using a spin coating process or the like is performed. It is preferable to proceed

The upper electrode 120 is formed on the second semiconductor layer 119 of the photodiode region PINA. The upper electrode 120 may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper electrode 120 becomes the anode electrode of the photodiode PIN.

A fifth insulating layer 121 is formed on the fourth insulating layer 125 . The fifth insulating layer 121 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The fifth insulating layer 121 may be defined as a third passivation layer. The fifth insulating layer 121 is formed to cover the lower connection electrode 118a, the lower electrode 118b, the reflective electrode 118R, and the upper electrode 120 of the photodiode region PINA. The fifth insulating layer 121 has a contact hole exposing the lower connection electrode 118a of the data line area DLA and the upper electrode 120 of the bias line area BLA.

Upper metal layers 122a and 122b are formed on the fifth insulating layer 121 of the data line area DLA and the bias line area BLA. The upper metal layers 122a and 122b are one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or these may be an alloy of , and may consist of a single layer or multiple layers.

The upper metal layer 122a of the data line area DLA is electrically connected to the lower connection electrode 118a of the data line area DLA. The upper metal layer 122b of the bias line area BLA is electrically connected to the upper electrode 120 of the photodiode PIN, which becomes the bias line BL.

The second embodiment of the present invention forms an electrode film that can serve as a hydrogen barrier and a light shield as described above, so that hydrogen influence (possibility of deterioration of oxide thin film transistor) during semiconductor layer processing of photodiode. can be reduced and the incident path of visible light from the top can be blocked. In addition, according to the second embodiment of the present invention, signal interference between the lower electrode 118 of the photodiode PIN, the thin film transistor TFT, and a signal line connected thereto can be reduced.

Hereinafter, another embodiment of the present invention will be described. However, in the following description, the part related to the photo-sensing sub-pixel will be mainly described and the part related to the pad part will be omitted.

<Third embodiment>

10 is a cross-sectional view illustrating a photo-sensing sub-pixel according to a third embodiment of the present invention.

As shown in FIG. 10 , a data line area DLA, a thin film transistor area TFTA, a photodiode area PINA, and a bias line area BLA are defined on the thin film transistor array substrate 110a.

A buffer layer 111 is formed on the thin film transistor array substrate 110a. The buffer layer 111 may be formed to protect a thin film transistor formed in a subsequent process from impurities such as alkali ions leaking from the thin film transistor array substrate 110a. The buffer layer 111 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like, and may be omitted.

A lower electrode 118 is formed on the buffer layer 111 of the photodiode region PINA. The lower electrode 118 becomes a cathode electrode or an anode electrode of the photodiode PIN. The lower electrode 118 is a metal electrode such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or indium tin oxide (ITO). ) or a transparent oxide electrode such as IZO (Indium Zinc Oxide).

A second semiconductor layer 119 is formed on the lower electrode 118 of the photodiode region PINA. The second semiconductor layer 119 is formed in a structure in which PINs (P-type semiconductor layer/intrinsic (I) semiconductor layer/N-type semiconductor layer) are stacked.

The upper electrode 120 is formed on the second semiconductor layer 119 of the photodiode region PINA. The upper electrode 120 becomes an anode electrode or a cathode electrode of the photodiode PIN. The upper electrode 120 is a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO) or molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), It may be formed of a metal electrode such as nickel (Ni) and copper (Cu).

Meanwhile, although not shown, a bias line electrically connected to the lower electrode 118 or the upper electrode 120 of the photodiode area PINA is positioned in the bias line area BLA. The bias line may be formed on the same layer as the lower electrode 118 or the upper electrode 120 , or may be formed on the uppermost insulating layer as shown in FIG. 7 or FIG. 8 .

A first passivation layer 125 is formed on the buffer layer 111 . The first passivation layer 125 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The first passivation layer 125 is formed to cover the upper electrode 120 of the photodiode PIN.

A first semiconductor layer 112 is formed on the first passivation layer 125 of the thin film transistor area TFTA. The first semiconductor layer 112 is made of an oxide such as indium gallium zinc oxide (IGZO) or TiO2, ZnO, WO3, SnO2, or the like.

A first insulating layer 113a is formed on the first semiconductor layer 112 of the thin film transistor area TFTA. The first insulating layer 113a may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The first insulating layer 113a may be defined as a gate insulating layer. The first insulating layer 113a is formed in an island shape.

A gate metal layer 114a is formed on the first insulating layer 113a of the thin film transistor area TFTA. The gate metal layer 114a is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The gate metal layer 114a of the thin film transistor area TFTA becomes a gate electrode.

According to the present invention, since a thin film transistor array for a digital X-ray detector is implemented based on a thin film transistor having a top gate coplanar structure as described above, a factor of generating a parasitic capacitance (Cgs) can be reduced. In addition, in the present invention, since the semiconductor layer of the thin film transistor is formed of an oxide (eg, IGZO) having excellent off current characteristics, it is possible to improve the current crowding issue and secure device characteristics.

A second insulating layer 115 is formed on the first passivation layer 125 . The second insulating layer 115 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The second insulating layer 115 may be defined as an interlayer insulating layer. The second insulating layer 115 is formed to cover the gate metal layer 114a. The second insulating layer 115 has a contact hole exposing the source region, the drain region, and the upper electrode 120 of the first semiconductor layer 112 .

Meanwhile, the second insulating layer 115 may have a height similar to or the same as that of the first insulating layer 113 . In this case, the second insulating film 115 is defined as a planarization film, and may be made of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. there is. When the second insulating layer 115 is used as a planarization layer, it is possible to reduce the thickness of the array while protecting the thin film transistor TFT.

Data metal layers 116a and 116b are formed on the second insulating layer 115 . The data metal layers 116a and 116b are one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or these may be an alloy of , and may consist of a single layer or multiple layers.

The data metal layer 116a of the data line area DLA becomes a first electrode of the thin film transistor TFT, and the data metal layer 116b of the thin film transistor area TFTA becomes a second electrode of the thin film transistor TFT. The data metal layer 116b of the thin film transistor area TFTA extends to the photodiode area PINA and is electrically connected to the upper electrode 120 of the photodiode PIN.

A second passivation layer 117 is formed on the second insulating layer 115 . The second passivation layer 117 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The second passivation layer 117 is formed to cover the data metal layers 116a and 116b. The third insulating layer 117 has a contact hole exposing the data metal layer 116a of the data line area DLA.

An upper metal layer 122a is formed on the second passivation layer 117 of the data line area DLA. The upper metal layer 122a is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The upper metal layer 122a is electrically connected to the data metal layer 116a of the data line area DLA, which becomes the data line DL.

In the third embodiment of the present invention, since the photodiode (PIN) is formed first, the hydrogen influence (possibility of deterioration of the oxide thin film transistor) can be reduced and the electrode film that can serve as a light shield can be omitted. can In addition, in the third embodiment of the present invention, since the photodiode PIN is formed first, the signal between the lower electrode 118 or the upper electrode 120 of the photodiode PIN and the thin film transistor TFT and the signal line connected thereto interference can be reduced. In addition, in the third embodiment of the present invention, since the photodiode PIN is formed at a position close to the substrate 110a, flatness and uniformity can be increased, thereby improving signal detection capability.

<Fourth embodiment>

11 is a cross-sectional view illustrating a photo-sensing sub-pixel according to a fourth embodiment of the present invention.

11 , a data line area DLA, a thin film transistor area TFTA, a photodiode area PINA, and a bias line area BLA are defined on the thin film transistor array substrate 110a.

A buffer layer 111 is formed on the thin film transistor array substrate 110a. The buffer layer 111 may be formed to protect a thin film transistor formed in a subsequent process from impurities such as alkali ions leaking from the thin film transistor array substrate 110a. The buffer layer 111 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like, and may be omitted.

A lower electrode 118 is formed on the buffer layer 111 of the photodiode region PINA. The lower electrode 118 becomes a cathode electrode or an anode electrode of the photodiode PIN. The lower electrode 118 is a metal electrode such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or indium tin oxide (ITO). ) or a transparent oxide electrode such as IZO (Indium Zinc Oxide).

A second semiconductor layer 119 is formed on the lower electrode 118 of the photodiode region PINA. The second semiconductor layer 119 is formed in a structure in which PINs (P-type semiconductor layer/intrinsic (I) semiconductor layer/N-type semiconductor layer) are stacked.

The upper electrode 120 is formed on the second semiconductor layer 119 of the photodiode region PINA. The upper electrode 120 becomes an anode electrode or a cathode electrode of the photodiode PIN. The upper electrode 120 is a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO) or molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), It may be formed of a metal electrode such as nickel (Ni) and copper (Cu).

Meanwhile, although not shown, a bias line electrically connected to the lower electrode 118 or the upper electrode 120 of the photodiode area PINA is positioned in the bias line area BLA. The bias line may be formed on the same layer as the lower electrode 118 or the upper electrode 120 , or may be formed on the uppermost insulating layer as shown in FIG. 7 or FIG. 8 .

A planarization layer 124 for planarizing a surface is formed on the buffer layer 111 . The planarization layer 124 is formed to cover the upper electrode 120 and the buffer layer 111 of the photodiode PIN. The planarization layer 124 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The planarization layer 124 is used to reduce signal interference between the upper electrode 120 of the photodiode PIN and the like, the thin film transistor TFT, and the signal line connected thereto.

A first passivation layer 125 is formed on the planarization layer 124 . The first passivation layer 125 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The first passivation layer 125 may be omitted depending on the material of the planarization layer 124 .

A first semiconductor layer 112 is formed on the first passivation layer 125 of the thin film transistor area TFTA. The first semiconductor layer 112 is made of an oxide such as indium gallium zinc oxide (IGZO) or TiO2, ZnO, WO3, SnO2, or the like.

A first insulating layer 113a is formed on the first semiconductor layer 112 of the thin film transistor area TFTA. The first insulating layer 113a may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The first insulating layer 113a may be defined as a gate insulating layer. The first insulating layer 113a is formed in an island shape.

A gate metal layer 114a is formed on the first insulating layer 113a of the thin film transistor area TFTA. The gate metal layer 114a is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The gate metal layer 114a of the thin film transistor area TFTA becomes a gate electrode.

According to the present invention, since a thin film transistor array for a digital X-ray detector is implemented based on a thin film transistor having a top gate coplanar structure as described above, a factor of generating a parasitic capacitance (Cgs) can be reduced. In addition, in the present invention, since the semiconductor layer of the thin film transistor is formed of an oxide (eg, IGZO) having excellent off current characteristics, it is possible to improve the current crowding issue and secure device characteristics.

A second insulating layer 115 is formed on the first passivation layer 125 . The second insulating layer 115 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The second insulating layer 115 may be defined as an interlayer insulating layer. The second insulating layer 115 is formed to cover the gate metal layer 114a. The second insulating layer 115 has a contact hole exposing the source region, the drain region, and the upper electrode 120 of the first semiconductor layer 112 .

Data metal layers 116a and 116b are formed on the second insulating layer 115 . The data metal layers 116a and 116b are one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or these may be an alloy of , and may consist of a single layer or multiple layers.

The data metal layer 116a of the data line area DLA becomes a first electrode of the thin film transistor TFT, and the data metal layer 116b of the thin film transistor area TFTA becomes a second electrode of the thin film transistor TFT. The data metal layer 116b of the thin film transistor area TFTA extends to the photodiode area PINA and is electrically connected to the upper electrode 120 of the photodiode PIN.

A second passivation layer 117 is formed on the second insulating layer 115 . The second passivation layer 117 may be formed of a single layer or multiple layers of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx). The second passivation layer 117 is formed to cover the data metal layers 116a and 116b. The second passivation layer 117 has a contact hole exposing the data metal layer 116a of the data line area DLA.

An upper metal layer 122a is formed on the second passivation layer 117 of the data line area DLA. The upper metal layer 122a is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The upper metal layer 122a is electrically connected to the data metal layer 116a of the data line area DLA, which becomes the data line DL.

In the fourth embodiment of the present invention, since the photodiode (PIN) is formed first, the effect of hydrogen (possibility of deterioration of the oxide thin film transistor) can be reduced and the electrode film that can serve as a light shield can be omitted. can In addition, in the fourth embodiment of the present invention, since the photodiode PIN is formed first, the signal between the lower electrode 118 or the upper electrode 120 of the photodiode PIN and the thin film transistor TFT and the signal line connected thereto interference can be reduced. In addition, in the third embodiment of the present invention, since the photodiode PIN is formed at a position close to the substrate 110a, flatness and uniformity can be increased, thereby improving signal detection capability.

Meanwhile, in the embodiments of the present invention, a thin film transistor having a top gate inverted coplanar structure is taken as an example, but this is only an example and may be implemented in a structure such as a batam gate inverted coplanar structure. .

As described above, the present invention has the following effects when manufacturing and implementing a thin film transistor array substrate for a digital X-ray detector. Since the present invention is implemented based on a thin film transistor having a coplanar structure, it is possible to reduce the generation factor of the parasitic capacitance (Cgs) (reduction of power consumption). In addition, since the semiconductor layer of the thin film transistor is formed of an oxide (eg, IGZO) with excellent off current characteristics, the present invention improves signal detection ability according to noise reduction and improves the current crowding issue. It is possible to improve the characteristics of the device. In addition, the present invention forms an electrode film that can serve as a hydrogen barrier and a light shield to reduce the effect of hydrogen (possibility of deterioration of the oxide thin film transistor) during the semiconductor layer process of the photodiode and from the top. It can block the incident path of visible light.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

PIN: photodiode TFT: thin film transistor
111: buffer layer 112: first semiconductor layer
113a, 113b: first insulating layer 114a, 114b: gate metal layer
115: second insulating layer 116a, 116b, 116c, 116d: data metal layer
117: third insulating layer 118: lower electrode
118R: reflective electrode 119: second semiconductor layer
120: upper electrode 121: fourth insulating film

Claims (7)

Board;
a thin film transistor having a coplanar structure disposed on the substrate and having a first semiconductor layer of oxide, a gate electrode, a first electrode, and a second electrode;
a protective film covering the thin film transistor;
a reflective electrode disposed on the passivation layer and covering a region corresponding to a channel region of the thin film transistor; and
Digital X-ray including a photodiode positioned on the passivation layer and having a lower electrode connected to the second electrode of the thin film transistor, a second semiconductor layer positioned on the lower electrode, and an upper electrode positioned on the second semiconductor layer A thin film transistor array substrate for a detector. According to claim 1,
The reflective electrode is
A thin film transistor array substrate for a digital X-ray detector, characterized in that extending from the lower electrode. Board;
a thin film transistor having a coplanar structure disposed on the substrate and having a first semiconductor layer of oxide, a gate electrode, a first electrode, and a second electrode;
a first passivation layer covering the thin film transistor;
a planarization layer disposed on the first passivation layer and planarizing a surface thereof;
a second passivation layer disposed on the planarization layer;
a lower connection electrode positioned on the second passivation layer and connected to the first electrode of the thin film transistor;
a reflective electrode positioned on the second passivation layer and covering a region corresponding to a channel region of the thin film transistor; and
a photodiode having a lower electrode positioned on the second passivation layer and connected to the second electrode of the thin film transistor, a second semiconductor layer positioned on the lower electrode, and an upper electrode positioned on the second semiconductor layer,
The photodiode is a thin film transistor array substrate for a digital X-ray detector positioned below the thin film transistor. Board;
a photodiode having a lower electrode positioned on the substrate, a second semiconductor layer positioned on the lower electrode, and an upper electrode positioned on the second semiconductor layer;
an insulating film covering the photodiode; and
and a thin film transistor of a coplanar structure disposed on the insulating film and having a first semiconductor layer of oxide, a gate electrode, a first electrode, and a second electrode electrically connected to the upper electrode,
The photodiode is a thin film transistor array substrate for a digital X-ray detector positioned below the thin film transistor. 5. The method of claim 4,
The insulating film is
a planarization film covering the photodiode and planarizing a surface thereof;
A thin film transistor array substrate for a digital X-ray detector further comprising a first passivation layer disposed on the planarization layer. 4. The method of claim 3,
The reflective electrode is
A thin film transistor array substrate for a digital X-ray detector extending from the lower electrode and having a flat surface structure on the second passivation layer. 5. The method of claim 4,
The photodiode is
A thin film transistor array substrate for a digital X-ray detector positioned between the buffer layer positioned on the substrate and the insulating film.

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