KR20200137307A - Thin film transistor array substrate for digital x-ray detector and the digital x-ray detector including the same and the manufacturing method thereof - Google Patents

Abstract

The present invention provides a thin film transistor array substrate for a digital X-ray detector, a digital X-ray detector including the same and a manufacturing method thereof which can minimize creation of parasitic capacitors while maximally increasing a fill factor. Specifically, the present invention forms a data line on a lower portion of an active layer of a thin film transistor, forms a first electrode and a second electrode of the thin film transistor in opposite directions, and forms the first electrode and the second electrode in different layers to maximally separate the data line and a PIN diode in a vertical direction to minimize parasitic capacitors which can be created between the data line and the PIN diode. Also, since the distance between the data line and the PIN diode is maximum in the vertical direction, creation of parasitic capacitors can be minimized even if the horizontal distance between the data line and the PIN diode is short to maximally increase the area of the PIN diode in the horizontal direction to maximally increase the fill factor of a digital X-ray detector.

Description

A thin film transistor array substrate for a digital X-ray detector, and a digital X-ray detector including the same, and a method of manufacturing the same.

The present invention relates to a thin film transistor array substrate for a digital X-ray detector, a digital X-ray detector including the same, and a method of manufacturing the same.

More specifically, to provide a thin film transistor array substrate for a digital X-ray detector capable of minimizing the occurrence of parasitic capacitors while increasing the fill factor as much as possible, a digital X-ray detector including the same, and a method of manufacturing the same.

Because X-rays have a short wavelength, they can easily penetrate the subject. The amount of X-ray transmission is determined according to the density inside the subject. Therefore, the internal structure of the subject can be observed by detecting the amount of X-rays transmitted through the subject.

One of the x-ray examination methods used for medical purposes is the film printing method. However, in the case of the film printing method, it takes a lot of time to check the result because the result can be confirmed only after the film is taken and the printing process is performed. In particular, in the case of the film printing method, there are many difficulties in storing and preserving the printed film.

Accordingly, recently, a digital X-ray detector (DXD) using a thin film transistor has been developed and is widely used for medical purposes.

A digital X-ray detector refers to a device that detects the amount of X-rays transmitted through an object and displays an internal state of an object to the outside through a display.

Therefore, the digital X-ray detector has the advantage of being able to display the internal structure of a subject without using a separate film and photo paper, and that the result can be checked in real time immediately after taking an X-ray.

The fill factor of the digital X-ray detector refers to a ratio occupied by the light-receiving area of the digital X-ray detector per pixel, and may be specifically defined as a ratio of the area of the PIN diode to the area of one pixel.

If the fill factor is decreased, even if the same amount of visible light is irradiated to the PIN diode, the converted electric signal amount is also reduced due to the reduction in the light-receiving area, so that the performance of the overall digital X-ray detector may be degraded.

Therefore, in order to improve the performance of the digital x-ray detector, it is important to increase the fill factor of the digital x-ray detector.

However, if the area of the PIN diode is increased in order to increase the fill factor of the digital X-ray detector, the distance between the PIN diode and the data line becomes closer, so an unintended parasitic capacitor occurs between the PIN diode and the data line. Performance may be degraded.

Accordingly, the inventors of the present invention invented a thin film transistor array substrate for a digital X-ray detector capable of minimizing parasitic capacitors that may occur between a data line and a PIN diode while increasing the fill factor as much as possible, a digital X-ray detector including the same, and a manufacturing method thereof. .

An object of the present invention is to provide a thin film transistor array substrate for a digital X-ray detector capable of minimizing parasitic capacitors that may occur between a data line and a PIN diode, a digital X-ray detector including the same, and a method of manufacturing the same.

It is also an object of the present invention to provide a thin film transistor array substrate for a digital X-ray detector capable of increasing the fill factor as much as possible by increasing the area of the PIN diode, a digital X-ray detector including the same, and a method of manufacturing the same.

In addition, an object of the present invention is a thin film transistor array substrate for a digital X-ray detector capable of forming a light blocking layer capable of protecting the lower surface of the active layer of the thin film transistor from X-rays without adding a separate process, and a digital X-ray detector including the same And to provide a method of manufacturing the same.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention that are not mentioned can be understood by the following description, and will be more clearly understood by examples of the present invention. In addition, it will be easily understood that the objects and advantages of the present invention can be realized by the means shown in the claims and combinations thereof.

According to an embodiment of the present invention, a thin film transistor array substrate for a digital X-ray detector capable of minimizing the occurrence of parasitic capacitors while increasing a fill factor as much as possible and a digital X-ray detector including the same are provided.

A thin film transistor including a first electrode, a second electrode, a gate electrode, and an active layer is formed on a base substrate, and a PIN diode connected to the thin film transistor is formed on the thin film transistor. The first electrode and the second electrode are respectively connected to the active layer in opposite directions, the second electrode is connected to the PIN diode, and the first electrode and the second electrode are formed on different layers.

In addition, a plurality of thin film transistors including a first electrode, a second electrode, a gate electrode, and an active layer on a base substrate in which a plurality of pixel regions are defined by a plurality of gate lines and a plurality of data lines crossing each other orthogonal to each other, and A plurality of PIN diodes connected to each of the thin film transistors are formed on the thin film transistor. The first electrode and the second electrode are respectively connected to the active layer in opposite directions, the second electrode is connected to the PIN diode, the first electrode is in the data line, and the data line is formed under the active layer. In this case, the first electrode and the second electrode are formed on different layers.

In this case, as an embodiment, the second electrode is connected to the lower electrode of the PIN diode including the lower electrode, the PIN layer, and the upper electrode, and the second electrode is the PIN layer of the PIN diode including the PIN layer and the upper electrode. The connection is made in another embodiment. In another embodiment, the active layer includes a channel region and a conductor and regions interposed between the channel region, and the first electrode extends to the channel region.

In addition, a thin film transistor array substrate for a digital X-ray detector capable of minimizing the occurrence of parasitic capacitors while increasing the fill factor as much as possible according to an embodiment of the present invention and a method of manufacturing a digital X-ray detector including the same are provided.

Forming a first electrode on a base substrate, forming a buffer layer to cover the first electrode, forming an active layer on the buffer layer to be connected to the first electrode, a gate insulating layer and a gate electrode on the active layer And forming a second electrode to be connected to the other side of the active layer.

In this case, as an embodiment, forming a lower electrode to be connected to the second electrode and forming a PIN layer and an upper electrode on the lower electrode are used as an embodiment, and the PIN on the second electrode is connected to the second electrode. Another embodiment includes the step of forming a layer and an upper electrode.

According to the present invention, the data line is formed under the active layer of the thin film transistor and the first electrode and the second electrode of the thin film transistor are formed in opposite directions, so that the data line and the PIN diode are spaced apart in the vertical direction as much as possible. Parasitic capacitors that may occur between PIN diodes can be minimized.

In addition, according to the present invention, since the distance between the data line and the PIN diode is maximally separated in the vertical direction, generation of parasitic capacitors can be minimized even when the horizontal distance between the data line and the PIN diode is close, so that the area of the PIN diode is maximized in the horizontal direction. By increasing it, the fill factor of the digital x-ray detector can also be increased as much as possible.

In addition, according to the present invention, by forming the first electrode of the thin film transistor to extend to the channel region of the active layer, the first electrode can also serve as a light blocking layer, without adding a separate process for forming the light blocking layer. The lower surface of the active layer of the thin film transistor can be effectively protected from X-rays.

In addition to the above-described effects, specific effects of the present invention will be described together while describing specific details for carrying out the present invention.

1 is a block diagram schematically illustrating a digital X-ray detector.
2 is a plan view of a thin film transistor array substrate for a digital X-ray detector and a partial area of a digital X-ray detector including the same according to an embodiment of the present invention.
3 is a cross-sectional view of a thin film transistor array substrate for a digital X-ray detector and a partial region of a digital X-ray detector including the same according to an embodiment of the present invention.
4 is a cross-sectional view of a thin film transistor array substrate for a digital X-ray detector and a partial region of a digital X-ray detector including the same according to another embodiment of the present invention.
5 is a cross-sectional view of a thin film transistor array substrate for a digital X-ray detector and a partial region of a digital X-ray detector including the same according to still another embodiment of the present invention.
6A to 6L are flowcharts illustrating a thin film transistor array substrate for a digital X-ray detector and a method of manufacturing a digital X-ray detector including the same according to an embodiment of the present invention.
7A to 7J are flowcharts illustrating a thin film transistor array substrate for a digital X-ray detector and a method of manufacturing a digital X-ray detector including the same according to another embodiment of the present invention.

The above-described objects, features, and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, one of ordinary skill in the art to which the present invention pertains will be able to easily implement the technical idea of the present invention. In describing the present invention, when it is determined that a detailed description of known technologies related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description will be omitted. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar elements.

Hereinafter, it means that an arbitrary component is disposed on the "top (or lower)" of the component or the "top (or lower)" of the component, the arbitrary component is arranged in contact with the top (or bottom) of the component. In addition, it may mean that other components may be interposed between the component and any component disposed on (or under) the component.

In addition, when a component is described as being "connected", "coupled" or "connected" to another component, the components may be directly connected or connected to each other, but other components are "interposed" between each component. It is to be understood that "or, each component may be "connected", "coupled" or "connected" through other components.

Hereinafter, a thin film transistor array substrate for a digital X-ray detector, a digital X-ray detector including the same, and a method of manufacturing the same according to some embodiments of the present invention will be described.

1 is a block diagram schematically illustrating a digital X-ray detector. The digital X-ray detector may include a thin film transistor array 110, a gate driving unit 120, a bias supply unit 130, a power voltage supply unit 140, a readout circuit unit 150, and a timing control unit 160.

The thin film transistor array 110 includes a plurality of gate lines (Gate Line, GL) arranged in one direction and a plurality of data lines (Data Line, DL) arranged in one direction so as to be orthogonal to the gate lines GL. It may include a plurality of cell areas defined by.

The cell regions are arranged in a matrix form, and each cell region may include a pixel region in which the photo-sensing pixels Pixel and P are formed. The thin film transistor array 110 may detect X-rays emitted from an X-ray source, photoelectrically convert the detected X-rays, and output an electrical detection signal.

Each photo-sensing pixel has a PIN diode that converts light in the visible light region converted from X-ray by a scintillator to an electronic signal and outputs it, and a readout circuit unit ( 150) may include a thin film transistor (TFT), respectively. One side of the PIN diode may be connected to the thin film transistor and the other side may be connected to a bias line (BL).

A gate electrode of the thin film transistor may be connected to a gate line GL transmitting a scan signal, and a source/drain electrode may be connected to a PIN diode and a data line DL transmitting a detection signal output from the PIN diode, respectively. The bias lines BL may be arranged parallel to the data lines DL.

The gate driver 120 may sequentially apply gate signals to the thin film transistors of the photo-sensing pixels through the gate lines GL. The thin film transistors of the photo-sensing pixels may be turned on in response to a gate signal having a gate-on voltage level.

The bias supply unit 130 may apply a driving voltage to the photo-sensing pixels through the bias lines BL. The bias supply unit 130 may selectively apply a reverse bias or a forward bias to the PIN diode.

The readout circuit unit 150 may read out a detection signal transmitted from the turned-on thin film transistor in response to a gate signal of the gate driver. That is, the detection signal output from the PIN diode may be input to the readout circuit unit 150 through the thin film transistor and the data line DL.

The readout circuit unit 150 may read out the detection signals output from the photo-sensing pixels in the offset readout section for reading out the offset image and the X-ray readout section for reading out the detection signal after X-ray exposure.

The readout circuit unit 150 may include a signal detector and a multiplexer. The signal detection unit includes a plurality of amplifying circuit units corresponding to the data lines DL one-to-one, and each amplifying circuit unit may include an amplifier, a capacitor, and a reset element.

The timing controller 160 may control the operation of the gate driver 120 by generating a start signal and a clock signal and supplying it to the gate driver 120. In addition, the timing control unit 160 may control the operation of the readout circuit unit 150 by generating a readout control signal, a readout clock signal, and the like and supplying it to the readout circuit unit 150.

2 and 3 are plan and cross-sectional views, respectively, of a thin film transistor array substrate for a digital X-ray detector and a portion of a digital X-ray detector including the same according to an embodiment of the present invention.

Hereinafter, an exemplary embodiment of the present invention will be described in detail centering on a PIN diode and a thin film transistor corresponding to one pixel with reference to FIGS. 2 and 3, and the same may be applied to adjacent pixels unless otherwise specified. .

First, a thin film transistor array substrate for a digital X-ray detector and a digital X-ray detector including the same according to an embodiment of the present invention include a base substrate 210.

The base substrate 210 may be a substrate made of a glass material, but is not limited thereto. When applied to a flexible digital X-ray detector, a substrate made of a polyimide material having flexibility may be used.

A plurality of cell regions are defined on the base substrate 210 by a plurality of gate lines 223 and a plurality of data lines 211 crossing each other so as to be orthogonal to each other. A plurality of pixel regions are defined by corresponding pixels P to each cell region. A region corresponding to the gate line 223 and the data line 211 may be defined as a boundary region between pixel regions.

Each of the thin film transistors 220 and the PIN diodes 230 are arranged to correspond to each other, so that a plurality of thin film transistors 220 and a plurality of PIN diodes 230 are formed on an array substrate having a plurality of pixel regions. I can.

A thin film transistor 220 including a first electrode 211a, a second electrode 225a, a gate electrode 223a, and an active layer 221 is formed on the base substrate 210.

In this case, the first electrode 211a and the second electrode 225a are respectively connected to the active layer 221 in opposite directions. Specifically, the first electrode 211a is connected to the lower surface of one side of the active layer 221 to be formed in the direction in which the base substrate 210 is, and the second electrode 225a is connected to the upper surface of the other side of the active layer 221. It may be connected and formed in a direction in which the PIN diode 230 is located.

That is, based on the active layer 221, the first electrode 211a may be formed under the active layer 221, and the second electrode 225a may be formed over the active layer 221.

The first electrode 211a is included in the data line 211, and by forming the data line 211 on the base substrate 210, the first electrode 211a may also be formed at the same time. Specifically, the first electrode 211a may coincide with the data line 211, and a predetermined area of the data line 211 corresponding to the lower surface of one side of the active layer 221 is defined as the first electrode 211a. I can.

That is, the first electrode 211a and the data line 211 are not physically separated, and a partial region of the data line 211 may be defined as the first electrode 211a.

The data line 211 and the first electrode 211a are a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be made of one selected from or an alloy thereof, but is not limited thereto.

When a glass substrate is used as the base substrate 210, the data line 211 and the first electrode 211a may be formed by being deposited to directly contact the organic substrate.

On the other hand, when a flexible substrate made of a flexible material such as polyimide is used as the base substrate 210, a buffer layer (not shown) is formed on the base substrate 210 and then the data line 211 and the first electrode 211a are formed. Can be formed.

In this case, the buffer layer (not shown) may be formed of an inorganic material such as a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx), or may be formed as a multi-layered multi-buffer layer.

Since the first electrode 211a coincides with the data line 211 and is in the data line 211, the first electrode 211a and the PIN diode 230 are compared with a structure in which the data line and the first electrode are formed as separate electrodes. ), it is possible to minimize the occurrence of parasitic capacitors as the maximum distance between them is possible.

In addition, since the first electrode 211a is in the data line 211 corresponding to the boundary area of the pixel area, it is possible to minimize the pixel area covered by the first electrode 211a, thereby reducing the fill factor of the PIN diode 230. It can also be advantageous for securing.

The active layer 221 is on the first electrode 211a, and the first electrode 211a is connected to a lower surface of one side of the active layer 221.

In this case, there is a buffer layer 212 between the first electrode 211a and the active layer 221, so that the first electrode 211a and the active layer 221 are a first contact hole 212h that is a contact hole of the buffer layer 212 They can be connected to each other through

Specifically, the active layer 221 may be formed on the buffer layer 212 and connected to the first electrode 211a through the first contact hole 212h. Accordingly, a partial area of the data line 211 exposed to the outside by the first contact hole 212h may become the first electrode 211a.

The buffer layer 212 may be formed of an inorganic material such as a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx), or may be formed as a multi-layered multi-buffer layer.

The active layer 221 may be formed of an oxide semiconductor material such as Indium Gallium Zinc Oxide (IGZO), but is not limited thereto, and is formed of Low Temperature Polycrystalline Silicon (LTPS) or amorphous silicon (a-Si). It could be.

The active layer 221 may include a channel region 221a and conductive regions with the channel region 221a interposed therebetween. Specifically, the conductive regions can be divided into a first conductive region 221b connected in direct contact with the first electrode 211a and a second conductive region 221c connected in direct contact with the second electrode 225a. have.

Conducting regions of the active layer 221 may be formed by conducting conductorization at both ends of the active layer 221, and the conductorization treatment method is various methods such as dry etching, hydrogen plasma treatment, and helium plasma treatment. Can be used.

A gate electrode 223a is formed on the active layer 221, and a gate insulating layer 222 is formed between the active layer 221 and the gate electrode 223a to form the active layer 221 and the gate electrode 223a. They can insulate each other.

That is, the gate electrode 223a may be formed on the gate insulating layer 222 to correspond to the channel region 221a of the active layer 221. The gate electrode 223a is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof It may be, and may be made of a single layer or multiple layers.

The gate electrode 223a may be formed to extend from the gate line 223, and the gate electrode 223a may be formed in the gate line 223 by matching the gate line 223 and the gate electrode 223a. Accordingly, the gate line 223 and the gate electrode 223a may be formed on the same layer.

The gate insulating layer 222 made of an inorganic material is formed to correspond to the gate electrode 223a, and may be formed to have the same or larger area as the gate electrode 223a for effective insulation.

The gate electrode 223a and the gate insulating layer 222 may be formed to correspond to the center of the active layer 221. Accordingly, the region of the active layer 221 exposed without being covered by the gate electrode 223a, that is, both ends of the active layer 221 other than the channel region 221a, are formed with the first conductive region 221b and the second It may be a conductive region 221c.

In this case, the first conductive region 221b becomes a drain region connected to the first electrode 211a, which is a drain electrode, and the second conductive region 221c is a source electrode. 2 It may be a source region connected to the electrode 225a.

As described above, unlike the first electrode 211a connected to one lower surface of the active layer 221, the second electrode 225a is formed to be connected to the other upper surface of the active layer 221.

In this case, an interlayer insulating layer 224 made of an inorganic material may be formed on the gate electrode 223a. A second electrode 225a is formed on the interlayer insulating layer 224 so that the second electrode 225a and the active layer 221 may be connected to each other through the second contact hole 224h, which is a contact hole of the interlayer insulating layer 224. have.

The second electrode 225a is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or It may be made of an alloy, but is not limited thereto.

In this way, the first electrode 211a and the active layer 221 of the thin film transistor 220 are formed to sandwich the buffer layer 212, and the second electrode 225a and the active layer 221 are interlayer insulating layers 224 By being formed so as to intervene, the first electrode 211a and the second electrode 225a may be formed on different layers.

That is, the first electrode 211a and the second electrode 225a are in different layers and are formed in opposite directions, so that the distance between the first electrode 211a and the second electrode 225a is as far apart as possible. I can. In addition, since the first electrode 211a is formed on the same layer as the data line 211, the distance between the data line 211 and the second electrode 225a may be formed to be as far apart as possible.

A first protective layer 226 may be formed on the thin film transistor 220 to cover the entire surface of the base substrate 210. The first protective layer 226 may be formed of an inorganic material such as a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx), but is not limited thereto.

The first protective layer 226 may serve to protect the lower thin film transistor 220, particularly the active layer 221.

A PIN diode 230 is formed on the first passivation layer 226 to be connected to the lower thin film transistor 220. The PIN diode 230 may be disposed in the pixel area.

The PIN diode 230 includes a lower electrode 231 connected to the thin film transistor 220, a PIN layer 232 on the lower electrode 231, and an upper electrode 233 on the PIN layer 232. I can.

The lower electrode 231 may serve as a pixel electrode in the PIN diode 230. The lower electrode 231 is one of an opaque metal such as molybdenum (Mo) or a transparent oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or ZnO (Zinc Oxide) according to the characteristics of the PIN diode 230 It can be made of the above materials.

The lower electrode 231 is connected to contact the second electrode 225a of the thin film transistor 220 through a third contact hole 226h, which is a contact hole of the first protective layer 226, so that the thin film transistor 220 is a PIN It may be connected to the diode 230.

A PIN layer 232 for converting visible light converted from X-rays into electrical signals through a scintillator may be formed on the lower electrode 231. The PIN layer 232 includes an N (Negative)-type semiconductor layer 232c containing N-type impurities, an I (Intrinsic)-type semiconductor layer 232b containing no impurities, and a P (positive)-type semiconductor layer 232b containing P-type impurities. ) Type semiconductor layers 232a may be sequentially stacked to be formed.

The I-type semiconductor layer 232b may be formed to be relatively thicker than the N-type semiconductor layer 232c and the P-type semiconductor layer 232a. The PIN layer 232 is made to include a material capable of converting X-rays emitted from an X-ray source into an electrical signal. For example, a-Se, HgI2, CdTe, PbO, PbI2, BiI3, GaAs, Ge Materials may be included.

An upper electrode 233 may be formed on the PIN layer 232. The upper electrode 233 is made of one or more of transparent oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ZnO (Zinc Oxide) to improve the fill factor of the PIN diode 230. I can.

A second protective layer 234 may be formed on the PIN diode 230 to cover the entire surface of the base substrate 210. The second protective layer 234 may be formed of an inorganic material such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx), but is not limited thereto.

A bias electrode 243 may be formed on the second protective layer 234 on the PIN diode 230. The bias electrode 243 is connected to the upper electrode 233 of the PIN diode 230 through a fourth contact hole 234h, which is a contact hole of the second protective layer 234, to apply a bias voltage to the PIN diode 230. Can do it.

The bias electrode 243 may be formed by branching from the bias line 241 arranged parallel to the data line 211.

A third protective layer 244 may be formed on the bias electrode 243 to cover the entire surface of the base substrate 210. The third protective layer 244 may be formed of an inorganic material such as a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx), but is not limited thereto.

A scintillator layer 250 may be formed on the third protective layer 244 to cover the PIN diode 230.

When the scintillator layer 250 is directly deposited on the thin film transistor array substrate and formed, planarization of the upper surface of the array substrate may be required. In this case, by forming a planarization layer made of an organic material such as PAC (Photo Acryl) to planarize the top surface, the scintillator layer 250 may be easily formed by evaporation of the scintillator.

The digital x-ray detector 200 according to the present invention operates as follows.

X-rays irradiated to the digital X-ray detector 200 are converted into visible light in the scintillator layer 250. Light in the visible region is converted into an electronic signal in the PIN layer 232 of the PIN diode 230.

Specifically, when the PIN layer 232 is irradiated with light in the visible region, the I-type semiconductor layer 232b becomes depleted by the P-type semiconductor layer 232a and the N-type semiconductor layer 232c. An electric field is generated. In addition, holes and electrons generated by light are drifted by an electric field and are collected in the P-type semiconductor layer 232a and the N-type semiconductor layer 232c, respectively.

The PIN diode 230 converts light in the visible light region into an electronic signal and transmits it to the thin film transistor 220. The transmitted electronic signal is displayed as an image signal through the data line 211 connected to the thin film transistor 220.

The thin film transistor array substrate for a digital X-ray detector and a digital X-ray detector including the same according to an embodiment of the present invention have the following advantageous effects compared to the prior art.

In the case of a conventional structure in which the first electrode and the second electrode of the thin film transistor are formed in the same direction on the active layer, the data line is also formed on the same layer as the first electrode and the second electrode.

In the case of such a conventional structure, since the vertical distance between the lower electrode of the PIN diode and the data line is close, in order to minimize the occurrence of parasitic capacitors, it is difficult to increase the area of the PIN diode to a certain level or more, so that there is a limitation in improving the fill factor.

In contrast, in the case of the present invention, the data line 211 is formed under the active layer 221 of the thin film transistor 220 and the first electrode 211a and the second electrode 225a of the thin film transistor 220 are opposite to each other. By forming the data line 211 and the first electrode 211a, the lower electrode 231 of the PIN diode 230 can be spaced apart in the vertical direction as much as possible.

In particular, in the case of the data line 211, the total area occupied by the data line 211 is large, and in the case of a signal applied to the data line 211, interference with a signal applied to the lower electrode 231 of the PIN diode 230 It is more important to reduce the generation of parasitic capacitors between the data line 211 and the lower electrode 231 of the PIN diode 230 because the noise is greater.

Accordingly, due to the arrangement structure of the data line 211 and the first electrode 211a and the lower electrode 231 of the PIN diode 230 further spaced apart in the vertical direction as in the present invention, the data line 211 and the PIN diode 230 It is possible to minimize the occurrence of parasitic capacitors that may be formed between the lower electrodes 231 of ).

In addition, in the case of the present invention, even if the horizontal distance between the data line 211 and the PIN diode 230 is close due to the arrangement structure of the data line 211 and the PIN diode 230 having the maximum distance in the vertical direction, the parasitic capacitor is Since the occurrence is minimized, the fill factor of the digital X-ray detector can be increased as much as possible by increasing the area of the PIN diode 230 in the horizontal direction as much as possible.

Accordingly, according to the present invention, the PIN diode 230 covers at least a portion of the gate electrode 223a and the second electrode 225a of the thin film transistor 220 in the pixel region, and the active layer 221. Since the area of the diode 230 is increased, the fill factor can be increased as much as possible.

Specifically, the PIN diode 230 may be formed to cover even the channel region 221a of the active layer 221, thereby increasing the fill factor as much as possible.

In this case, since the PIN diode 230 covering the active layer 221 absorbs X-rays that may be directly irradiated to the active layer 221, the reliability of the digital X-ray detector 200 may be further increased.

A thin film transistor array substrate for a digital X-ray detector having a structure according to an exemplary embodiment of the present invention and a digital X-ray detector including the same can clearly see the effect compared to the conventional structure through the following experimental results.

The comparative example differs from the embodiment of the present invention in that the data line is formed on the active layer of the thin film transistor so that the first electrode and the second electrode are formed identically in the direction of the top surface of the active layer. Arrangement of the remaining components was the same as in the embodiment.

The embodiments have the structure according to FIG. 3 described above, but the horizontal distance d between the data line and the lower electrode of the PIN diode as shown in FIG. 2 is different from each other.

division Distance between data line and lower electrode of PIN diode (d) Capacitor (F) Fill factor (%) Comparative example 3.0㎛ 1.34 X 10 ^-15 69.498 Example 1 3.0㎛ 1.21 X 10 ^-15 69.498 Example 2 2.9㎛ 1.21 X 10 ^-15 69.657 Example 3 2.8㎛ 1.21 X 10 ^-15 69.816 Example 4 2.7㎛ 1.21 X 10 ^-15 69.975 Example 5 2.6㎛ 1.22 X 10 ^-15 70.134 Example 6 2.5㎛ 1.23 X 10 ^-15 70.293 Example 7 2.4㎛ 1.24 X 10 ^-15 70.452 Example 8 2.3㎛ 1.26 X 10 ^-15 70.611 Example 9 2.2㎛ 1.29 X 10 ^-15 70.770 Example 10 2.1㎛ 1.35 X 10 ^-15 70.929

As shown in Table 1, in the comparative example, based on the horizontal distance d between the data line and the lower electrode of the PIN diode is 3.0 μm, the capacitor formed between the data line and the lower electrode of the PIN diode and the digital X-ray detector were It is a measure of the fill factor.

In the case of Example 1, the capacitor and the fill factor were measured based on the fact that the horizontal distance d between the data line 211 and the lower electrode 231 of the PIN diode 230 is 3.0 μm, as in the comparative example.

In the case of Example 1, since the area of the PIN diode 230 is the same, it has the same fill factor value, but the capacitor formed between the data line 211 and the lower electrode 231 of the PIN diode 230 is significantly compared to the comparative example. It can be seen that it is reduced.

In the case of Examples 2 to 10, the horizontal distance d between the data line 211 and the lower electrode 231 of the PIN diode 230 in the structure of Example 1 was measured by decreasing each 0.1 μm, From Example 1 to Example 10, the area of the PIN diode 230 gradually increases.

That is, it can be seen that the fill factor continues to increase from Example 1 to Example 10, and in the case of the capacitor between the data line 211 and the lower electrode 231 of the PIN diode 230, it remains the same until the fourth embodiment. From Example 5, it can be seen that it increases little by little.

In particular, even if the horizontal distance d between the data line 211 and the lower electrode 231 of the PIN diode 230 is 2.2 μm, which is 0.8 μm lower than that of the comparative example, it is still higher than that of the comparative example. It can be seen that it has a fill factor and a lower capacitor value.

As in Example 10, when the horizontal distance d between the data line 211 and the lower electrode 231 of the PIN diode 230 is 2.1 μm, the value of the capacitor is higher as compared to the comparative example, but the fill factor In the case of, it can be seen that it is significantly increased compared to the comparative example.

In addition, the present invention may have other embodiments. In describing the other embodiments, descriptions of components that are the same as or corresponding to the previous embodiments will be omitted, and differences will be mainly described.

Referring to FIG. 4, a thin film transistor array substrate for a digital X-ray detector and a digital X-ray detector including the same according to another embodiment of the present invention are the second electrode of the thin film transistor 220 as compared to the embodiment of FIG. 3. There is a difference between 225a and the lower electrode 231 of the PIN diode 230 in that they are not formed as separate electrodes but are formed integrally.

Specifically, referring to FIG. 4, the second electrode 225a may function as a source electrode of the thin film transistor 220 or a lower electrode of the PIN diode 230.

That is, since the thin film transistor 220 and the PIN diode 230 each share the second electrode 225a as a source electrode and a lower electrode, it is not necessary to form two electrodes as separate electrodes.

Accordingly, the second electrode 225a may be connected to directly contact the upper surface of the other side of the thin film transistor 220 and may be connected to directly contact the PIN layer 232 of the PIN diode 230.

In describing the present embodiment, the second electrode 225a was described as a reference, but since the second electrode 225a and the lower electrode are integrally formed, the lower electrode is the thin film transistor 220 It may be connected to directly contact the upper surface of the other side and at the same time be connected to directly contact the PIN layer 232 of the PIN diode 230.

Accordingly, the process of forming the second electrode 225a and the lower electrode separately and forming the first protective layer and the third contact hole as in the embodiment of FIG. 3 are not required, thus maximizing process efficiency. can do.

In addition, since the second electrode 225a and the lower electrode do not need to be formed separately, the second electrode 225a and the lower electrode are integrally formed, and the first protective layer 226 does not need to be formed. Since the thickness can be reduced, portability is good, and it may be more advantageous when implementing a flexible device.

In addition, the present invention may have another embodiment. In describing another embodiment, descriptions of components that are the same as or corresponding to the previous embodiment will be omitted, and differences will be mainly described.

Referring to FIG. 5, a thin film transistor array substrate for a digital X-ray detector and a digital X-ray detector including the same according to another embodiment of the present invention are compared with the first embodiment of the thin film transistor 220. There is a difference in that the electrode 211a extends to the channel region 221a of the active layer 221.

Specifically, the first electrode 211a is connected to a lower surface of one side of the thin film transistor 220 and is branched from the data line 211 to correspond to the channel region 221a of the active layer 221 to reach the channel region 221a. Can be extended.

That is, as the first electrode 211a is formed so as to correspond to the lower surface of the channel region 221a of the active layer 221, the first electrode 211a is directly irradiated to the lower surface of the live layer or the base substrate 210 It may also serve as a light blocking layer capable of blocking X-rays reflected from and irradiated to the lower surface of the active layer 221 as much as possible.

In particular, to form such a light blocking layer, a light blocking layer capable of protecting the active layer 221 of the thin film transistor 220 from X-rays can be formed at the same time as the patterning process of forming the data line 211 without adding a separate process. As can be achieved, process efficiency can be obtained.

In addition, since there is not a separate layer only for forming the light blocking layer, there is an advantage in that the light blocking layer can be formed without increasing the thickness of the entire digital X-ray detector.

The method of manufacturing a thin film transistor array substrate for a digital X-ray detector according to an embodiment of the present invention includes: i) forming a first electrode 211a on the base substrate 210, ii) covering the first electrode 211a. Forming the buffer layer 212 so that the buffer layer 212 is formed, iii) forming the active layer 221 on the buffer layer 212 to be connected to the first electrode 211a, iv) a gate insulating layer on the active layer 221 ( 222 and the gate electrode 223a, v) forming the second electrode 225a to be connected to the other side of the active layer 221, vi) the lower electrode to be connected to the second electrode 225a ( 231) and vii) forming a PIN layer 232 and an upper electrode 233 on the lower electrode 231.

A method of manufacturing a thin film transistor array substrate for a digital X-ray detector according to an embodiment of the present invention will be described in detail with reference to FIGS. 6A to 6L based on a mask process.

The pattern formation method for each layer described below is a technique performed by a person skilled in the art, such as deposition (Deposition), photoresist coating (Photoresist Coating), exposure (Exposure), development (Develop), and etching (Etch). , Since a photolithography process including a photoresist strip is used, a detailed description thereof will be omitted.

For example, in the case of deposition, sputtering in the case of a metallic material, and plasma enhanced vapor deposition (PECVD) in the case of a semiconductor or insulating film can be used separately.Even in the case of etching, dry type depending on the material can be used. Etching and wet etching can be selected and used, and a technique performed by a person skilled in the art is appropriately applied.

First, a first electrode 211a of the thin film transistor 220 is formed on the base substrate 210 as shown in FIG. 6A. Depending on the material of the base substrate 210, a buffer layer (not shown) may be formed on the base substrate 210 before forming the first electrode 211a.

For example, when the base substrate 210 is used as a glass substrate, the first electrode 211a may be formed without forming a separate buffer layer (not shown), but the base substrate 210 is made of polyimide. When used as a substrate, the first electrode 211a may be formed after a separate buffer layer (not shown) is formed.

Since the first electrode 211a is formed in the data line 211 and the first electrode 211a and the data line 211 are formed on the same layer, the data line 211 is formed on the base substrate 210 In this case, the first electrode 211a may also be formed at the same time.

A buffer layer 212 is formed on the first electrode 211a to cover the entire surface of the base substrate 210 as shown in FIG. 6B. In a region of the buffer layer 212 corresponding to the first electrode 211a, a first contact hole 212h exposing the first electrode 211a connected to the active layer 221 of the thin film transistor 220 to the outside is formed. can do.

That is, a region of the data line 211 corresponding to the first contact hole 212h of the buffer layer 212 may be the first electrode 211a of the thin film transistor 220.

On the buffer layer 212, an active layer 221 of the thin film transistor 220 is formed as shown in FIG. 6C. Specifically, the active layer 221 is formed on the buffer layer 212 to be connected to the first electrode 211a through the first contact hole 212h of the buffer layer 212. Accordingly, the first electrode 211a may be connected to the lower surface of one side of the active layer 221.

A gate insulating layer 222 and a gate electrode 223a are formed on the active layer 221 as shown in FIG. 6D. The gate insulating layer 222 and the gate electrode 223a are formed by patterning to correspond to the channel region 221a of the active layer 221. Since the gate electrode 223a may be branched from the gate line 223, when forming the gate line 223, the gate electrode 223a may also be formed at the same time.

When patterning the gate insulating layer 222 and the gate electrode 223a, the regions other than the channel region 221a of the active layer 221 are exposed to the outside, but since patterning is performed using the same method as etching, The active layer 221 other than the channel region 221a may be formed into a conductor through an etching process.

Accordingly, in the active layer 221, a first conductive region 221b and a second conductive region 221c with the channel region 221a interposed therebetween may be formed. The first electrode 211a may be connected to the first conductive region 221b of the active layer 221.

However, the method of conducting the active layer 221 is not limited thereto, and various methods such as hydrogen plasma treatment and helium plasma treatment may be used in addition to the dry etching method.

Next, as shown in FIG. 6E, an interlayer insulating layer 224 may be formed to cover the entire surface of the base substrate 210. A second contact hole 224h may be formed in the interlayer insulating layer 224 so that a region corresponding to the second conductive region 221c of the active layer 221 is exposed to the outside.

A second electrode 225a is formed on the interlayer insulating layer 224 as shown in FIG. 6F to be connected to the second conductive region 221c of the active layer 221. Specifically, the second electrode 225a is formed to be connected to the upper surface of the other side of the active layer 221 through the second contact hole 224h of the interlayer insulating layer 224.

Accordingly, the base substrate 210 includes a first electrode 211a, a second electrode 225a, a gate electrode 223a, and an active layer 221, and the first electrode 211a and the second electrode 225a Each may form a thin film transistor 220 connected to the active layer 221 in opposite directions to each other.

A first protective layer 226 may be formed on the second electrode 225a to cover the entire surface of the base substrate 210 as shown in FIG. 6G. A third contact hole 226h may be formed in the first passivation layer 226 to expose a partial upper portion of the second electrode 225a.

A lower electrode 231 of the PIN diode 230 is formed on the first protective layer 226 so as to be connected to the second electrode 225a as shown in FIG. 6H. Specifically, the lower electrode 231 may be formed to be connected to the second electrode 225a through the third contact hole 226h of the first protective layer 226.

In the present invention, the data line 211 is formed under the active layer 221 of the thin film transistor 220 so that the vertical distance between the data line 211 and the lower electrode 231 of the PIN diode 230 is far apart. Therefore, even if the lower electrode 231 is formed to a degree to cover at least a portion of the gate electrode 223a, the second electrode 225a, and the active layer 221 of the thin film transistor 220, the influence of the parasitic capacitor is minimized. can do.

Accordingly, the lower electrode 231 may be formed to cover even the channel region 221a of the active layer 221 so as to secure the maximum area of the PIN diode 230 in order to increase the fill factor.

Next, a PIN diode 230 is formed by forming a PIN layer 232 and an upper electrode 233 on the lower electrode 231 as shown in FIG. 6I. The PIN layer 232 includes an N-type semiconductor layer 232c containing N-type impurities, an I-type semiconductor layer 232b containing no impurities, and a P-type semiconductor layer 232a containing P-type impurities. It can be formed to be stacked as it is.

Further, as shown in FIG. 6J, a second protective layer 234 is formed to cover the entire surface of the base substrate 210, and a portion of the upper electrode 233 of the PIN diode 230 is exposed on the second protective layer 234. A fourth contact hole 234h may be formed.

A bias electrode 243 is formed on the second protective layer 234 as shown in FIG. 6K to be connected to the upper electrode 233 of the PIN diode 230 through the fourth contact hole 234h of the second protective layer 234. I can.

Next, as shown in FIG. 6L, a third protective layer 244 may be formed on the entire surface of the base substrate 210 to cover the bias electrode 243. In this case, a separate contact hole may be formed on the third protective layer in a region corresponding to the bias electrode. In addition, a scintillator layer may be formed on the third protective layer.

A method of manufacturing a thin film transistor array substrate for a digital X-ray detector according to another embodiment of the present invention includes: i) forming a first electrode 211a on the base substrate 210, ii) forming the first electrode 211a Forming the buffer layer 212 to cover, iii) forming the active layer 221 on the buffer layer 212 to be connected to the first electrode 211a, iv) a gate insulating layer on the active layer 221 Forming 222 and the gate electrode 223a, v) forming a second electrode 225a to be connected to the other side of the active layer 221, and vi) a second electrode 225a to be connected to the second electrode 225a And forming the PIN layer 232 and the upper electrode 233 on the electrode 225a.

A method of manufacturing a thin film transistor array substrate for a digital X-ray detector according to another embodiment of the present invention will be described in detail with reference to FIGS. 7A to 7J based on a mask process.

In addition, in describing a manufacturing method for another embodiment of the present invention, descriptions of the same or corresponding components as in the previous embodiment will be omitted.

In the manufacturing method according to another embodiment of the present invention, in the case of FIGS. 7A to 7E, the detailed description thereof will be omitted since it is the same as the manufacturing method according to FIGS. 6A to 6E described above.

Accordingly, the manufacturing method according to another exemplary embodiment of the present invention includes a first electrode 211a, a buffer layer 212, an active layer 221, and a gate insulating layer on the base substrate 210 through the processes of FIGS. 7A to 7E. 222, a gate electrode 223a, and an interlayer insulating layer 224 may be formed.

A second electrode 225a is formed on the interlayer insulating layer 224 as shown in FIG. 7F. The second electrode 225a may be formed to be connected to an upper surface of the other side of the active layer 221 through the second contact hole 224h of the interlayer insulating layer 224.

In this case, the second electrode 225a may function as a source electrode of the thin film transistor 220 and may be formed to function as a lower electrode of the PIN diode 230.

In the case of the present invention, since the data line 211 is formed under the active layer 221 of the thin film transistor 220 and the vertical distance between the data line 211 and the second electrode 225a is far apart, the second electrode Even if 225a is formed to a degree to cover at least a portion of the gate electrode 223a and the active layer 221 of the thin film transistor 220, the influence of the parasitic capacitor can be minimized.

Accordingly, the second electrode 225a, which also functions as a lower electrode of the PIN diode 230, is a channel region of the active layer 221 so as to secure the maximum area of the PIN diode 230 in order to increase the fill factor. It may be formed to cover even (221a).

That is, in the case of another embodiment of the present invention, there is no need to separately form the lower electrode of the PIN diode 230 in addition to the second electrode 225a of the thin film transistor 220, and the second electrode 225a and the lower electrode are integrally formed. Can be.

Accordingly, in the case of another embodiment of the present invention, as compared with the manufacturing method according to the previous embodiment, the process of separately forming the second electrode 225a and the lower electrode, and the first protective layer 226 and the third contact hole ( Since the formation process for 226h) is not required, process efficiency can be maximized.

A PIN diode 230 is formed by forming a PIN layer 232 and an upper electrode 233 on the second electrode 225a on the second electrode 225a as shown in FIG. 7G. The PIN layer 232 includes an N-type semiconductor layer 232c containing N-type impurities, an I-type semiconductor layer 232b containing no impurities, and a P-type semiconductor layer 232a containing P-type impurities. It can be formed to be stacked as it is.

The remaining processes according to FIGS. 7H to 7J are the same as those of FIGS. 6J to 6L of the previous embodiment, so a further description will be omitted.

As described above, the thin film transistor array substrate for a digital X-ray detector according to the present invention is on the base substrate and the base substrate, on the thin film transistor and the thin film transistor including the first electrode, the second electrode, the gate electrode and the active layer, and A PIN diode connected to the transistor is included, the first electrode and the second electrode are connected to the active layer in opposite directions, respectively, the second electrode is connected to the PIN diode, and the first electrode and the second electrode are different layers. Is in.

In this case, the PIN diode may include a lower electrode, a PIN layer, and an upper electrode, and the second electrode may be connected to the lower electrode.

Further, the PIN diode includes a PIN layer and an upper electrode, and the second electrode may be connected to the PIN layer.

The first electrode may be connected to one lower surface of the active layer, and the second electrode may be connected to the other upper surface of the active layer.

The PIN diode may cover at least a portion of the active layer, the active layer may include a channel region and conductive regions interposed between the channel region, and the PIN diode may cover the channel region.

The active layer includes a channel region and conductive regions interposed between the channel region, and the first electrode may extend to the channel region.

A buffer layer is provided between the first electrode and the active layer, and the first electrode and the active layer may be connected through a contact hole of the buffer layer.

In addition, the thin film transistor array substrate for a digital X-ray detector according to the present invention includes a base substrate on which a plurality of pixel regions are defined by a plurality of gate lines and a plurality of data lines crossing to be orthogonal to each other, a first electrode, A plurality of thin film transistors including a second electrode, a gate electrode, and an active layer, and a plurality of PIN diodes on the thin film transistor and connected to each of the thin film transistors, and the first electrode and the second electrode are in opposite directions to each other Is connected to the active layer, the second electrode is connected to the PIN diode, the first electrode is in the data line, the data line is under the active layer, and the first electrode and the second electrode are on different layers. I can.

In this case, the PIN diode may include a lower electrode, a PIN layer, and an upper electrode, and the second electrode may be connected to the lower electrode.

Further, the PIN diode includes a PIN layer and an upper electrode, and the second electrode may be connected to the PIN layer.

The data line and the second electrode may be on different layers.

The first electrode may be connected to one lower surface of the active layer, and the second electrode may be connected to the other upper surface of the active layer.

The PIN diode may cover at least a portion of the active layer, the active layer may include a channel region and conductive regions interposed between the channel region, and the PIN diode may cover the channel region.

The active layer includes a channel region and conductive regions interposed between the channel region, and the first electrode may extend to the channel region.

A buffer layer is provided between the first electrode and the active layer, and the first electrode and the active layer may be connected through a contact hole of the buffer layer.

The digital X-ray detector according to the present invention includes a thin film transistor array substrate for a digital X-ray detector and a scintillator layer on the thin film transistor array substrate for a digital X-ray detector.

In addition, the method of manufacturing a thin film transistor array substrate for a digital X-ray detector according to the present invention includes forming a first electrode on a base substrate, forming a buffer layer to cover the first electrode, and connecting the first electrode on the buffer layer. Forming an active layer, forming a gate insulating layer and a gate electrode on the active layer, forming a second electrode to be connected to the other side of the active layer, forming a lower electrode to be connected to the second electrode, and And forming a PIN layer and an upper electrode on the lower electrode.

Further, in the digital X-ray detector according to the present invention, forming a first electrode on a base substrate, forming a buffer layer to cover the first electrode, forming an active layer on the buffer layer to be connected to the first electrode, Forming a gate insulating layer and a gate electrode on the active layer, forming a second electrode to be connected to the other side of the active layer, forming a PIN layer and an upper electrode on the second electrode to be connected to the second electrode Includes.

As described above with reference to the drawings illustrated for the present invention, the present invention is not limited by the embodiments and drawings disclosed in the present specification, and various by a person skilled in the art within the scope of the technical idea It is obvious that transformation can be made. In addition, even if not explicitly described and described the effects of the configuration of the present invention while describing the embodiments of the present invention, it is natural that the predictable effects of the configuration should also be recognized.

110: thin film transistor array 120: gate driver
130: bias supply unit 140: power supply voltage supply unit
150: readout circuit unit 160: timing control unit
200: digital x-ray detector 210: base substrate
211: data line 211a: first electrode
212: buffer layer 212h: first contact hole
220: thin film transistor 221: active layer
221a: channel region 221b: first conductive region
221c: second conductive region 222: gate insulating layer
223: gate line 223a: gate electrode
224: interlayer insulating layer 224h: second contact hole
225a: second electrode 226: first protective layer
226 h: third contact hole 230: PIN diode
231: lower electrode 232: PIN layer
232a: P-type semiconductor layer 232b: I-type semiconductor layer
232c: N-type semiconductor layer 233: upper electrode
234: second protective layer 234h: fourth contact hole
241: bias line 243: bias electrode
244: third protective layer 250: scintillator layer

Claims (18)

A base substrate;
A thin film transistor on the base substrate and including a first electrode, a second electrode, a gate electrode, and an active layer; And
A PIN diode on the thin film transistor and connected to the thin film transistor; Including,
The first electrode and the second electrode are respectively connected to the active layer in opposite directions,
The second electrode is connected to the PIN diode,
A thin film transistor array substrate for a digital X-ray detector in which the first electrode and the second electrode are on different layers. The method of claim 1,
The PIN diode includes a lower electrode, a PIN layer, and an upper electrode,
The second electrode is a thin film transistor array substrate for a digital X-ray detector connected to the lower electrode. The method of claim 1,
The PIN diode includes a PIN layer and an upper electrode,
The second electrode is a thin film transistor array substrate for a digital X-ray detector connected to the PIN layer. The method of claim 1,
The first electrode is connected to a lower surface of one side of the active layer,
The second electrode is a thin film transistor array substrate for a digital X-ray detector connected to an upper surface of the other side of the active layer. The method of claim 1,
The PIN diode covers at least a portion of the active layer,
The active layer includes a channel region and conductive regions interposed between the channel region,
The PIN diode is a thin film transistor array substrate for a digital X-ray detector covering the channel region. The method of claim 1,
The active layer includes a channel region and conductive regions interposed between the channel region,
The first electrode is a thin film transistor array substrate for a digital X-ray detector extending to the channel region. The method of claim 1,
There is a buffer layer between the first electrode and the active layer,
The first electrode and the active layer are connected to each other through a contact hole of the buffer layer. A base substrate in which a plurality of pixel regions are defined by a plurality of gate lines and a plurality of data lines intersecting so as to be orthogonal to each other;
A plurality of thin film transistors on the base substrate and including a first electrode, a second electrode, a gate electrode, and an active layer; And
A plurality of PIN diodes on the thin film transistor and connected to each of the thin film transistors; Including,
The first electrode and the second electrode are respectively connected to the active layer in opposite directions,
The second electrode is connected to the PIN diode,
The first electrode is in the data line,
The data line is under the active layer,
A thin film transistor array substrate for a digital X-ray detector in which the first electrode and the second electrode are on different layers. The method of claim 8,
The PIN diode includes a lower electrode, a PIN layer, and an upper electrode,
The second electrode is a thin film transistor array substrate for a digital X-ray detector connected to the lower electrode. The method of claim 8,
The PIN diode includes a PIN layer and an upper electrode,
The second electrode is a thin film transistor array substrate for a digital X-ray detector connected to the PIN layer. The method of claim 8,
A thin film transistor array substrate for a digital X-ray detector in which the data line and the second electrode are on different layers. The method of claim 8,
The first electrode is connected to a lower surface of one side of the active layer,
The second electrode is a thin film transistor array substrate for a digital X-ray detector connected to an upper surface of the other side of the active layer. The method of claim 8,
The PIN diode covers at least a portion of the active layer,
The active layer includes a channel region and conductive regions interposed between the channel region,
The PIN diode is a thin film transistor array substrate for a digital X-ray detector covering the channel region. The method of claim 8,
The active layer includes a channel region and conductive regions interposed between the channel region,
The first electrode is a thin film transistor array substrate for a digital X-ray detector extending to the channel region. The method of claim 8,
There is a buffer layer between the first electrode and the active layer,
The first electrode and the active layer are connected to each other through a contact hole of the buffer layer. The thin film transistor array substrate for a digital X-ray detector according to any one of claims 1 to 15; And
A digital x-ray detector comprising a scintillator layer on the thin film transistor array substrate for the digital x-ray detector. Forming a first electrode on the base substrate;
Forming a buffer layer to cover the first electrode;
Forming an active layer on the buffer layer to be connected to the first electrode;
Forming a gate insulating layer and a gate electrode on the active layer;
Forming a second electrode to be connected to the other side of the active layer;
Forming a lower electrode to be connected to the second electrode; And
Forming a PIN layer and an upper electrode on the lower electrode; Method of manufacturing a thin film transistor array substrate for a digital X-ray detector comprising a. Forming a first electrode on the base substrate;
Forming a buffer layer to cover the first electrode;
Forming an active layer on the buffer layer to be connected to the first electrode;
Forming a gate insulating layer and a gate electrode on the active layer;
Forming a second electrode to be connected to the other side of the active layer;
Forming a PIN layer and an upper electrode on the second electrode to be connected to the second electrode; Method of manufacturing a thin film transistor array substrate for a digital X-ray detector comprising a.

Images