KR102259259B1 - Method of fabricating the variable resistance memory - Google Patents

Abstract

A variable resistance memory device according to an embodiment of the present invention includes preparing a substrate on which a lower electrode is formed, forming a mold layer on the substrate, patterning the mold layer to form a trench, and forming the trench on the mold layer forming a variable resistive film including a first portion in the trench and a second portion on an upper surface of the mold film, and applying a laser to the variable resistive film so that the second portion of the variable resistive film is formed with the first and peeling from the portion to form a variable resistance element in the trench.

Description

Method of fabricating the variable resistance memory device

The present invention relates to a method of manufacturing a variable resistance memory device, and more particularly, to a method of manufacturing a variable resistance memory device with improved reliability.

In line with the trend toward higher performance and lower power consumption of semiconductor memory devices, next-generation semiconductor memory devices such as ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and phase-change random access memory (PRAM) are being developed. Materials constituting these next-generation semiconductor memory devices have a resistance value that changes according to a current or voltage, and maintains the resistance value even when the current or voltage supply is stopped.

Among these variable resistance memory devices, a phase change memory device (PRAM) using a phase-change material has a high operating speed and has a structure advantageous for high integration, and thus development is continuing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a variable resistance memory device with improved reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A method of manufacturing a variable resistance memory device according to an embodiment of the present invention includes preparing a substrate on which a lower electrode is formed, forming a mold layer on the substrate, patterning the mold layer to form a trench, and on the mold layer forming a variable resistance film including a first portion filling the trench and a second portion on an upper surface of the mold film, and irradiating a laser to the variable resistance film so that the second portion of the variable resistance film is formed with the first peeling from the portion to form a variable resistance element in the trench.

The irradiating of the laser to the variable resistance film may include melting and/or vaporizing the second portion of the variable resistance film by the laser to be peeled off from the first portion.

The method may further include forming a sacrificial layer on the mold layer before forming the trench, and forming the sacrificial pattern on the mold layer by patterning the sacrificial layer and the mold layer.

The laser may include melting the sacrificial pattern to peel the sacrificial pattern from the mold layer.

The peeling of the sacrificial pattern from the mold layer includes attaching the substrate to a support disposed on the upper part of the chamber so that the mold layer faces the lower part of the chamber, and the laser is controlled from the lower part of the chamber. irradiating the resistive layer, and the sacrificial pattern is melted by the laser to peel the sacrificial pattern from the mold layer in the direction of gravity, and at the same time, the second part of the variable resistive layer is peeled from the first part may include

The sacrificial layer may include one selected from the group consisting of GaN, TiN, Al-Si, Si, Ge, crystalline AlN, amorphous AlN, amorphous SiC, Al, W, Cr, Ni, CU, and combinations thereof. have.

The variable resistance element may be formed to have a concave upper surface.

A method of manufacturing a variable resistance memory device according to an embodiment of the present invention includes preparing a substrate on which a lower electrode is formed, forming a mold film on the substrate, patterning the mold film to form a trench, and on the mold film forming a variable resistive film including a first portion filling the trench and having a void and a second portion on an upper surface of the mold film, and applying a laser to the variable resistive film so that the second portion of the variable resistive film is formed and flowing into the trench to form a variable resistance element in the trench.

The second portion of the variable resistance layer may be melted by the laser to fill the void.

The second portion of the variable resistance layer may flow into the trench to expose an upper surface of the mold layer.

According to an embodiment of the present invention, the variable resistance element may be formed by peeling off the second portion of the variable resistance layer using a laser. The second portion of the variable resistance film may be lifted off from the first portion of the variable resistance film by melting the sacrificial pattern with a laser.

According to another embodiment of the present invention, without a sacrificial pattern, the second portion of the variable resistance film may be melted and/or vaporized by a laser to be lifted off from the first portion of the variable resistance film. Accordingly, it is possible to form a variable resistance element without changing the physical properties of the variable resistance layer.

1 is a circuit diagram illustrating a memory cell array of a variable resistance memory device according to embodiments of the present invention.
2 is a plan view illustrating a variable resistance memory device according to Embodiment 1 of the present invention.
3 to 13 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to Embodiment 1 of the present invention, taken along line I-I' of FIG. 2 .
14 to 17 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to a second embodiment of the present invention, taken along line I-I' of FIG. 2 .
18 to 21 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to a third embodiment of the present invention, taken along line I-I' of FIG. 2 .
22 to 25 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to a fourth embodiment of the present invention, taken along line I-I' of FIG. 2 .
26 is a block diagram of an electronic device including a semiconductor device according to example embodiments.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in a variety of different forms. It is provided to completely inform the scope of the invention to the possessor, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same constituent elements throughout the entire specification.

The terms used in the present specification are for describing exemplary embodiments and are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used herein, 'comprises' and/or 'comprising' refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

Further, the embodiments described in the present specification will be described with reference to sectional views and/or plan views, which are ideal exemplary diagrams of the present invention. In the drawings, thicknesses of films and regions are exaggerated for effective description of technical content. Accordingly, the form of the illustrative drawing may be modified due to manufacturing technology and/or tolerance. Accordingly, the embodiments of the present invention are not limited to the specific form shown, but also include changes in the form generated according to the manufacturing process. For example, the etched area shown at a right angle may be rounded or may have a shape having a predetermined curvature. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are for illustrating a specific shape of the region of the device and are not intended to limit the scope of the invention.

1 is a circuit diagram illustrating a memory cell array of a variable resistance memory device according to embodiments of the present invention.

Referring to FIG. 1 , a semiconductor device according to embodiments of the present invention may be a variable resistance memory device 10 , and more specifically, a phase change memory device. In the variable resistance memory device 10 , a plurality of memory cells MC are arranged in a matrix form. Each of the memory cells MC includes a selection element 108 and a variable resistance element 128 . The selection element 108 may be connected between the variable resistance element 128 and the word line WL, and the variable resistance element 128 may be connected between the bit line BL and the selection element 108 .

The selection element 108 may be connected between the variable resistance element 128 and the word line WL, and current supply to the variable resistance element 128 is controlled according to the voltage of the word line WL. In the present invention, the selection element 108 may be a PN junction diode.

The variable resistance element 128 may include, for example, a phase-change material, a ferroelectric material, or a magnetic material. The state of the variable resistance element 128 may be determined according to the amount of current supplied through the bit line BL.

Hereinafter, in embodiments of the present invention, a variable resistance memory device including memory cells using a phase change material as the variable resistance element 128 will be described as an example. However, the technical spirit of the present invention is not limited thereto, and it is of course applicable to resistance random access memory (RRAM), ferroelectric RAM (FRAM), and magnetic RAM (MRAM).

In embodiments of the present invention, the resistance of the phase change material that is the variable resistance element 128 changes according to temperature. That is, the phase change material has an amorphous state having a relatively high resistance and a crystalline state having a relatively low resistance according to temperature and cooling time. The variable resistance element 128 may generate Joule's heat according to the amount of current supplied through the lower electrode to heat the phase change material. At this time, Joule heat is generated in proportion to the specific resistance of the phase change material and the supply time of the current.

2 is a plan view illustrating a variable resistance memory device according to Embodiment 1 of the present invention. 3 to 13 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to Embodiment 1 of the present invention, taken along line I-I' of FIG. 2 .

2 and 3 , the substrate 100 is prepared. The substrate 100 may include a single crystal semiconductor material. For example, the substrate 100 may be a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, and/or a silicon-germanium substrate. . Alternatively, the substrate 100 may be doped with, for example, P-type impurities. However, the substrate 100 is not limited thereto and may be various.

An active region may be defined by forming a device isolation layer (not shown) in the substrate 100 . The word lines 102 arranged to be spaced apart from each other at regular intervals in the active region may be formed. The word lines 102 may be formed by, for example, doping an N-type impurity.

An interlayer insulating film 104 is formed on the substrate 100 . The interlayer insulating layer 104 is patterned to form first trenches 106 . The first trenches 106 may be formed on the word lines 102 to expose the word lines 102 . The interlayer insulating film 104 may be, for example, a silicon oxide film or a silicon nitride film.

A selective epitaxial growth (SEG) process is performed using the word lines 102 exposed in the first trenches 106 as seeds. A semiconductor layer filling a portion of the first trenches 106 may be formed by the SEG process. The selection element 108 may be formed by doping the semiconductor layer with impurities. In detail, the selection element 108 may be formed by doping different types of impurities into the semiconductor layer. For example, a lower portion of the selection element 108 may be doped with an N-type impurity to form a first semiconductor pattern (not shown), and a first semiconductor doped with a P-type impurity on an upper portion of the selection element 108 . A second semiconductor pattern (not shown) may be formed on the pattern (not shown). The selection element 108 may be, for example, a diode.

A lower electrode pad 110 may be formed on the selection element 108 . The lower electrode pad 110 may include, for example, at least one of a metal silicide layer, a metal nitride layer, and a metal layer.

A spacer 112 may be formed on the lower electrode pad 110 . In detail, the spacer 112 may be formed to expose the upper surface of the lower electrode pad 110 and cover sidewalls of the first trenches 106 . The spacer 112 may be, for example, a silicon oxide layer.

The lower electrode 114 may be conformally formed in the first trenches 106 to cover the upper surface of the lower electrode pad 110 and the spacer 112 . The lower electrode 114 may be, for example, Ti, TiSix, TiN, TiON, TiW, TiAlN, TiAlON, TiSiN, TiBN, W, WSi _x , WN, WON, WSiN, WBN, WCN, Ta, TaSi _x , TaN, containing one selected from the group consisting of TaON, TaAlN, TaSiN, TaCN, Mo, MoN, MoSiN, MoAlN, NbN, ZrSiN, ZrAlN, Ru, CoSi, NiSi, conductive C group, Cu, and combinations thereof can do. The lower electrode 114 has a 'U' shape on the cross-section of the drawing, but the shape of the lower electrode 114 is not limited to the shape shown in the drawing.

A filling insulating pattern 116 filling the first trenches 106 may be formed on the lower electrode 114 . The buried insulating pattern 116 may be made of the same material as the interlayer insulating layer 104 , and may be, for example, a silicon oxide layer or a silicon nitride layer.

A mold layer 118 may be formed on the interlayer insulating layer 104 . The mold layer 118 is, for example, may comprise a SiOx, SiN, SiON, SICN, TiO, ZrOx, MgOx, at least one of HfO _x and AlO _x.

A sacrificial layer 120 may be formed on the mold layer 118 . The sacrificial layer 120 is, for example, a group consisting of GaN, TiN, Al-Si, Si, Ge, crystalline AlN, amorphous AlN, amorphous SiC, Al, W, Cr, Ni, CU, and combinations thereof. It may include one selected from.

Referring to FIG. 4 , the sacrificial layer 120 and the mold layer 118 are patterned to form second trenches 122 on the interlayer insulating layer 104 . A sacrificial pattern 121 is formed on the mold layer 118 in which the second trenches 122 are formed. In detail, the second trenches 122 are formed to expose the lower electrode 114 by forming a mask pattern (not shown) on the sacrificial layer 120 and etching the mold layer 118 exposed to the mask pattern. can A portion of the sacrificial layer 120 exposed to the mask pattern may be etched to form the sacrificial pattern 121 on the mold layer 118 . The sacrificial layer 120 and the mold layer 118 may be etched by, for example, dry etching or wet etching.

Referring to FIG. 5 , a variable resistance layer 124 is formed on the mold layer 118 . The variable resistance layer 124 may be formed to fill the second trenches 122 and cover the upper surface of the sacrificial pattern 121 . The variable resistance layer 124 may include a first portion P1 and a second portion P2 . The first portion P1 is a portion of the variable resistance layer 124 filled in the second trenches 122 , and the second portion P2 is a variable resistance layer 124 formed on the upper surface of the mold layer 118 . may be part of The variable resistance layer 124 is a layer including at least one of Te (tellurium) and selenium (Se), for example, GeSbTe, GeTeAs, SnTeSn, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi. , InSe, GaTeSe, InSe, GaTeSe or InSbTe. In addition, impurities (eg, any one of C, N, Si, O, N, and B) may be doped into the variable resistance layer 124 .

6 and 7 , a laser 126 may be irradiated to the variable resistance layer 124 . In detail, the substrate 100 on which the variable resistance layer 124 is deposited may be adhered to the support 132 in the chamber 130 . The support 132 is disposed on the upper portion of the chamber 130 , and since the substrate 100 is adhered to the support 132 , the upper surface of the variable resistance layer 124 may be disposed toward the lower portion of the chamber 130 . . The laser 126 may be provided from a lower portion of the chamber 130 and applied to the variable resistance layer 124 and the sacrificial pattern 121 disposed on the upper portion of the chamber 130 . The laser 126 may melt the sacrificial pattern 121 . The laser 126 is used for the purpose of melting the sacrificial pattern 121, but at the same time the sacrificial pattern 121 is melted, a variable resistance film ( The second portion P2 of 124 may be melted by a laser 126 . When the sacrificial pattern 121 is, for example, GaN, the laser 126 may separate the sacrificial pattern 121 into Ga+N to change gallium (Ga) into a liquid state. As the sacrificial pattern 121 changes to a molten state, the sacrificial pattern 121 may be peeled off from the mold layer 118 . Due to the peeling of the sacrificial pattern 121 , a portion of the variable resistance layer 124 adjacent to the sacrificial pattern 121 may be peeled off from the variable resistance layer 124 . In detail, the variable resistance layer 124 is directed toward the lower portion of the chamber 130 , and gravity is directed from the upper portion to the lower portion of the chamber 130 . While the sacrificial pattern 121 is peeled off in the direction of gravity, the second portion P2 of the variable resistance layer 124 adjacent to the interface between the sacrificial pattern 121 and the mold layer 118 is separated from the first portion P1 . The sacrificial pattern 121 may be peeled off.

Laser 126 may be, for example, a solid-state laser. A solid-state laser is a method of forming a laser using a solid medium. The solid state laser may have a wavelength between about 500 nm and about 1200 nm. The solid-state laser may be, for example, an aluminum-garnet (YAG) laser using a YAG crystal doped with Nd and Yb as a medium. The process atmosphere during application of the laser 126 is a reaction gas (eg, H ₂ , N ₂ , O ₂ ) or an inert gas (He) at a temperature of room temperature to about 600 °C and a pressure of 1 atm to 10 ^{-8 torr.} , Ne, Ar, Kr) can be used. The reaction gas may be used as an accelerator for causing a chemical reaction so that the separation between the interface between the mold film 118 and the variable resistance film 124 can be better performed. The inert gas may be used to create an atmosphere that does not cause a chemical reaction between layers of different materials. Embodiments of the invention be carried out from about 500nm to about 600nm, or from about 1000nm to about 1200nm laser having a wavelength and, 0.3J / cm ² to the laser processing conditions of the time of 4J / cm ² energy density and 300ns to 1200ns of can

8 to 10 , as the sacrificial pattern 121 is peeled off from the mold layer 118 and the second portion P2 of the variable resistance layer 124 is peeled off, the variable resistance in the second trenches 122 is peeled off. Device 128 may be formed. As the sacrificial pattern 121 is peeled off, the upper surface of the mold layer 118 may be exposed. The height of the variable resistance element 128 may vary depending on a position where the second portion P2 of the variable resistance layer 124 is peeled off while being peeled off.

Referring to FIG. 8 , the upper surface of the variable resistance element 128 may be positioned on the same level as the upper surface of the mold layer 118 . In this case, the peeling position of the variable resistance layer 124 may be between the first portion P1 and the second portion P2 of the variable resistance layer 124 .

Referring to FIG. 9 , the upper surface of the variable resistance element 128 may be positioned at a higher level than the upper surface of the mold layer 118 . In this case, the peeling position of the variable resistive layer 124 may be within the second portion P2 of the variable resistive layer 124 .

Referring to FIG. 10 , the upper surface of the variable resistance element 128 may be positioned at a level lower than the upper surface of the mold layer 118 . In this case, the peeling position of the variable resistive layer 124 may be within the first portion P1 of the variable resistive layer 124 .

Although not shown in the drawing, the upper surface of the variable resistance element 128 may have a rough surface. This is because the second portion P2 of the variable resistance layer 124 is peeled off while being physically torn from the first portion P1 .

In general, a damascene process is used to form a variable resistance element in each of the memory cells. More specifically, a variable resistive layer is formed to fill the trenches, and a portion of the variable resistive layer that does not fill the trenches is etched to form a variable resistive element in each of the trenches. The etching process of etching a portion of the variable resistive layer may include dry etching or a chemical physical polishing (CMP) process. However, there is a problem in that the halogen element included in the halogen gas used for dry etching is combined with the element included in the variable resistance layer to change material properties of the variable resistance layer. The CMP process requires slurry particles to polish the variable resistive film. However, the type of the slurry particles should be different depending on the type and density of the material of the variable resistive film.

According to an embodiment of the present invention, the variable resistance layer 124 formed on the second trenches 122 by applying a solid laser to the variable resistance layer 124 and the sacrificial pattern 121 to melt the sacrificial pattern 121 . The second portion P2 of the may be lifted off. Since the solid-state laser melts the sacrificial pattern 121 in a short time, a change in physical properties of the variable resistance layer 124 may be minimized.

11 to 13 , bit lines 129 covering the variable resistance element 128 are formed on the mold layer 118 . The bit lines 129 may be formed to intersect the word lines 102 . The bit lines 129 may be formed by forming a metal layer (not shown) on the mold layer 118 and patterning the metal layer.

Referring to FIG. 11 , the bit lines 129 may be formed to cover the upper surface of the variable resistance element 128 .

Referring to FIG. 12 , the bit lines 129 may be formed to cover the upper surface of the variable resistance element 128 and a portion of the sidewall exposed by the mold layer 118 .

Referring to FIG. 13 , the bit lines 129 may be formed to cover the upper surface of the variable resistance element 128 and be buried in the second trenches 122 . The bit lines 129 may include a conductive material.

14 to 17 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to a second embodiment of the present invention, taken along line I-I' of FIG. 2 . For brevity of description, in Example 2, components substantially the same as in Example 1, descriptions of the corresponding components, and process methods will be omitted.

Referring to FIG. 14 , second trenches 122 are formed by patterning the mold layer 118 . The second trenches 122 may be formed to expose the upper surface of the lower electrode 114 . A variable resistance layer 124 is formed on the mold layer 118 . The variable resistance layer 124 may be formed to fill the second trenches 122 and cover the upper surface of the mold layer 118 . In Example 2, since the sacrificial pattern 121 in Example 1 is not formed, the upper surface of the mold layer 118 may directly contact the variable resistance layer 124 . The variable resistance layer 124 may include a first portion P1 and a second portion P2 . The first portion P1 is a portion of the variable resistance layer 124 filled in the second trenches 122 , and the second portion P2 is a variable resistance layer 124 formed on the upper surface of the mold layer 118 . may be part of

Referring to FIG. 15 , a laser 126 may be applied on the variable resistance layer 124 . When the laser 126 is applied to the variable resistive layer 124 , the temperature of the variable resistive layer 124 may be changed. For example, the temperature of the variable resistance layer 124 may be increased. Accordingly, the variable resistance film 124 having a high temperature may be melted or vaporized by the laser 126 . In detail, the second portion P2 of the variable resistance film 124 including the upper surface of the variable resistance film 124 is a portion to which the laser 126 is directly applied, and the first portion of the variable resistance film 124 . It may have a higher temperature by the laser 126 than the portion P1. (ie, T2>T1) Accordingly, the second portion P2 of the variable resistance layer 124 may be melted and/or vaporized.

Laser 126 may be, for example, a solid-state laser. The process atmosphere during application of the laser 126 is a reaction gas (eg, H ₂ , N ₂ , O ₂ ) or an inert gas (He) at a temperature of room temperature to about 600 °C and a pressure of 1 atm to 10 ^{-8 torr.} , Ne, Ar, Kr) can be used. Embodiments of the invention be carried out from about 500nm to about 600nm, or from about 1000nm to about 1200nm laser having a wavelength and, 0.3J / cm ² to the laser processing conditions of the time of 4J / cm ² energy density and 300ns to 1200ns of can

Referring to FIG. 16 , as the second portion P2 of the variable resistance film 124 is melted and/or vaporized, it is peeled off from the first portion P1 of the variable resistance film 124 in the second trenches 122 . A variable resistance element 128 may be formed. The delamination phenomenon may occur more easily at interfaces between films containing different materials than at interfaces between films containing the same material. Accordingly, peeling occurs more easily between the upper surface of the mold layer 118 and the variable resistance layer 124 , so that the second portion P2 of the variable resistance layer 124 can be easily peeled off from the first portion P1 . have. The variable resistance element 128 may have a concave upper surface.

According to an exemplary embodiment, the variable resistance element 128 may be formed by peeling off the second portion P2 of the variable resistance layer 124 without the sacrificial pattern 121 described in the first exemplary embodiment. A solid laser is applied to the variable resistance film 124 in a short time to melt and/or vaporize the second portion P2 of the variable resistance film 124 to form the second portion P2 of the variable resistance film 124 . It can be lifted off. Accordingly, the variable resistance element 128 may be formed by minimizing a change in the physical properties of the variable resistance layer 124 .

Referring to FIG. 17 , bit lines 129 covering the variable resistance element 128 may be formed on the mold layer 118 .

18 to 21 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to a third embodiment of the present invention, taken along line I-I' of FIG. 2 . For brevity of description, in Example 3, components substantially the same as in Examples 1 and 2, descriptions of corresponding components, and process methods will be omitted.

Referring to FIG. 18 , the second trenches 122 are formed by patterning the mold layer 118 . A variable resistance layer 124 is formed on the mold layer 118 . The variable resistance layer 124 may be formed to fill the second trenches 122 and cover the upper surface of the mold layer 118 . The upper surface of the mold layer 118 may be in direct contact with the variable resistance layer 124 . The variable resistance layer 124 may include a first portion P1 and a second portion P2 .

Referring to FIG. 19 , a laser 126 and a gas 134 may be simultaneously provided to the variable resistance layer 124 . In detail, the laser 126 may be applied on the upper portion of the variable resistance film 124 , and the gas 134 may be sprayed onto one side of the variable resistance film 124 . The variable resistance layer 124 may be melted by the laser 126 . The molten variable resistance layer 124 may have fluidity. Accordingly, the second portion P2 of the variable resistance layer 124 may be focused in a direction in which the gas 134 is injected by the gas 134 . That is, the second portion P2 of the variable resistance layer 124 may be directed to the other side of the variable resistance layer 124 , which is the opposite side to which the gas 134 is injected. The first portion P1 of the variable resistance layer 124 may be attached to the surface of the first trenches 106 by capillary action by an adhesive force to fill the first trenches 106 . The second portion P2 of the variable resistance layer 124 may be removed through an exhaust port (not shown) disposed on the other side of the variable resistance layer 124 .

Laser 126 may be, for example, a solid-state laser. The process atmosphere during application of the laser 126 is a reaction gas (eg, H ₂ , N ₂ , O ₂ ) at a temperature of room temperature (about 20 °C) to about 600 °C and a pressure of 1 atm to 10 ^{-8 torr.} ) or an inert gas (He, Ne, Ar, Kr) may be used. Embodiments of the invention be carried out from about 500nm to about 600nm, or from about 1000nm to about 1200nm laser having a wavelength and, 0.3J / cm ² to the laser processing conditions of the time of 4J / cm ² energy density and 300ns to 1200ns of can

The gas 134 may be, for example, air.

20 and 21 , the variable resistance element 128 may be formed in the second trenches 122 while the second portion P2 of the variable resistance layer 124 is removed. Bit lines 129 may be formed on the variable resistance element 128 .

22 to 25 are cross-sectional views illustrating a method of manufacturing a variable resistance memory device according to a fourth embodiment of the present invention, taken along line I-I' of FIG. 2 . For brevity of description, in Example 4, components substantially the same as in Examples 1 and 3, descriptions of corresponding components, and process methods will be omitted.

Referring to FIG. 22 , second trenches 122 are formed by patterning the mold layer 118 . A variable resistance layer 124 is formed on the mold layer 118 . The variable resistance layer 124 may be formed to fill the second trenches 122 and cover the upper surface of the mold layer 118 . In detail, the variable resistance layer 124 may be formed to partially fill the second trenches 122 . Accordingly, the first portion P1 of the variable resistance layer 124 may include the void 136 . The variable resistance layer 124 may be formed using, for example, a physical vapor deposition (PVD) method.

23 and 24 , a laser 126 may be applied on the variable resistance layer 124 . The variable resistance layer 124 may be melted by the laser 126 . Since the second portion P2 of the variable resistance layer 124 has fluidity, it may flow into the first trenches 106 to fill the voids 136 .

Laser 126 may be, for example, a solid-state laser. The process atmosphere during application of the laser 126 is a reaction gas (eg, H ₂ , N ₂ , O ₂ ) at a temperature of room temperature (about 20°C) to about 600°C and a pressure of 1 atm to 10 ^{-8 torr.} ) or an inert gas (He, Ne, Ar, Kr) may be used. Embodiments of the invention be carried out from about 500nm to about 600nm, or from about 1000nm to about 1200nm laser having a wavelength and, 0.3J / cm ² to the laser processing conditions of the time of 4J / cm ² energy density and 300ns to 1200ns of can

Referring to FIG. 25 , the second portion P2 of the variable resistance layer 124 may completely flow into the second trenches 122 to fill the second trenches 122 to form the variable resistance element 128 . . A top surface of the mold layer 118 may be exposed from the variable resistance element 128 . Bit lines 129 may be formed on the variable resistance element 128 .

26 is a block diagram of an electronic device including a semiconductor device according to example embodiments.

The electronic device 1000 including the semiconductor device according to the embodiments of the present invention includes an application chipset, a camera image processor (CIS), a PDA, a laptop computer, a portable computer, and a web tablet. It may be one of a web tablet, a wireless phone, a mobile phone, a digital music player, a wired/wireless electronic device, or a composite electronic device including at least two of them.

Referring to FIG. 26 , the electronic device 1000 includes a semiconductor memory device 1300 including a semiconductor device (eg, PRAM; 1100 ) and a memory controller 1200 , and a system bus (eg, PRAM) according to embodiments of the present invention. 1450 includes a central processing unit 1500 , a user interface 1600 , and a power supply unit 1700 electrically connected to the 1450 .

In the semiconductor memory device 1100 , data provided through the user interface 1600 or processed by the central processing unit 1500 is stored through the memory controller 1200 . The semiconductor memory device 1100 may be configured as a semiconductor disk device (SSD), and in this case, the operating speed of the electronic device 1000 may be remarkably increased.

As mentioned above, although embodiments of the present invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can practice the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate
102: word lines
104: interlayer insulating film
106: first trenches
108: selection element
110: lower electrode pad
112: spacer
114: lower electrode
116: first trenches
118: mold film
121: sacrifice pattern
122: second trenches
124: variable resistance film
126: laser
P1: first part
P2:: 2nd part

Claims (10)

preparing a substrate on which a lower electrode is formed;
forming a mold film on the substrate;
patterning the mold layer to form a trench;
forming a variable resistance layer on the mold layer, the variable resistance layer including a first portion filling the trench and a second portion on an upper surface of the mold layer; and
and irradiating a laser to the variable resistance film to separate the second portion of the variable resistance film from the first portion, thereby forming a variable resistance element in the trench.
The method of claim 1,
Irradiating the laser to the variable resistive film comprises:
and wherein the second portion of the variable resistance film is melted and/or vaporized by the laser to be peeled off from the first portion.
The method of claim 1,
Before forming the trench,
forming a sacrificial layer on the mold layer; and
and patterning the sacrificial layer and the mold layer to form a sacrificial pattern on the mold layer.
The method of claim 3,
and wherein the laser melts the sacrificial pattern to separate the sacrificial pattern from the mold layer.
The method of claim 4,
When the sacrificial pattern is peeled off from the mold layer:
attaching the substrate to a support disposed above the chamber so that the mold layer faces a lower portion of the chamber;
irradiating the variable resistance film with the laser from the lower portion of the chamber; and
and wherein the sacrificial pattern is melted by the laser to peel the sacrificial pattern from the mold layer in the direction of gravity, and at the same time, the second part of the variable resistance layer is peeled from the first part. manufacturing method.
The method of claim 3,
The sacrificial layer may include one selected from the group consisting of GaN, TiN, Al-Si, Si, Ge, crystalline AlN, amorphous AlN, amorphous SiC, Al, W, Cr, Ni, CU, and combinations thereof. A method of manufacturing a resistive memory device.
The method of claim 1,
The method of manufacturing a variable resistance memory device, wherein the variable resistance element is formed to have a concave upper surface.
preparing a substrate on which a lower electrode is formed;
forming a mold film on the substrate;
patterning the mold layer to form a trench;
forming a variable resistance film on the mold film, the variable resistance film including a first portion filling the trench and having a void and a second portion on an upper surface of the mold film; and
and applying a laser to the variable resistance film so that the second portion of the variable resistance film flows into the trench to form a variable resistance element in the trench.
The method of claim 8,
and the second portion of the variable resistance film is melted by the laser to fill the void.
The method of claim 8,
The method of manufacturing a variable resistance memory device, wherein the second portion of the variable resistance layer flows into the trench to expose an upper surface of the mold layer.

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