KR20030057697A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20030057697A
KR20030057697A KR1020010087773A KR20010087773A KR20030057697A KR 20030057697 A KR20030057697 A KR 20030057697A KR 1020010087773 A KR1020010087773 A KR 1020010087773A KR 20010087773 A KR20010087773 A KR 20010087773A KR 20030057697 A KR20030057697 A KR 20030057697A
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substrate
insulating film
interlayer insulating
semiconductor device
forming
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KR1020010087773A
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Korean (ko)
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신순하
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주식회사 하이닉스반도체
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Priority to KR1020010087773A priority Critical patent/KR20030057697A/en
Publication of KR20030057697A publication Critical patent/KR20030057697A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of improving topology by planarizing using a laser. CONSTITUTION: Metal lines(22) are formed on a semiconductor substrate(20). An interlayer dielectric is formed on the metal lines(22). A via hole is formed by selectively etching the interlayer dielectric. A metal film(23) is formed on the resultant structure including the via hole. A via plug is then formed by irradiating laser beam to sides of the metal film(23) using a laser irradiation apparatus(35) while rotating the substrate(20) using a chuck(24).

Description

반도체 소자의 제조 방법{Method for fabricating semiconductor device}Method for manufacturing a semiconductor device {Method for fabricating semiconductor device}

본 발명은 반도체 소자의 평탄화 방법에 관한 것으로, 특히 기판에 형성된 층을 레이저(laser)를 이용하여 평탄화하는 반도체 소자의 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and more particularly, to a planarization method of a semiconductor device in which a layer formed on a substrate is planarized using a laser.

고집적 회로의 금속배선 공정에는 배선간의 전기적 절연을 위해 절연막을 형성하는데, 하부구조로 인하여 단차가 발생한 절연막을 평탄화하는 공정을 거치게 된다.In the metallization process of the highly integrated circuit, an insulating film is formed to electrically insulate between the wirings, and a step of planarizing the insulating film having a step due to the lower structure is performed.

일반적으로, 단차가 형성된 반도체 소자를 평탄화하기 위해서 화학적기계적 연마를 이용한다. 반도체 웨이퍼 프로세싱에서 화학기계적 평탄화(chemical mechanical planarization) 즉 CMP는, 웨이퍼와 같은 기판 즉 반도체 피가공물 위에 소자 밀도를 증가시키는 능력을 향상시키기 때문에 그 사용이 선호되어 왔다.In general, chemical mechanical polishing is used to planarize a semiconductor device in which a step is formed. Chemical mechanical planarization, or CMP, in semiconductor wafer processing has been preferred because of its ability to increase device density on substrates, such as wafers, or semiconductor workpieces.

이를 자세히 살펴보면, 다층 배선간의 절연막은 현재 하부 금속패턴의 갭필 특성을 좋게 하는 HD-USG막 단독으로 형성하거나, HD-USG막을 형성하고 그 상부에 PE-CVD 법으로 산화막을 두껍게 재 증착하는 이중막을 주로 사용한다. 증착후의 평탄화는 슬러리(Slurry)를 매개로 웨이퍼와 연마패드의 동시 회전에 의해 산화막을 원하는 높이만큼 갈아내는 화학적 기계적 연마 기법을 많이 사용하고 있다.In detail, the insulating film between the multi-layer wirings may be formed of an HD-USG film alone, which improves the gap fill characteristics of the lower metal pattern, or a double film forming an HD-USG film and re-depositing an oxide film thickly thereon by PE-CVD. Mainly used. The planarization after deposition uses a chemical mechanical polishing technique that grinds an oxide film to a desired height by simultaneously rotating a wafer and a polishing pad through a slurry.

화학적기계적 연마는 광역평탄화에 유리하여 널리 사용되고 있으나, 일반적으로 화학적기계적 연마공정후 웨이퍼 중앙과 가장자리 부분의 단차는 무시못할 정도로 크며, 촉매제인 슬러리가 깨끗이 제거되지 않는 경우가 많다.Chemical mechanical polishing is widely used because of the advantages of wide-area flattening, but in general, the step difference between the center and the edge of the wafer after the chemical mechanical polishing process is negligibly large, and the slurry as a catalyst is often not removed.

종래 화학적 기계적 연마공정은 다음과 같은 문제점이 있다.The conventional chemical mechanical polishing process has the following problems.

첫째, 화학적 기계적 연마공정은 슬러리(Slurry)를 이용하여 실시하는데, 슬러리의 종류에 따라 연마 정도의 변수가 많아 연마 평가 및 최적의 연마 조건을 분석하는데 많은 시간이 소요된다.First, the chemical mechanical polishing process is carried out using a slurry (Slurry), a large amount of the degree of polishing according to the type of slurry, it takes a lot of time to evaluate the polishing and analyze the optimum polishing conditions.

둘째, 화학적 기계적 연마공정시 공정 장비의 파라메타(parameter)에 대한 의존성이 강해 일관성있는 연마공정을 실시하기 어렵다.Second, in the chemical mechanical polishing process, the dependence of the process equipment (parameter) is strong, so it is difficult to carry out a consistent polishing process.

셋째, 화학적 기계적 연막공정시 셀(cell) 및 주변영역의 단차가 큰 영역에서 디싱(dishing) 현상으로 인하여 후속 공정시 찌꺼기 등이 발생하여 후속공정에서 문제를 유발한다.Third, in the chemical mechanical smoke screening process, debris is generated in the subsequent process due to dishing in a region where the step difference between the cell and the peripheral region is large, causing problems in the subsequent process.

넷째, 화학적 기계적 연마공정은 기판을 이루고 있는 물질과 단차에 대한 의존성이 강하여 공정변수를 조절하기 힘들다. 특히, 반도체 소자의 층간절연막인 BPSG막은 붕소 및 인의 함유량에 따라 연마비의 변화 차이가 크게 발생한다.Fourth, the chemical mechanical polishing process has a strong dependence on the material and the step of the substrate, making it difficult to control the process variables. In particular, in the BPSG film, which is an interlayer insulating film of a semiconductor device, a large difference in polishing ratio occurs depending on the content of boron and phosphorus.

다섯째, 화학적 기계적 연마공정은 패턴(pattern)에 따른 일관성 있는 연마가 어려워 고집적화로 갈수록 공정마진이 감소한다.Fifth, the process of chemical mechanical polishing is difficult to achieve consistent polishing according to the pattern (pattern), the process margin decreases toward higher integration.

따라서 화학적 기계적 연마를 대채할 수 있는 평탄화 방법이 필요하다.Therefore, there is a need for a planarization method capable of replacing chemical mechanical polishing.

본 발명은 반도체 소자의 제조과정에서 생기는 토폴리지를 없애기 위해서, 레이저를 이용하여 기판상부의 구조물의 평탄화를 이루는 반도체 제조방법을 제공함을 목적을 한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor manufacturing method for planarizing a structure on a substrate by using a laser in order to eliminate the topologies generated during the manufacturing process of the semiconductor device.

도1 내지 도4는 본 발명의 바람직한 일실시예에 따른 반도체 소자의 제조방법을 나타내는 공정단면도.1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with one preferred embodiment of the present invention.

도5내지 도6은 본 발명의 제2 실시예에 따른 반도체 소자의 제조공정 단면도.5 to 6 are cross-sectional views of the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

* 도면의 주요 부분에 대한 부호 설명* Explanation of symbols on the main parts of the drawing

20 : 기판20: substrate

21 : 제1 층간절연막21: first interlayer insulating film

22 : 금속배선22: metal wiring

23 : 제2 층간절연막23: second interlayer insulating film

24 : 척 장비24: Chuck Equipment

25 : 레이져 조사 장비25: laser irradiation equipment

상기의 목적을 달성하기 위한 본 발명의 일측면에 따르면, 기판상에 층간절연막을 형성하는 단계; 및 상기 기판을 회전시키면서 상기 기판의 측면에서 레이저 빔을 조사하여 상기 층간절연막을 평탄화하는 단계를 포함하는 반도체 제조방법이 제공된다.According to an aspect of the present invention for achieving the above object, forming an interlayer insulating film on a substrate; And planarizing the interlayer insulating film by irradiating a laser beam from a side of the substrate while rotating the substrate.

또한, 본 발명의 타측면에 따르면, 소정 구조물이 형성된 반도체 기판상에 금속배선을 형성하는 단계; 상기 금속배선 상부에 층간절연막을 형성하는 단계; 상기 층간절연막을 선택적으로 식각하여 비아홀을 형성하는 단계; 상기 비아홀을 포함한 전체구조상에 금속막을 형성하는 단계; 및 상기 기판을 회전시키면서 기판의 측면에서 레이저 빔을 조사하여 비아플러그를 형성하는 단계를 포함하는 반도체 제조방법이 제공된다.In addition, according to another aspect of the invention, forming a metal wiring on a semiconductor substrate having a predetermined structure; Forming an interlayer insulating film on the metal wiring; Selectively etching the interlayer insulating film to form via holes; Forming a metal film on the entire structure including the via hole; And irradiating a laser beam from a side of the substrate while rotating the substrate to form a via plug.

본 발명은 반도체 제조과정에서 생기는 단차를 평탄화시키기 위해, 고분해능을 가진 식각레이저를 회전하는 웨이퍼의 옆면으로 조사시켜 기판 상부의 구조물이 평탄화 될 수 있도록 하는 것이다.The present invention is to planarize the structure on the top of the substrate by irradiating the etched laser having a high resolution to the side of the rotating wafer in order to planarize the step generated during the semiconductor manufacturing process.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시 할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

도1 내지 도4는 본 발명의 바람직한 일실시에에 따른 반도체 소자의 제조방법을 나타내는 공정단면도이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with one preferred embodiment of the present invention.

본 발명의 일실시예에 따른 반도체 소자의 제조방법은 먼저 도1에 도시된 바와 같이, 기판(20) 상부에 제1 층간절연막(21)을 형성하고, 그 상부에 금속배선(22)을 형성한다. 이어서 금속배선(22) 상부에 제2 층간절연막(22)을 형성한다. 여기서 제2 층간절연막(22)으로는 갭필(gap-fill) 특성이 우수한 산화막을 4000 ~ 5000Å 범위로 형성한다.In the method of manufacturing a semiconductor device according to an embodiment of the present invention, first, as shown in FIG. 1, the first interlayer insulating film 21 is formed on the substrate 20, and the metal wiring 22 is formed thereon. do. Subsequently, a second interlayer insulating film 22 is formed on the metal wiring 22. Here, the second interlayer insulating film 22 is formed with an oxide film having excellent gap-fill characteristics in the range of 4000 to 5000 GPa.

이어서 도2에 도시된 바와 같이, 제2 층간절연막(22)상부에 제3 층간절연막(23)을 형성한다. 여기서 고분해능의 레이저를 사용하면 10 ~ 100Å 정도 높이를 충분히 조절할 수 있으므로, 종래의 화학적기계적연마 공정에서처럼 제2 층간절연막(22)상부에 제3 층간절연막(23)을 1300~15000Å 정도로 두껍게 형성할 필요는 없다.Next, as shown in FIG. 2, a third interlayer insulating film 23 is formed on the second interlayer insulating film 22. In this case, the high resolution laser can sufficiently adjust the height of about 10 to 100 microseconds. Therefore, as in the conventional chemical mechanical polishing process, it is necessary to form the third interlayer insulating film 23 thickly on the second interlayer insulating film 22 to about 1300 to 15000 microseconds. There is no.

이어서 도3에 도시된 바와 같이, 기판 중심을 축으로 회전할 수 있는 척(chuck) 장비에 웨이퍼를 뒤집어서 부착한다. 뒤집어서 부착하는 이유는 식각시 생기는 부산물이 잘 떨어져 나갈 수 있도록 하기 위함이다.3, the wafer is then inverted and attached to a chuck device that can rotate about the substrate center axially. The reason for attaching upside down is to make sure that the by-products generated during the etching can fall off.

이어서, 식각 레이저는 웨이퍼의 가장자리부터 식각해 나갈 수 있도록 옆면에 위치해야 하고, 척(chuck) 장비에 웨이퍼에 고정되도록 챔버내는 수십 mTorr 정도의 진공을 유지하도록 고진공 펌프를 사용한다.The etch laser should then be located on the side to etch away from the edge of the wafer and use a high vacuum pump to maintain a vacuum of several tens of mTorr in the chamber to be fixed to the wafer in the chuck equipment.

이어서, 레이저를 조사하고 웨이퍼를 회전시켜 제3 층간절연막(23)을 식각한다. 이 때 레이저 빔의 정확한 입사위치, 레이저 파워, 빔의 집속거리, 회전척의 속도등을 조절하여 제3 층간절연막(23)이 평탄화 될 수 있도록 한다.Subsequently, the third interlayer insulating film 23 is etched by irradiating a laser and rotating the wafer. At this time, the third interlayer insulating film 23 may be planarized by adjusting the exact incident position of the laser beam, the laser power, the focusing distance of the beam, and the speed of the rotating chuck.

웨이퍼 가장자리와 중앙부분을 같은 파워, 같은 집속거리로 조사할 경우 균등한 식각이 이루어 지지 않으므로, 웨이퍼 반경과 시간, 그리고 입사빔의 파워에 대한 상관관계를 통하여 적절한 조절이 필요하다.When the wafer edge and the center portion are irradiated with the same power and the same focusing distance, even etching is not performed. Therefore, proper adjustment is required through correlation between the wafer radius, the time, and the power of the incident beam.

이어서 도4에 도시된 바와 같이, 기판 중앙부까지 식각이 완료되면 레이저 빔과 산화막과의 반응에 의해 생기는 부산물을 제거하기 위해 세정공정을 한다. 세정공정으로 PVA(polyvinyl Alcohole) Brush를 이용할 수 있다.Subsequently, as shown in FIG. 4, when etching is completed to the center portion of the substrate, a cleaning process is performed to remove by-products generated by the reaction between the laser beam and the oxide film. PVA (polyvinyl alcohole) brush can be used as a cleaning process.

여기서 생기는 부산물은 화학물질에 의한 불순물이 아니므로 간단하게 제거할 수 있다.The by-products produced here are not chemical impurities and can be easily removed.

전술한 레이저를 이용한 평탄화 방법은 레이저 빔의 파워를 적당히 조절하면 금속매질에도 충분히 식각이 가능하다. 도5는 레이저 빔을 이용하여 비아홀을 형성하는 반도체 제조방법의 공정단면도이다.In the planarization method using the above-described laser, the laser beam can be sufficiently etched by properly adjusting the power of the laser beam. 5 is a process cross-sectional view of a semiconductor manufacturing method of forming a via hole using a laser beam.

도5를 참조하여 살펴보면, 기판(30) 상부에 제1 금속배선(31) 및 층간절연막(32)을 증착하고 선택적으로 식각하여 비아홀(A)을 형성한다.Referring to FIG. 5, a via hole A is formed by depositing and selectively etching the first metal wiring 31 and the interlayer insulating layer 32 on the substrate 30.

이어서, 비아홀(A)이 매립되도록 제2 금속배선(33)을 형성한다.Subsequently, the second metal wiring 33 is formed to fill the via hole A.

이어서, 도6을 참조하여 살펴보면, 기판 중심을 축으로 회전할 수 있는 척(chuck) 장비(36)에 웨이퍼를 뒤집어서 부착하고, 웨이퍼를 회전시키면서 레이저를 이용하여 제2 금속배선(33)를 식각해서 비아플러그(37)를 형성한다. 웨이퍼를 뒤집어서 식각공정을 진행하는 것을 식각시 생기는 부산물을 떨어뜨리기 위한 것이다.Subsequently, referring to FIG. 6, the wafer is inverted and attached to a chuck device 36 that can rotate about the center of the substrate, and the second metal wiring 33 is etched using a laser while rotating the wafer. Thus, the via plug 37 is formed. Inverting the wafer to perform the etching process is to reduce the by-products generated during etching.

전술한 바와 같이 평탄화 방법에 레이저를 사용함으로써, 층칸절연막으로 사용되는 실리콘산화막을 화학적기계적연마 공정으로 연마할 때보다 횔씬 낮은 두꼐로 증착하여도 휠씬 정밀한 평탄도를 얻을 수 있다. 따라서 종래에는 화학적기계적연마 공정으로 연마되는 정도를 고려하여 통상적으로 13000~15000Å정도 증착하였으나 본발명에 의해서는 9000 ~ 10000Å 정도로 증착하면 되어 4000 ~ 5000Å 정도의 층간절연막은 증착할 필요가 없다.As described above, by using a laser in the planarization method, evenly deposited silicon oxide film used as the layer cell insulation film can be obtained even more precisely than when polished by a chemical mechanical polishing process. Therefore, in the related art, in consideration of the degree of polishing by the chemical mechanical polishing process, it is generally deposited about 13000 ~ 15000Å, but according to the present invention is deposited to about 9000 ~ 10000Å, it is not necessary to deposit an interlayer insulating film of 4000 ~ 5000Å.

또한, 고비용의 슬러리를 사용하지 않아도 되고, 화학반응이 필요하지 않으므로 공정시간을 단축할 수 있고, 종전의 화학적기계적연마 공정보다 단차가 거의 없어지게 되므로 후속 비아플러그 등의 공정에서 식각시 에러율을 줄일수 있다.In addition, it does not require the use of expensive slurry, and the chemical reaction is not necessary, so that the process time can be shortened. Since the step is almost eliminated compared to the conventional chemical mechanical polishing process, the error rate during etching in the subsequent via plug process is reduced. Can be.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

본 발명에 의해 반도체 구조의 평탄화를 단축된 공정시간으로 보다 더 정밀하게 할수 있게 되어 반도체 소자의 수율향상이 기대된다.According to the present invention, the planarization of the semiconductor structure can be made more precise with a shorter process time, and the yield of semiconductor devices is expected to be improved.

Claims (4)

기판상에 층간절연막을 형성하는 단계; 및Forming an interlayer insulating film on the substrate; And 상기 기판을 회전시키면서 상기 기판의 측면에서 레이저 빔을 조사하여 상기 층간절연막을 평탄화하는 단계Planarizing the interlayer insulating film by irradiating a laser beam from a side of the substrate while rotating the substrate 를 포함하는 반도체 제조방법.Semiconductor manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막의 평탄화는 상기 층간절연막이 지면을 향하는 상태로 진행하는 것을 특징으로 하는 반도체 제조방법.And planarization of the interlayer insulating film is performed in a state in which the interlayer insulating film faces the ground. 소정 구조물이 형성된 반도체 기판상에 금속배선을 형성하는 단계;Forming metal wiring on a semiconductor substrate on which a predetermined structure is formed; 상기 금속배선 상부에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the metal wiring; 상기 층간절연막을 선택적으로 식각하여 비아홀을 형성하는 단계;Selectively etching the interlayer insulating film to form via holes; 상기 비아홀을 포함한 전체구조상에 금속막을 형성하는 단계; 및Forming a metal film on the entire structure including the via hole; And 상기 기판을 회전시키면서 기판의 측면에서 레이저 빔을 조사하여 비아플러그를 형성하는 단계Irradiating a laser beam from a side of the substrate while rotating the substrate to form a via plug 를 포함하는 반도체 제조방법.Semiconductor manufacturing method comprising a. 제 3 항에 있어서,The method of claim 3, wherein 상기 비아플러그의 형성단계는 상기 금속막이 지면을 향한 상태로 진행하는 것을 특징으로 하는 반도체 제조방법.The forming of the via plug is a semiconductor manufacturing method, characterized in that the metal film proceeds toward the ground.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425395B2 (en) 2014-10-14 2016-08-23 Samsung Electronics Co., Ltd. Method of fabricating a variable resistance memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425395B2 (en) 2014-10-14 2016-08-23 Samsung Electronics Co., Ltd. Method of fabricating a variable resistance memory device

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