CN117690866A - Manufacturing method for chip packaging and chip - Google Patents

Abstract

The invention relates to a manufacturing method for chip packaging and a chip, wherein the manufacturing method for the chip packaging comprises the following steps: depositing a barrier layer on the front surface of the wafer after bonding and thinning, wherein the barrier layer is one or more of SIN, SIC and NDC materials; depositing an oxide layer on the barrier layer; s30, forming a silicon through hole through an etching process, wherein the depth of the silicon through hole reaches a structural layer to be connected; s40, performing electrochemical copper filling in the through silicon via and on the front surface of the wafer; s50, polishing the copper layer and the oxide layer on the surface by using a chemical mechanical polishing process, wherein the polishing depth reaches the barrier layer; s60, carrying out a fine grinding process on the residual copper on the barrier layer, and grinding the residual copper on the barrier layer until no residue exists. The invention solves the technical problems of copper overgrinding and copper residue in the copper grinding process in the prior art.

Description

Manufacturing method for chip packaging and chip

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method for chip packaging and a chip.

Background

Vertical via (TSV) technology is a critical semiconductor fabrication technology for establishing vertical electrical connections from chip to chip or wafer to wafer. TSV technology achieves vertical electrical interconnection of through silicon vias by forming vertical vias in a silicon wafer and filling these vias with a conductive material such as copper, tungsten, or polysilicon. This technology is the key to 3D advanced packaging, which allows for higher integration chips and faster data transfer speeds.

One of the key steps in the TSV fabrication process is the bonding TSV through-silicon via technique. However, in this step, copper filling and grinding of the through-silicon via is a common process step used to planarize the copper fill material to ensure that the conductive layer inside the TSV via does not protrude excessively. In the copper grinding/polishing process in the prior art, uneven grinding can occur, so that the problem of copper residue or dishing defect of copper overgrinding is caused, the surface flatness and connection performance are affected, and the product quality is affected.

Disclosure of Invention

Aiming at the defects existing in the related art, the invention provides a manufacturing method for chip packaging and the chip packaging, and solves the technical problems of copper residue and copper overgrinding.

According to a first aspect of the present application, there is provided a manufacturing method for a chip package, comprising in one possible embodiment the steps of: s10, depositing a barrier layer on the wafer subjected to bonding and thinning, wherein the barrier layer is one or more of SIN, SIC and NDC materials; s20, depositing an oxide layer on the barrier layer; s30, forming a silicon through hole through an etching process, wherein the depth of the silicon through hole is less than or equal to 100um; s40, performing electrochemical copper filling in the through silicon via and on the front surface of the wafer; s50, polishing the copper layer and the oxide layer on the surface by using a chemical mechanical polishing process, wherein the polishing depth reaches the barrier layer; s60, carrying out a fine grinding and polishing process on the residual copper on the barrier layer, and grinding the residual copper on the barrier layer until no residue exists.

In one possible embodiment, the barrier layer has a thickness in the range of 500A to 2000A.

In one possible embodiment, the barrier layer is made of SIN, SIC, NDC or another material having a lower polishing rate than the oxide layer.

In one possible embodiment, depositing the barrier layer includes: s11, depositing a layer of silicon nitride precursor material on the bottom wafer by using a chemical vapor deposition method; and S12, performing heat treatment on the silicon nitride precursor material to form a barrier layer.

In one possible embodiment, the material of the wafer may be silicon or other semiconductor material.

In one possible implementation, in step S30, photolithography is used to etch the through silicon via.

In one possible embodiment, the residual amount of residual copper is controlled by a finish grinding and polishing process.

In one possible implementation, in step S10, the barrier layer is fabricated for all packaging technologies using TSV processes, including 3D packaging processes.

In another method of the present application, a chip is provided, and the method for manufacturing a chip package according to any one of the above embodiments is used.

Based on the technical scheme, the manufacturing method for the chip package and the chip in the embodiment of the invention prevent the copper connection in the through silicon via from being excessively ground and the surface of the wafer from being copper residue by arranging the barrier layer, effectively protect the wafer from being damaged in the subsequent processing process, protect the physical structure and the electrical performance of the chip and improve the product quality.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a flow chart of a method for fabricating a chip package according to one embodiment of the present application;

FIG. 2 is a schematic diagram of a chip structure after depositing a barrier layer and an oxide layer according to a method for fabricating a chip package according to an embodiment of the present application;

fig. 2a is a schematic diagram of a chip structure after etching through silicon vias according to a method for manufacturing a chip package according to an embodiment of the present application;

fig. 3 is a schematic diagram of a chip structure after copper filling according to a method for manufacturing a chip package according to an embodiment of the present application;

fig. 4 is a schematic diagram of a chip structure after polishing a metal copper layer and fabricating a second metal layer according to a method for fabricating a chip package according to an embodiment of the present application.

In the figure:

10. a barrier layer; 20. an oxide layer; 30. a through silicon via; 40. copper metal; 50. a first metal layer; 60. a second metal layer.

Detailed Description

The technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present invention, it should be understood that the terms "center", "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.

The terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", or a third "may explicitly or implicitly include one or more such feature.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In order to solve the problems of copper overgrinding and copper residue in the prior art, an aspect of the present application provides a manufacturing method for chip packaging.

In one possible embodiment, referring to fig. 1, the method for manufacturing the chip package includes the steps of: s10, depositing a barrier layer on the wafer subjected to bonding and thinning, wherein the barrier layer is one or more of SIN, SIC and NDC materials; s20, depositing an oxide layer on the barrier layer; s30, forming a silicon through hole through an etching process, wherein the depth of the silicon through hole reaches a structural layer to be connected; s40, performing electrochemical copper filling in the through silicon via and on the front surface of the wafer; s50, polishing the copper layer and the oxide layer on the surface by using a chemical mechanical polishing process, wherein the polishing depth reaches the barrier layer; and S60, carrying out finish grinding and polishing over polish process on the residual copper on the barrier layer, and grinding the residual copper on the barrier layer until no residue exists.

In the above embodiment, after the wafer is subjected to the bonding and thinning process, first, in step S10, a barrier layer is formed thereon; referring to fig. 2, the barrier layer 10 is formed of one or more of SIN (silicon nitride), SIC (silicon carbide) or NDC (silicon carbide thin film) materials having excellent physical and chemical stability, and can effectively protect the wafer from being damaged during the subsequent processing, and protect the physical structure and electrical properties of the chip.

Further, in step S20, an oxide layer 20 is further deposited on the fabricated barrier layer, see fig. 2; the oxide layer serves as another protective barrier, so that the stability and the integrity of the wafer in the subsequent processing process are ensured, and the structural strength and the insulating performance of the wafer are optimized.

Then, in step S30, a precise etching process is used to form a through silicon via 30 on the wafer, where the depth of the through silicon via 30 is the structure layer to be connected, such as the first metal layer 50, see fig. 2a; in the above-described aspect, the depth of the through silicon via 30 may be controlled to be less than or equal to 100 μm; the precise formation of through silicon vias is used to ensure effective connection of the various parts inside the chip.

Further, in step S40, electrochemical copper filling treatment is performed in the formed through silicon vias and on the front surface of the wafer, see fig. 3 for metallic copper 40; this step consists in using electrochemical means to fill precisely the copper material to form a stable and efficient conductive path, communicating with the first metal layer 50 at the bottom of the chip, the copper filling process not only improving the electrical conductivity of the wafer, but also enhancing the solidity of the overall structure.

Finally, in step S50, the copper layer and the oxide layer 20 on the surface are polished using a chemical mechanical polishing process until the barrier layer 10 is reached, see fig. 4, and the excess copper material and the smooth surface are removed for subsequent processing steps; after this step is completed, an over polish process is performed to ensure that no copper remains on the barrier layer, thereby ensuring perfect planarity and cleaning of the wafer surface.

In one possible embodiment, wherein the thickness of the barrier layer ranges from 500A to 2000A.

In this embodiment, the thickness of the barrier layer is controlled in the range of 500 angstroms (angstrom) to 2000 angstroms during the fabrication of the chip package.

First, the primary function of the barrier layer is to act as a barrier to protect the wafer from damage during subsequent processing steps while ensuring stability and insulation of the package structure. The thickness range of 500A to 2000A provides the best balance in achieving these functions. On the one hand, this thickness is sufficient to provide the necessary protection and insulation; on the other hand, avoiding excessive increases in the overall thickness and weight of the wafer is critical to maintaining wafer flexibility and reducing load.

Within this thickness range, the properties of the barrier material (e.g., silicon nitride, silicon carbide, or silicon carbide film) are maximized. The thickness in this range can effectively prevent penetration of chemicals while withstanding thermal and mechanical stresses that may be encountered during wafer processing; in addition, such a thick barrier layer also has good thermal conductivity, which aids in thermal management of the wafer during operation, particularly in high power applications.

In summary, the precise control of the barrier layer thickness in this embodiment not only represents a profound understanding of material science and microelectronics processes, but also represents a careful consideration of chip packaging requirements. The method not only improves the reliability and efficiency of the packaging process, but also provides a basis for realizing higher-performance microelectronic devices.

In one possible embodiment, the material of the barrier layer is SIN, SIC, NDC, which has a lower polishing rate than the oxide layer 20.

In this embodiment, the material selection of the barrier layer used in the chip package manufacturing process uses SIN (silicon nitride), SIC (silicon carbide), NDC (silicon carbide thin film) and the like. These materials have a lower polishing rate than the oxide layer 20, a property that is critical in the fabrication of chip packages.

Firstly, the low polishing rate of the materials can effectively serve as a barrier layer in a Chemical Mechanical Polishing (CMP) process to prevent excessive polishing; especially when grinding copper and oxide layers to a precise depth, it is ensured that the underlying structural layers are not damaged; the choice of these materials is therefore not only based on their physical and chemical stability, but also taking into account their practical application effect in the manufacturing process.

In addition, the precision and consistency in the manufacturing process can be effectively controlled by using SIN, SIC, NDC and other materials. Because the grinding rate of the materials is lower, the grinding process can be controlled more accurately, so that the flatness and consistency of the wafer are maintained; for subsequent processing steps, such as patterning and metal layer deposition, a higher processing quality is ensured.

In one possible embodiment, depositing the barrier layer includes: s11, depositing a layer of silicon nitride precursor material on the bottom wafer by using a chemical vapor deposition method; s12, carrying out heat treatment on the silicon nitride precursor material, and exposing the silicon nitride precursor material to the atmosphere at the temperature of 300-400 ℃ to form a barrier layer, wherein the heat treatment time is 0.4-10min.

In this embodiment, the barrier layer is fabricated by first depositing a silicon nitride precursor material on the bottom wafer using Chemical Vapor Deposition (CVD) in step S11. This process requires precise control of deposition conditions, including temperature, atmosphere, and pressure, to ensure uniform deposition and proper thickness of precursor materials. Silicon nitride is a critical material for use in microelectronic packaging, particularly in high density integrated circuits. Chemical vapor deposition provides an accurate and controlled way to produce such high quality films.

Next, in step S12, the silicon nitride precursor material is subjected to a heat treatment process to form a final barrier layer. This step is carried out at high temperatures and this heat treatment is intended to improve the stability and insulation properties of the material. In this process, the conditions of the heat treatment, such as temperature and time, are precisely controlled to ensure that the uniformity and performance of the silicon nitride layer meets the packaging requirements. This heat treatment process not only affects the physical and chemical properties of the barrier layer, but also relates to the reliability and durability of the entire chip package.

In addition, this step also allows for compatibility with subsequent packaging processes. For example, the material and thickness of the barrier layer need to be compatible with subsequent oxide layer deposition and through silicon via formation processes. Thus, the fabrication of the barrier layer is not just a single step, but is a comprehensive consideration in the overall chip packaging process.

In one possible embodiment, the material of the wafer may be silicon or other semiconductor material.

In this embodiment, the choice of wafer material is versatile and flexible, and silicon or other types of semiconductor materials may be chosen during fabrication.

Among the above solutions, silicon has found wide application in the microelectronics manufacturing industry as the most commonly used semiconductor material. The main advantages include good electrical properties, mature processing techniques and relatively low cost. The widespread use of silicon wafers in chip fabrication makes it an ideal choice for this embodiment. As one embodiment, other types of semiconductor materials are used, such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon germanium (SiGe), etc.; such materials are superior to silicon in certain properties (such as frequency response, power consumption, or optoelectronic characteristics) making them more desirable in high frequency, high speed, or optoelectronic applications.

In selecting the wafer material, not only the electronic characteristics thereof, but also the compatibility with the packaging technology used are considered; for example, the different semiconductor materials may have different resistances to processing conditions (e.g., temperature and chemical environment) that directly affect the processing of the wafer and the design of the package structure. Therefore, the selection of the wafer material in the present embodiment is not only based on the properties of the material itself, but also based on the consideration of the whole manufacturing process, so as to ensure that the selected material can adapt to various subsequent processing steps.

In one possible implementation, in step S30, the through silicon via is etched using photolithography.

In this embodiment, in the etching step of the through-silicon via in the chip package manufacturing process, the photolithography is used to perform precise etching, so that a fine pattern is precisely formed on the wafer, which is important for the formation of the through-silicon via.

First, in step S30, the main purpose of etching through silicon vias using photolithography is to ensure that the position, size and shape of the vias meet design specifications. This process involves applying a photoresist to the wafer surface and then irradiating the wafer through a mask using a specific light source to transfer the pattern on the mask to the wafer surface. In this way, the location and shape of the through holes can be precisely defined on the wafer.

Subsequently, the portions of the photoresist that were not irradiated with light are removed, leaving exposed silicon regions that were removed by an etching process, and finally through-silicon vias are formed. In this step, the accuracy and uniformity of etching is critical because it directly affects the quality of the through-silicon vias and the performance of the chip.

The application of the photoetching technology not only improves the precision of the manufacture of the silicon through hole, but also greatly increases the flexibility of design. Through the use of precisely controlled light sources, masks and photoresists, various sizes and shapes of vias can be formed to accommodate different design requirements. In addition, photolithography also makes it possible to fabricate a plurality of through holes on a high-density wafer, thereby improving the functionality and integration of chips.

In general, the photoetching method is adopted to etch the through silicon via in the embodiment, so that not only is the accuracy and efficiency of manufacturing the through silicon via improved, but also the wide possibility is provided for the design and manufacture of high-performance chips.

In one possible embodiment, the amount of residual copper remaining is controlled using a finish grinding over polish process.

In this embodiment, an over polish (over polish) process is used to control the amount of copper remaining on the wafer, ensuring the planarity and cleanliness of the wafer surface, thus providing a desirable basis for subsequent package and integrated circuit fabrication.

First, an over polishing (over polishing) process is a fine polishing process performed after a general Chemical Mechanical Polishing (CMP) process. This process consists in removing the residual copper on the wafer surface to prevent any possible short circuits or electrical disturbances, in which step the optical endpoint detection function of the cmp apparatus is used, to control the pressure and time at which the polish reaches the interface and over polish, thus ensuring complete removal of the removal layer (copper) and precise control of the removal of the barrier layer.

The control requirements of the finish polishing process are extremely stringent, as any excessive polishing can lead to damage to the wafer surface, affecting the performance of the entire chip. Thus, this process typically involves fine tuning and real-time monitoring of the polishing parameters, including the speed of the polishing disc (50-100 r/min), the polishing head pressure (main pressure: 1-5 blf), and the type and flow rate of the polishing fluid used (200-500 ml/min). In addition, the surface condition of the wafer also needs to be continuously monitored to ensure uniformity and effect of the polishing process.

In one possible embodiment, the method further comprises the step of manufacturing a second metal layer 60 after finish grinding/polishing, wherein the second metal layer 60 is communicated with metal copper in the through silicon via and further communicated with the first metal layer 50 at the bottom, so that the electrical structure between the upper layer and the lower layer of the chip is communicated.

After finishing the finish grinding process, the residual copper on the wafer surface is effectively removed, so that the wafer has a flat and clean surface. The quality and precision of subsequent process steps such as deposition of metal layers or photoetching are ensured, so that the performance and reliability of the whole chip are improved.

In one possible implementation, in step S10, the barrier layer is fabricated for all packaging techniques using a through silicon via TSV process, including 3D packaging processes.

TSVs are formed by making vertical vias between chips, wafer to wafer; the TSV technology realizes vertical electrical interconnection of silicon through holes through filling of conductive substances such as copper, tungsten, polysilicon and the like, and is the only vertical electrical interconnection technology at present, and is one of key technologies for realizing 3D advanced packaging.

In the above embodiments, the fabrication process of the barrier layer is suitable for using packaging technology through a Through Silicon Via (TSV) process, including advanced 3D packaging processes, and this versatility and adaptability represents the advancement and flexibility of the fabrication method in the field of modern microelectronic packaging.

First, the TSV process is an important innovation in the field of modern microelectronic fabrication, which allows for the creation of vertical connections between different layers of the chip, thus enabling higher signal transmission speeds and more compact package designs. In this embodiment, the fabrication of the barrier layer is optimized to support the requirements of the TSV process; this makes the barrier layer required to have sufficient mechanical strength and chemical stability to withstand the various steps of etching, filling and grinding during TSV fabrication.

Further, the design of the barrier layer becomes particularly important when 3D packaging processes are involved. 3D packaging technology increases integration and performance by stacking multiple wafers or chips in a vertical direction, placing higher demands on accuracy and compatibility of each component. Therefore, the barrier layer is not only suitable for use in single wafer structures, but also complex 3D structures.

In practical application, the barrier layer not only can provide necessary protection and insulation, but also can ensure the integrity and performance of the whole packaging structure; the method can meet the requirements of various TSVs and 3D packages, and provides powerful support for achieving higher performance and smaller microelectronic devices.

In one possible embodiment, a chip is provided, made using the method of making a chip package of any of the above embodiments.

In the above scheme, the chip package is manufactured by any one or more of the manufacturing methods.

The fabrication method of such chip packages takes into account everything from the fabrication of the barrier layer to the finish grinding process, each step being optimized to ensure the quality and performance of the final package. By using advanced materials such as SIN, SIC, and NDC, and precisely controlled processes such as chemical vapor deposition, photolithography, and electrochemical copper filling, the packaging method can achieve complex circuit designs and efficient signal transmission while maintaining wafer integrity.

In addition, the design of such chip packages also takes into account compatibility with TSV technology and 3D packaging processes in particular. By creating connections in the vertical direction of the wafer, TSV technology offers the potential to achieve more compact and high performance packages. At the same time, the use of 3D packaging technology allows higher functional densities to be achieved in smaller space, which is critical to meeting the requirements of modern high performance computing and storage devices.

In such chip packages, each component and layer is carefully designed and fabricated to ensure performance and reliability of the overall package structure. For example, finish grinding and overpolishing the residual copper on the wafer surface not only improves the planarity of the surface, but also prevents potential short circuit risks. The stability of the quality and performance of the chip package at various levels is ensured.

Finally, it should be noted that: in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same; while the invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that: modifications may be made to the specific embodiments of the present invention or equivalents may be substituted for part of the technical features thereof; without departing from the spirit of the invention, it is intended to cover the scope of the invention as claimed.

Claims (8)

1. A method of making a chip package comprising the steps of:

s10, depositing a barrier layer on the bonded and thinned wafer;

s20, depositing an oxide layer on the barrier layer;

s30, forming a silicon through hole through an etching process, wherein the depth of the silicon through hole reaches a structural layer to be connected;

s40, performing electrochemical copper filling in the through silicon via and on the front surface of the wafer;

s50, polishing the copper layer and the oxide layer on the surface by using a chemical mechanical polishing process, wherein the polishing depth reaches the barrier layer;

s60, carrying out a fine grinding process on the residual copper on the barrier layer, and grinding the residual copper on the barrier layer until no residue exists.

2. The method of claim 1, wherein the barrier layer has a thickness in the range of 500A to 2000A.

3. The method of claim 2, wherein the barrier layer is made of a material having a lower polishing rate than the oxide layer, such as SIN, SIC, NDC.

4. A method of making as claimed in claim 3, wherein depositing the barrier layer comprises:

s11, depositing a layer of silicon nitride precursor material on the bottom wafer by using a chemical vapor deposition method;

and S12, performing heat treatment on the silicon nitride precursor material to form a barrier layer.

5. The method of claim 4 wherein the wafer material is silicon or other semiconductor material.

6. The method of claim 5, wherein in step S30, etching the through silicon via is performed by photolithography.

7. The method of claim 1, wherein in step S10, the barrier layer is formed for all packaging technologies using TSV technology, including 3D packaging technology.

8. A chip characterized by a method of manufacturing a chip package using any one of claims 1-7.