KR102231792B1 - 하이브리드 메모리 모듈 및 그것의 동작 방법 - Google Patents

하이브리드 메모리 모듈 및 그것의 동작 방법 Download PDF

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KR102231792B1
KR102231792B1 KR1020170120595A KR20170120595A KR102231792B1 KR 102231792 B1 KR102231792 B1 KR 102231792B1 KR 1020170120595 A KR1020170120595 A KR 1020170120595A KR 20170120595 A KR20170120595 A KR 20170120595A KR 102231792 B1 KR102231792 B1 KR 102231792B1
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무-티엔 창
디민 니우
홍종 정
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삼성전자주식회사
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    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
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    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
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    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/068—Hybrid storage device
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
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    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1048—Scalability
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    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
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    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/221—Static RAM
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/46—Caching storage objects of specific type in disk cache
    • G06F2212/466—Metadata, control data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020170120595A 2017-02-15 2017-09-19 하이브리드 메모리 모듈 및 그것의 동작 방법 Active KR102231792B1 (ko)

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US201762459414P 2017-02-15 2017-02-15
US62/459,414 2017-02-15
US15/587,286 2017-05-04
US15/587,286 US10282294B2 (en) 2017-02-15 2017-05-04 Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter

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KR102231792B1 true KR102231792B1 (ko) 2021-03-25

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US (1) US10282294B2 (https=)
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KR20240087273A (ko) 2022-12-12 2024-06-19 포항공과대학교 산학협력단 하이브리드 메모리 장치 및 그 관리 방법
KR102865250B1 (ko) 2024-04-17 2025-09-30 성균관대학교산학협력단 메모리 소자와 반도체 장치 및 그 동작 방법
KR20250152993A (ko) 2024-04-17 2025-10-24 성균관대학교산학협력단 디램 소자와 반도체 장치 및 그 동작 방법

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KR20240087273A (ko) 2022-12-12 2024-06-19 포항공과대학교 산학협력단 하이브리드 메모리 장치 및 그 관리 방법
KR102865250B1 (ko) 2024-04-17 2025-09-30 성균관대학교산학협력단 메모리 소자와 반도체 장치 및 그 동작 방법
KR20250152993A (ko) 2024-04-17 2025-10-24 성균관대학교산학협력단 디램 소자와 반도체 장치 및 그 동작 방법

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CN108427647A (zh) 2018-08-21
TWI744457B (zh) 2021-11-01
JP2018133086A (ja) 2018-08-23
TW201832086A (zh) 2018-09-01
US20180232310A1 (en) 2018-08-16
JP6916751B2 (ja) 2021-08-11
CN108427647B (zh) 2023-08-08
US10282294B2 (en) 2019-05-07
KR20180094469A (ko) 2018-08-23

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