KR102189920B1 - A method and apparatus for fast decoding a linear code based on bit matching - Google Patents

Abstract

Disclosed are a method for high-speed decoding of a linear code based on bit matching and an apparatus thereof. According to the present invention, the method for high-speed decoding of a linear code based on bit matching may comprise the steps of: hard-deciding a received signal to obtain a hard decision signal; extracting a message signal from the obtained hard decision signal; obtaining a corrected codeword candidate based on the extracted message signal and an error vector according to the current order; calculating a Hamming distance between the obtained corrected codeword candidate and the hard decision signal; comparing the calculated Hamming distance with a threshold based on bit matching; and determining the corrected codeword candidate as a corrected codeword according to the comparison result. Accordingly, it is possible to reduce the computational complexity while maintaining the decoding performance according to an ordered statistics decoder (OSD) as much as possible.

Description

Method and apparatus for high-speed decoding of linear codes based on bit matching {A METHOD AND APPARATUS FOR FAST DECODING A LINEAR CODE BASED ON BIT MATCHING}

The present invention relates to a method and apparatus for high-speed decoding of a linear code based on bit matching, and more particularly, to a technique for determining an error correction codeword at high speed through simple bit matching when the SNR of a received signal is high. .

In digital communication, a decision means a threshold decision based on quantization in a demodulator immediately before the decoder. At this time, the judgment methods include Hard Decision and Soft Decision.

Hard decision means that the waveform output by the demodulator is demodulated into a binary signal (for example, 0 or 1) and then decoded. On the other hand, soft decision means that the output of the demodulator is demodulated into two or more quantized signals and then decoded instead of making a solid integer decision like a hard decision.

Hard decision may cause irreversible information loss in the receiver, but less data processing is required and implementation is simple. On the other hand, soft decision is often used because it requires more data processing and is complicated to implement, but has excellent decoding performance compared to hard plate information.

Meanwhile, the process of decoding the soft-determined signal into the original signal is performed through a combination of information such as conditional probability or likelihood of the soft-determined signal. One of these soft decision-based decoding methods, an ordered statistics decoder (OSD), is attracting a lot of attention because it exhibits a performance that is close to maximum likelihood (ML).

However, since the OSD is similar to a method of finding a codeword that is most similar to the received data among all codewords, the computational complexity in the process of examining all combinations is very high. For example, the amount of computation required for a Gaussian erasure operation generally involved in decoding a received signal is very high.

Therefore, there is a need for a method capable of maintaining high decoding performance while lowering computational complexity.

An object of the present invention for solving the above problems is to provide a method for high-speed decoding of a linear code based on bit matching.

Another object of the present invention for solving the above problems is to provide an apparatus for high-speed decoding of a linear code based on bit matching.

Another object of the present invention for solving the above problems is to provide a method for performing Gaussian elimination at high speed in a method of decoding a linear code.

Another object of the present invention for solving the above problems is to provide an apparatus for performing Gaussian elimination at high speed in a method of decoding a linear code.

An aspect of the present invention for achieving the above object is to provide a method for high-speed decoding of a linear code based on bit matching.

A method of high-speed decoding of a linear code based on bit matching includes the steps of hard-determining a received signal to obtain a hard decision signal, extracting a message signal from the obtained hard decision signal, and the extracted message signal Obtaining a corrected codeword candidate based on an error vector according to the order, calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal, the calculated Hamming distance based on bit matching threshold And determining the error correction candidate word as a corrected codeword according to a comparison result with a value.

The error vector may be defined as a vector having the same length as the message signal and a hamming weight of the current order.

In the obtaining of the error correction candidate word, the error correction candidate word may be obtained by multiplying a value obtained by adding the message signal and the error vector by a generation matrix.

In the step of extracting the message signal, the message signal may be extracted by extracting component values by a number corresponding to the rank of the generation matrix from the hard decision signal.

After the comparing step, if the calculated Hamming distance is greater than the bit matching-based threshold value, the step of increasing the current order and obtaining the error correction candidate word may be performed again.

After the comparing step, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of obtaining the error correction candidate word by changing the generation matrix may be performed again.

The step of determining the error correction candidate word as a corrected codeword may include determining the error correction candidate word as the error correction code word if the calculated Hamming distance is less than or equal to the bit matching-based threshold value. have.

Another aspect of the present invention for achieving the above object is to provide an apparatus for high-speed decoding of a linear code based on bit matching.

An apparatus for high-speed decoding of a linear code based on bit matching includes at least one processor and a memory storing instructions for instructing the at least one processor to perform at least one step ( memory).

The at least one step may include obtaining a hard decision signal by hard-determining the received signal, extracting a message signal from the obtained hard decision signal, and correcting an error based on the extracted message signal and an error vector according to the current order. Obtaining a corrected codeword candidate, calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal, comparing the calculated Hamming distance with a threshold based on bit matching, and according to the comparison result It may include the step of determining the error correction candidate word as an error corrected codeword.

The error vector may be defined as a vector having the same length as the message signal and a hamming weight of the current order.

In the obtaining of the error correction candidate word, the error correction candidate word may be obtained by multiplying a value obtained by adding the message signal and the error vector by a generation matrix.

In the step of extracting the message signal, the message signal may be extracted by extracting component values by a number corresponding to the rank of the generation matrix from the hard decision signal.

After the comparing step, if the calculated Hamming distance is greater than the bit matching-based threshold value, the step of increasing the current order and obtaining the error correction candidate word may be performed again.

After the comparing step, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of obtaining the error correction candidate word by changing the generation matrix may be performed again.

The step of determining the error correction candidate word as a corrected codeword may include determining the error correction candidate word as the error correction codeword when the calculated Hamming distance is less than or equal to the bit matching-based threshold value. .

Another aspect of the present invention for achieving the above object is to provide a method of performing Gaussian elimination at high speed in a method of decoding a linear code.

The method of performing Gaussian elimination at high speed in the decoding method of the linear code includes the steps of generating a heat-exchanged generation matrix by performing column exchange in a substituted generation matrix, and a front end of the heat-exchanged generation matrix. Generating a row-swapped generation matrix by performing row exchange so that the columns located at are forming a partial identity matrix, and Gaussian for the remaining columns excluding the columns constituting the partial identity matrix from the row-exchanged generation matrix. It may include the step of performing erasing.

The generating of the heat-exchanged generation matrix includes, in the replaced generation matrix, columns that are unit vectors among columns corresponding to MRB (Most Reliable Bases) of the received signal are a front end of the heat-exchanged generation matrix. It may include the step of exchanging heat to be located at.

In the generating of the heat exchanged generation matrix, at least one column having a low reliability among columns corresponding to the MRB of the received signal may be excluded from the heat exchange.

Another aspect of the present invention for achieving the above object is to provide an apparatus for performing Gaussian elimination at high speed in a method of decoding a linear code.

An apparatus for performing Gaussian elimination at high speed in a method of decoding a linear code stores at least one processor and instructions for instructing the at least one processor to perform at least one step. It may include a memory (memory).

The at least one step may include generating a heat-exchanged generation matrix by performing column exchange on the replaced generation matrix, and row exchange so that columns located in front of the heat-exchanged generation matrix form a partial unit matrix. exchange) generating a row-exchanged generation matrix, and performing Gaussian erasure on the remaining columns excluding columns constituting the identity matrix from the row-exchanged generation matrix.

The generating of the heat-exchanged generation matrix includes, in the replaced generation matrix, columns that are unit vectors among columns corresponding to MRB (Most Reliable Bases) of the received signal are a front end of the heat-exchanged generation matrix. It may include the step of exchanging heat to be located at.

In the generating of the heat exchanged generation matrix, at least one column having a low reliability among columns corresponding to the MRB of the received signal may be excluded from the heat exchange.

In the case of using the method and apparatus for high-speed decoding of a linear code based on bit matching according to the present invention as described above, it is possible to reduce computational complexity while maximizing the decoding performance according to the OSD.

In addition, by using bit matching in a method of calculating a Hamming distance, there is an advantage in that all procedures such as an alignment process or Gaussian erasure are omitted, and error correction can be performed at a high speed.

On the other hand, in the case of using a method and apparatus for performing Gaussian elimination at high speed in the decoding method of a linear code according to the present invention, the decoding speed is increased because Gaussian elimination is performed at high speed using the characteristics of the generation matrix. There is an advantage that can be improved.

1 is an exemplary diagram for explaining the concept of linear encoding according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating a method of decoding an ordered statistics decoder (OSD) according to an embodiment of the present invention.
3 is a flowchart illustrating a method of decoding probabilistic necessary conditions (PNC) according to an embodiment of the present invention.
4 is a flowchart illustrating a method of decoding probabilistic sufficient conditions (PSC) according to an embodiment of the present invention.
5 is a flowchart illustrating a method for high-speed decoding of a linear code based on soft decision according to an embodiment of the present invention.
6A to 6J are graphs analyzing decoding performance and speed of proposed methods according to an embodiment of the present invention for each order.
7A to 7D are graphs analyzing decoding performance and speed according to Method 2 among proposed methods according to an embodiment of the present invention.
8A to 8H are graphs comparing decoding performance and speed of proposed methods according to an embodiment of the present invention under different experimental conditions.
9A to 9D are graphs analyzing decoding performance and speed according to Method 2 among proposed methods according to an embodiment of the present invention under different experimental conditions.
FIG. 10 is a conceptual diagram illustrating a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention.
11 is a flowchart of a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention.
12 is a flowchart of a method for fast decoding a linear code based on bit matching according to an embodiment of the present invention.
13 is a graph showing a substantial ratio of Gaussian elimination in a method for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention.
14 is a hardware configuration diagram of an apparatus for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention.

In the present invention, various modifications may be made and various embodiments may be provided, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to a specific embodiment, it is to be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention. In describing each drawing, similar reference numerals have been used for similar elements.

Terms such as first, second, A, and B may be used to describe various elements, but the elements should not be limited by the terms. These terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. Does not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary diagram for explaining the concept of linear encoding according to an embodiment of the present invention.

Block coding may refer to a coding method in which data is grouped in a predetermined block unit and encoding and decoding are performed for each block. Linear coding may mean a code in which a set of codewords forms a linear vector space (or satisfies a linear condition).

Referring to FIG. 1, a general linear encoding process may be expressed using a generation matrix (G). If the message m to be transmitted is expressed as a vector of 1×k, the codeword x expressed as a vector of 1Хn can be derived by multiplying the message m by a generation matrix having a size of kХn. Hereinafter, k may mean a dimension (or rank of a generation matrix), and n may mean a length of a codeword.

Here, the generation matrix for generating codewords may be determined in advance according to the type or method of codewords to be used. In general, the larger the minimum distance between codewords is, the higher the error correction capability is, which is advantageous. Here, the minimum distance may mean the smallest distance among Hamming distances between codewords. Also, the Hamming distance may mean the number of different symbols between two codewords.

In addition, the generation matrix for converting a message into a codeword is not limited to a single one, but may be plural. In this case, all of the plurality of generation matrices may convert a specific message into the same codeword. As the number of generation matrices increases, the possibility of error correction in the current order increases, but the amount of calculation performed using a plurality of generation matrices may increase. Accordingly, the number of generation matrices may be determined differently according to a user input or a codeword method used.

The codeword linearly encoded through the above process is transmitted from the transmitting side of the wired/wireless communication system to the receiving side, and the receiving side recovers the original waveform through a demodulator, and uses a decoder to correct errors mixed in the recovered waveform. It can detect and recover valid codewords (or data symbols).

Hereinafter, based on these concepts, a method and apparatus for high-speed decoding of a linear code based on soft decision according to an embodiment of the present invention will be described.

In addition, for convenience of explanation, the transmission channel is AWGN (Additive white Gaussian noise) and the modulation method is described on the premise that BPSK (Binary Phase Shift Keying) is used, but the channel or modulation method is interpreted as being limited. Can't.

FIG. 2 is a flowchart illustrating a method of decoding an ordered statistics decoder (OSD) according to an embodiment of the present invention.

Referring to FIG. 2, in the OSD according to an embodiment of the present invention, a signal received from a decoder may be first sorted in order of magnitude to obtain an alignment signal (S100). For example, if r = (r ₀ , r ₁ , ..., r _n-1 ) is a received signal (where n can be the length of the codeword), the individual components of the received signal (r ₀ , r ₁ , ..., r _n-1 ) by taking absolute values and sorting them in order of magnitude of absolute values to obtain alignment signals y = (y ₀ , y ₁ , ..., y _n-1 ) Can (in the following the alignment signal may be referred to as y). Here, the sorting order may be sorted in descending order, but is not limited thereto, and it is not necessarily sorted according to the size order.

After step S100, a hard decision signal may be obtained by hard-determining the alignment signal y (S110). For example, a hard decision signal Y = (Y ₀ , Y ₁ , ..., Y _n-1 ) may be obtained by hard decision on the alignment signal y (hereinafter, the hard decision signal may be referred to as Y. ). When the hard decision signal Y is obtained, an upper signal corresponding to Most Reliable Bases (MRB) may be obtained from the hard decision signal (S120, hereinafter, the upper signal may be referred to as α). Specifically, in the hard decision signal, the high-order k components (where k may be the dimension described in FIG. 1) with a large size are classified as MRB, the remaining nk components are classified as LRB, and the high-order signal having the highest k components ( α) can be obtained.

After step S120, a substituted error correction candidate word may be obtained using an error vector according to an upper signal α and an order (hereinafter, referred to as o) (S130). Specifically, for example, if an error vector for an arbitrary degree o is denoted by k _o and the substituted generation matrix is denoted by G', an error correction candidate Eo substituted for an arbitrary degree o is the following Equation 1 It can be defined as

Referring to Equation 1, the substituted error correction candidate word E _o may be obtained by multiplying the upper signal α and the error vector k _o according to the order by the substituted generation matrix G′. In a more detailed expression, the substituted error correction candidate word (E _o ) is obtained by multiplying the sum of the upper signal (α) and the error vector (k _o ) according to the order by the substituted generation matrix (G'), or It may be obtained as a sum of a value obtained by multiplying the signal α by the substituted generation matrix G′ and the value obtained by multiplying the error vector k _o by the substituted generation matrix G′. At this time, the substituted generation matrix is obtained by substituting the column of the generation matrix G described in FIG. 1 in the same order as the order in which the previous alignment signal y was generated, and performing Gaussian elimination. Can be. Here, the method according to FIG. 10 to be described later may be applied to the process of performing Gaussian erasure.

In addition, the substituted error correction candidate words have a substituted order according to the substitution order of the substituted generation matrix, and may be defined as a candidate of a corrected codeword. In this case, the substituted generation matrix G'may have a standard form as shown in Equation 2 below.

Referring to Equation 2, I may be an identity matrix having a size of k × k, and P may be a matrix having a size of k × (n-k). Here, if the form as shown in Equation 2 is not formed, the column of the generation matrix G according to FIG. 1 may be appropriately substituted to derive the form according to Equation 2, and at this time, the substituted generation matrix G' The order of substitution for and the order of alignment signals may have to be the same.

Meanwhile, the error vector is interpreted as a vector indicating a component predicted to have an error (or a vector indicating a component predicted to be different from the substituted error correction candidate word among the components corresponding to the MRB of the alignment signal). Specifically, the error vector may be defined as a vector having the same length as the MRB (length of k) and the Hamming weight (the number of non-zero components in the codeword) of the current order (o). For example, when the order is 0, the error vector k ₀ has a Hamming weight of 0, and thus can be derived as in Equation 3 below.

That is, the error vector according to the case where the degree is 0 may be a vector in which all k components are 0. In addition, an error vector for a case of order 1 may be derived as shown in Equation 4 below.

In Equation 4, the location of the component having a value of 1 (or the location of the component predicted to have an error) may vary. That is, a total of k k ₁ can be derived according to the selected location. In addition, the error vector (k ₂ ) for the case of order 2 is derived by selecting two positions among the MRBs, and having only the component values for the selected positions 1 (or non-zero values) and the remaining component values as 0. Can be.

The substituted error correction candidate words are candidates that have the potential to become permuted and corrected codewords, such as a generation matrix whose order is substituted, and can be evaluated through a cost function according to an error vector. For example, it is predicted that the error vector is a vector having 1 in the j-th component as shown in Equation 4 (that is, the error correction candidate word substituted in the j-th component among the components corresponding to the MRB of the alignment signal and the hard decision signal are different). If it is), the cost function can be defined as in Equation 5 below.

Referring to Equation 5, the cost function is the size of the j-th component in the alignment signal (y), and among the components corresponding to the remaining nk LRBs, the substituted error correction candidate word (E _i ) and the hard decision signal ( It can be defined as the sum of the sizes of components corresponding to positions where Y _i ) has different values. In addition, as in Equation 3, the cost function for an error vector in which all components are 0 has no component indicated by the error vector, and thus can be defined as Equation 6 below.

Specifically, referring to Equation 6, the cost function for an error vector having a degree of 0 according to Equation 3 is that the substituted error correction candidate word and the hard decision signal among the components corresponding to nk LRBs have different values. It can be defined as the sum of the sizes of components corresponding to the location.

In the same manner as in Equations 5 and 6, if the non-zero component indicated by the error vector of degree 2 is the l-th component and the m-th component, the cost function can be defined as in Equation 7 below. .

That is, when Equations 5 to 7 are summarized, the cost function may be defined as an operation of adding all the sizes of components corresponding to positions in which the substituted error correction candidate word and the hard decision signal have different values in the alignment signal.

Therefore, after step S130, the cost for the current order may be calculated using the cost function (S140). Here, the current order may be a variable that starts from 0 and increases by one each time step S130 is passed.

When the cost for the current order is calculated in step S140, the substituted error correction candidate word may be determined as a permuted and corrected codeword according to a result of comparing the calculated cost with the minimum cost (S150). . Here, the minimum cost may mean a minimum value among costs calculated from order 0 to the current order. In a more specific description of step S150, if the calculated cost is less than the minimum cost, a substituted error correction candidate word may be determined as a substituted error correction codeword. Further, if the cost calculated in step S150 is less than the minimum cost, updating the calculated cost to the minimum cost may be included. Meanwhile, when the degree is 0, the cost calculated in step S140 may be determined as the minimum cost, and a substituted error correction candidate word may be determined as a substituted error correction codeword.

After step S150, it is determined whether there is an error vector that can be changed in the current order (S160), and if there is an error vector that can be changed in the current order, the error vector is changed (S180), and the process according to step S130 may be performed again. . Here, the change of the error vector may be performed by varying the position of a non-zero component (or a 1 component) in the error vector.

After step S160, it is determined whether the current order has reached a preset maximum order (S170), and if the maximum order has been reached, the encoding process may be terminated. However, if the maximum order has not been reached, the current order may be increased by one (S190) and may be performed again from step S130. Here, the maximum order is a value that can be input by a user, and can generally be derived by Equation 8 below.

In Equation 8, d may mean the minimum distance of the codeword, and k may mean the dimension.

3 is a flowchart illustrating a method of decoding probabilistic necessary conditions (PNC) according to an embodiment of the present invention.

The OSD described in FIG. 2 has a problem that computational complexity is high and unnecessary computations are repeatedly performed because the cost function is continuously calculated up to a preset maximum order and a substituted error correction candidate word is derived.

In order to reduce such computational complexity, even if the maximum order is not reached, a method of speeding up the decoding by omitting the operation for the subsequent order can be considered. At this time, the PNC (probabilistic necessary conditions) is a method of determining an error correction codeword only from the results of the investigation so far, if there is no possibility that a lower cost than the minimum cost exists even when the order is raised.

Referring to FIG. 3, the PNC may first perform the determination according to step S165 instead of performing steps S160 according to FIG. 2 and determining whether the maximum order has been reached (S170 ). That is, in step S165, among the components of the alignment signal corresponding to the MRB, the sum of components having a small size (hereinafter, may be referred to as an acceleration threshold) may be compared with the minimum cost determined up to the current order (S165). Here, the small components may be selected and added by one more number than the current order, since the number corresponding to the cost function operation for the next order of the current order should be considered.

For example, if the current order is o, the speedup threshold S _PNC for determining whether to perform an operation on the next order o+1 may be defined as in Equation 9 below.

Referring to Equation 9, assuming that the alignment signals are arranged in descending order, the acceleration threshold (S) by adding o+1 components upside down from the k-1th component, which is the last component of the components corresponding to the MRB of the alignment signal. _PNC ) can be determined. On the other hand, if the alignment signals are sorted in ascending order, j=0 to j=o can be added.

As a result of the comparison in step S165, if the sum of the components of the small size is greater than the minimum cost, there is no possibility or a very low possibility of becoming an error correction codeword because the subsequent orders must be greater than the minimum cost according to the current order. Accordingly, if the sum of components having a small size as a result of the comparison in step S165 is greater than the minimum cost, the process of repetitive calculation (S130 to S150) by increasing the order (S190) may be omitted, and decoding may be terminated.

4 is a flowchart illustrating a method of decoding probabilistic sufficient conditions (PSC) according to an embodiment of the present invention.

According to an embodiment of the present invention, another embodiment (PSC, probabilistic sufficient conditions) that reduces the amount of computation by improving the OSD according to FIG. 2 may be provided.

Referring to FIG. 4, after performing step S130 according to FIG. 2, the PSC may perform the process according to step S135 instead of step S140. That is, in step S135, the Hamming distance between the hard decision signal Y and the substituted error correction candidate word E _o according to the current order o is compared with a preset first threshold (S135) and according to the comparison result An error correction candidate may be obtained (S130) by omitting the operations S140 to S150 for the current error vector and changing the error vector of the current order (S180).

Specifically, if the Hamming distance between the hard decision signal and the substituted error correction codeword is greater than (or greater than or equal to) a preset first threshold, the substituted error correction code is unlikely to become an actual error correction codeword. Operations on the current error vector can be omitted and other candidate words of the current order can be calculated.

5 is a flowchart illustrating a method for high-speed decoding of a linear code based on soft decision according to an embodiment of the present invention.

Referring to FIG. 5, a method of high-speed decoding of a linear code based on a soft decision includes the steps of obtaining an alignment signal by arranging the received signal in order of magnitude (S200), and performing a hard decision on the alignment signal. Acquiring a decision signal (S210), obtaining an upper signal corresponding to the most reliable bases (MRB) from the hard decision signal (S220), an error substituted by using the higher signal and an error vector according to the current order Acquiring a permuted and corrected codeword candidate (S230), calculating a cost for the current order using a cost function (S240), and comparing the calculated cost with the minimum cost according to the result It may include determining the substituted error correction candidate word as a permuted and corrected codeword (S250) and determining a predefined speedup condition (S260).

The step of obtaining the error correction candidate word (S230) may include obtaining a substituted error correction candidate word by multiplying the upper signal and the error vector according to the current order by a substituted generation matrix. For example, the substituted error correction candidate word may be obtained according to Equation 1 above. In addition, the substituted generation matrix is obtained by substituting the column of the generation matrix G described in FIG. 1 in the same order as the alignment order in which the previous alignment signal y was generated, and performing Gaussian elimination. Can be.

Here, the method according to FIG. 10 to be described later may be applied to the process of performing Gaussian erasure.

The cost function may be defined as an operation of adding all the sizes of components corresponding to positions in which the substituted error correction candidate word and the hard decision signal have different values in the alignment signal. For example, the cost function may refer to Equations 5 to 7.

The error vector may have the same length as the MRB, and may be defined as a vector whose hamming weight is the current order. For example, the error vector may refer to Equations 3 to 4.

The step of determining the predefined speedup condition (S260) includes calculating a speedup threshold value by adding smaller components among components of the alignment signal corresponding to the MRB, and calculating the speedup threshold value to the minimum cost and It may include the step of comparing. For example, in determining a predefined acceleration condition (S260), the description according to FIG. 3 may be referred to, and Equation 9 may be referred to for the acceleration threshold.

After the comparing step, the step of obtaining the substituted error correction candidate word for the next order of the current order may be performed only when the comparison result is less than the minimum cost.

After obtaining the substituted error correction candidate word (S230), comparing a Hamming distance between the hard decision signal and the substituted error correction candidate word with a preset first threshold. For example, the step of comparing the Hamming distance with a preset first threshold may refer to the description of FIG. 4.

After the step of comparing the Hamming distance with a preset first threshold value, if the comparison result is that the Hamming distance is greater than the preset first threshold value, the operation on the error vector is omitted, and an error vector according to the current order By changing, the step of obtaining the substituted error correction candidate word may be performed. In more detail, reference may be made to the description according to FIG. 4.

On the other hand, when it is determined to perform step S130 for the next order o+1 as a result of determining step S165 as a pre-defined fastening condition for the current order o by applying the PNC according to FIG. 3, step S140 at the order o+1 The cost calculated from may be expressed as Equation 10 below.

Referring to Equation 10, the front end is an operation that adds the magnitudes of o+1 components indicated by the error vector in the alignment signal y according to the MRB, and corresponds to the front end in Equations 5 to 7 I can. In addition, the rear end of Equation 10 is a partial sum of reliability of symbols corresponding to LRB, and may correspond to the rear end of Equations 5 to 7.

In general, since LRBs are values with low reliability, there is a higher probability of error than components corresponding to MRBs. Therefore, γ in Equation 10 can be expected to have a value greater than 0. Using this point, the speedup threshold value defined in Equation 9 (a threshold value for determining whether to omit the operation for the next order o+1) can be changed as shown in Equation 11 below.

Referring to Equation 11, the newly defined high-speed threshold (S _proposed ) is a signal to noise ratio (SNR) and an order and error correction code (code) as factors in the high-speed threshold (S _PNC ) defined in Equation 9. It can be defined as the sum of the function f.

Accordingly, the calculating of the speeding threshold value includes calculating the speeding threshold value by adding a function having a signal to noise ratio (SNR) and an order and an error correction code as factors to the sum of the components having the small size. You may.

Meanwhile, the speedup threshold defined in Equation 9 (threshold value for determining whether to omit the operation for the next order o+1) may be changed as shown in Equation 12 below.

Referring to Equation 12, the newly defined speeding threshold (S _proposed ) is a function (f') having a received vector (expressed as a received vector) as a factor in the speeding threshold (S _PNC ) defined in Equation 9 It can also be defined as an added value.

Here, the received vector may be a vector obtained by substituting a column vector of a received signal or a column vector of a received signal in the same order as the substituted generation matrix G'.

Here, the function (f') having the received vector as a factor is a component of vectors corresponding to the parity of the received vector (the matrix P included in the substituted generation matrix G'according to Equation 2 and the components of the vectors to be calculated) ) Alternatively, an operation of adding all components corresponding to the LRB of the received vector or all components of the received vectors may be included, and an operation of multiplying the addition operation by a proportional constant may further be included.

Accordingly, calculating the speedup threshold may include calculating the speedup threshold by adding a function having a received vector as a factor to the sum of the components having the small size.

Meanwhile, a second preset threshold may be used by replacing or adding the step of comparing the Hamming distance with a preset first threshold value. Specifically, after the step of obtaining the substituted error correction candidate word (S230) (or after the step of comparing with the preset first threshold value), between the hard decision signal and the substituted error correction candidate word Comparing the Hamming distance with a preset second threshold value, and if the Hamming distance is less than the second threshold value, omitting the step of calculating the cost and immediately correcting the substituted error correction candidate word It may further include determining a code word. That is, if the Hamming distance is less than the second threshold, all subsequent processes including the step of calculating the cost may be omitted, and the decoding procedure may be terminated by immediately determining the substituted error correction candidate word as the substituted error correction coder. .

The method of high-speed decoding of linear codes based on soft decision according to FIG. 5 may be referred to as Fast and Scalable Soft Decision decoding methods for linear codes (FSSD) hereinafter.

6A to 6J are graphs analyzing decoding performance and speed of the proposed methods according to an embodiment of the present invention for each order.

In the graphs below, HDD means general hard decision-based decoding, PNC means a case in which step S165 according to FIG. 3 is applied, and in PSC, step S135 in FIG. 4 is additionally applied to the PNC. Means the case. In addition, proposed 1 (Method 1) applies a process of determining the speeding condition using a speeding threshold value newly defined according to Equation 11 above in the flow chart according to FIG. 5, and comparing the second threshold value and the Hamming distance to cost It may mean a method in which the calculation step is omitted.

In addition, proposed2 (Method 2) refers to a method in which the operation on the current error vector is omitted by applying step S135 according to FIG. 4 in addition to Method 1.

In the coded words used in FIGS. 6A to 6J, a BCH (Bose-Chaudhuri-Hocquenghem) code with a code length (n) of 127, a dimension (k) of 64, and a minimum distance (d) of 21 was used. In addition, in consideration of the minimum distance (d) of 21 points for the HDD, it was decided to fix all errors of 10 or less. In addition, in the graph, the vertical axis represents a code error rate (WER) or a decoding speed (Speed-up) representing decoding performance. Also, in the graph, the horizontal axis represents SNR (signal-to-noise ratio). In this case, the decoding speed is a relative indication of how fast the decoding speed is compared with the full ssearch algorithm of the OSD described in FIG. 2. In each experiment, all data was quantized to 7 bits, and the first preset threshold according to the PSC of FIG. 4 was set to 25, and the second threshold according to the description of FIG. 5 was set to 10. In addition, in method 1 (proposed 1) and method 2 (proposed 2), the value of the function (f) having the signal to noise ratio (SNR) and the order and error correction code as factors is 346.5, 346.5, 321.3, respectively from orders 1 to 5, respectively. 270.9 and 270.9 were used.

6A to 6J, a result of comparing decoding performance and speed for orders 1 to 5 can be confirmed. As can be seen from the graph, Method 1 and Method 2 are almost the same in terms of decoding performance as PNC and PSC. In addition, as for the decoding speed, Method 1 and Method 2 are significantly faster than that of PNC and PSC. In the case of Method 1, there is a section in which the decoding speed is slower than that of the PSC at low SNR, but it can be seen that the decoding speed of Method 2 rapidly converges as the SNR increases. It can be seen that method 2 exhibits a much faster decoding speed than all other methods.

Specifically, Method 1 and Method 2 are up to about 13770 times faster (Method 1) and 14609 times (Method 2) compared to OSD-FS according to each order, and up to about 336 times faster than PNC (Method 1). , And 797 times (Method 2) is faster. And compared to PSC, it is about 61 times faster (Method 1) and 139 times (Method 2) faster.

7A to 7D are graphs analyzing decoding performance and speed according to Method 2 among proposed methods according to an embodiment of the present invention.

Experimental conditions in FIGS. 7A to 7B are the same as those of FIGS. 6A to 6J.

7A to 7B, it is possible to check the decoding performance and speed of Method 2 according to each order. Here, the decoding speed shown in FIG. 7B represents a relative speed compared to the OSD-FS (full search) in order 1. Specifically, Method 2 converges to the speed of the OSD-FS according to the order 1 regardless of the order as the SNR increases. That is, when the SNR becomes more than a certain degree, the higher the order, the better the decoding performance is, and the computational complexity can be minimized.

7C to 7D, in method 2 (proposed2), the signal to noise ratio (SNR) and the function value (indicated by β in the graph) having the order and error correction code as factors are changed. You can check the decoding performance and speed. In this case, the decoding speed represents a relative speed compared to the OSD-FS in order 4. From the viewpoint of decoding performance, the same performance is exhibited before the β value exceeds a specific value, and as the β value increases, the decoding performance gradually decreases. The decoding speed exhibits a characteristic that becomes faster and faster as the β value increases. In other words, a detailed trade-off relationship between decoding performance and decoding speed is established according to the value of β, so that the user can change the parameters to suit the system environment.

8A to 8H are graphs comparing decoding performance and speed of proposed methods according to an embodiment of the present invention under different experimental conditions.

In FIGS. 8A to 8H, a BCH code having a length of 255, a dimension of 131, and a minimum distance of 37 is used. Also, since the minimum distance of the HDD is 37, all errors of 18 or less are set to be fixed. In this case, the decoding speed is a relative indication of how fast the decoding speed is compared to the full ssearch algorithm (OSD-FS) of the OSD described in FIG. 2. In each experiment, all data was quantized to 7 bits, and the first preset threshold according to the PSC of FIG. 4 was set to 46, and the second threshold according to the description of FIG. 5 was set to 18. In addition, in method 1 (proposed 1) and method 2 (proposed 2), the value of the function (f) having the signal to noise ratio (SNR) and the order and error correction code as factors is 706.8, 706.8, 706.8, respectively from orders 1 to 7, It was set to 706.8, 706.8, 644.8, and 620.0.

The decoding performance of the codewords used in FIGS. 6A to 6J is no longer improved even when the order exceeds 5, but when the codewords used in FIGS. 8A to 8H are increased to the order 7, the decoding performance is certainly improved. However, in the case of PSC or PNC, since it takes a tremendous amount of time even in order 5, performances up to order 4 are compared in FIGS. 8A to 8H.

8A to 8H, methods 1 to 2 show substantially the same performance in terms of decoding performance as PNC and PSC. In contrast, the decoding speed of Methods 1 to 2 is about 5287 times faster (Method 1) and 7420 times (Method 2) compared to OSD-FS for each order, and up to about 747 times faster than PNC (Method 1). ), and 1775 times (Method 2) is faster. And, compared to PSC, up to about 101 times (Method 1) and 240 times (Method 2) are faster. In addition, when the order is increased by 5 or more and compared, methods 1 to 2 can be predicted to be significantly faster compared to PNC or PSC.

9A to 9D are graphs analyzing decoding performance and speed according to Method 2 in different experimental conditions among proposed methods according to an embodiment of the present invention.

The experimental conditions of FIGS. 9A to 9D are the same as those of FIGS. 8A to 8H.

9A to 9B, the decoding performance and the decoding speed of Method 2 according to each order can be checked. In this case, the Relative Speed of FIG. 9B represents a relative speed compared to the OSD-FS in order 1.

As shown in FIG. 9A, it can be seen that as the order increases, the decoding performance of Method 2 significantly increases. As in Figs. 6A to 6J, method 2 rapidly converges to the OSD-FS speed of order 1 as the SNR increases regardless of the order. That is, when the SNR becomes more than a certain degree, it can be seen that the computational complexity always maintains a constant level (lowest level) regardless of the order.

9C to 9D, in method 2 (proposed2), when the function value (indicated by β in the graph) having the signal to noise ratio (SNR) and the order and error correction code as factors is changed. You can check the decoding performance and speed. Here, the decoding speed represents a relative speed compared to the OSD-FS in order 4. As in FIGS. 7A to 7D, the same decoding performance is displayed before the β value exceeds the specific value, and the decoding performance gradually decreases after the β value exceeds the specific value. On the contrary, the decoding speed exhibits a characteristic that the speed increases as the value of β increases. Using these characteristics, the user can change the parameters to suit the system environment.

10 is a conceptual diagram for explaining a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention. 11 is a flowchart of a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention. As described in FIGS. 1 and 2, the substituted generation matrix G′ is the alignment order in which the alignment signal y is generated prior to the column of the generation matrix G described in FIG. It can be obtained by substituting in the same order as the order of reliability magnitude) and performing Gaussian elimination.

In this way, the decoding method of a linear code based on soft decision is Gaussian elimination for a matrix (e.g., generation matrix G or parity check matrix) having a size of k×n (or n×k when rows and columns are configured in reverse). Including the process of doing it. In this case, k may mean the dimension (or the rank or rank of the generation matrix), and n may mean the length of the codeword.

Here, the generation matrix G has a full rank, and generally has a characteristic of a systematic shape. The meaning that the code format has a systematic characteristic may mean that a message (or information bit string) having a length of k is included in a code word having a length of n without modification. Accordingly, a systematic codeword may have a form in which a message sequence and a parity sequence are separated from each other. For example, a message sequence may be located before or after the codeword, and a parity column may be located in the remaining columns. In addition, in a systematic code, the generation matrix has an identity matrix having a size of k×k in the part corresponding to the message column of the systematic codeword, and a parity matrix having a size of k × (nk) in the remaining part. Can have

For example, the generation matrix G according to the systematic codeword may be expressed as Equation 13 below.

In Equation 13, the matrix I _k is a part corresponding to the message column, and may be a unit matrix having a size of k×k, and the matrix P may be a parity matrix having a size of k×(nk). In addition, u ₀ to u _k-1 may be unit vectors in which the k-th component value is 1 and the remaining component values are 0. In FIG. 11, this generation matrix G is represented as an exemplary matrix.

The substituted generation matrix G'used in the decoding method (denoted as the Previous Method) according to FIGS. 2 to 5 is a column of the generation matrix G expressed as Equation 13 as described in FIG. 2. ) Can be generated by exchanging heat according to the order of the reliability magnitude of the received signal. At this time, columns corresponding to k components with a high reliability level in the received signal (which may be components corresponding to the message signal in the received signal, and hereinafter may be referred to as MRB of the received signal) are indicated as MRB in FIG. And, the columns corresponding to the remaining components (hereinafter, may be referred to as LRB of the received signal) are indicated as LRB. That is, the specific column in the substituted generation matrix G'may be a unit vector corresponding to the message column in Equation 13 or a column belonging to the parity matrix P (parity vector). Therefore, in the decoding method according to FIGS. 2 to 5, it is difficult to utilize the characteristic according to Equation 13 because Gaussian erasure is performed as it is for the entire substituted generation matrix G'.

In an embodiment of the present invention, a method of performing Gaussian erasure at high speed may be proposed by minimizing the amount of computation required for Gaussian erasure by using the characteristic of the generation matrix expressed as in Equation 13.

Referring to FIG. 11, in the fast Gaussian erasure method according to an embodiment of the present invention, a step of generating a heat-exchanged generation matrix Gc by performing a column exchange in a substituted generation matrix G′. (S300), generating a row-exchanged generation matrix by performing row exchange so that columns located in front of the column-exchanged generation matrix form a partial unit matrix (S310), and in the row-exchanged generation matrix A step (S320) of performing Gaussian erasure on the remaining columns excluding the columns constituting the partial identity matrix may be included.

Here, the substituted generation matrix G'may be generated by exchanging columns of each column of the generation matrix according to the order of the reliability level of the received signal.

In the step of generating the heat-exchanged matrix Gc (S300), among the columns corresponding to the Most Reliable Bases (MRB) of the received signal in the substituted generation matrix G', columns that are unit vectors are , It may include the step of exchanging heat so as to be located at the front end of the heat exchanged generation matrix (Gc). For example, referring to FIG. 10, among the columns marked with MRB of the substituted generation matrix G', the columns corresponding to the unit vector are heat-exchanged so that they are located at the front end of the heat-exchanged generation matrix Gc. I can confirm.

Accordingly, according to an embodiment of the present invention, Gaussian erasing is performed at high speed by performing Gaussian erasing on only the remaining columns excluding columns forming a partial identity matrix in the row-exchanged matrix (G _r ). can do. Referring to FIG. 10, the partial identity matrix may be a matrix partially in the form of an identity matrix E.

As a result, Gaussian elimination is performed only for the rest of the matrix except for the partial identity matrix, so in the Gaussian elimination process, a non-zero coefficient at the front of each row is determined as a pivot, and the other row is erased around the determined pivot. Since the process of performing (forward elimination) and back-substitution can be omitted, Gaussian erasure can be quickly performed.

Meanwhile, among the columns corresponding to the MRB of the received signal in the substituted generation matrix G', m columns with low reliability have a high probability of error, so it may be desirable to target Gaussian erasure. Here, the variable m may be determined differently according to the user's setting.

That is, in the step of generating the column-exchanged generation matrix (S300), at least one column having a low reliability among columns corresponding to the MRB of the received signal may be excluded from the column exchange. When the method of performing Gaussian elimination at high speed described above is applied to a method and apparatus for decoding a linear code, the experimental effects are shown in Table 1 below.

In Table 1, the speed is the speed implemented using C language in the i7-4790K PC, the existing speed is the speed to which Gaussian erasure is applied in the decoding method according to FIGS. 2 to 5, and the proposed speed is according to FIG. It may be a speed when fast Gaussian erasure is applied to the decoding method according to FIGS. 2 to 5. In addition, in the fast Gaussian erasure in Table 1, the variable m (the number of columns with low reliability) is set to 5. As can be seen in Table 1, a method of performing Gaussian erasure at a high speed according to an embodiment of the present invention is described. When applied to the decoding method according to FIGS. 1 to 5, there is an effect of improving speed by at least 30% to 50% or more.

12 is a flowchart of a method for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention.

In the decoding method according to FIGS. 2 to 5, the fastest operation speed may be a case where an error correction codeword is immediately determined when the current order is 0 and the decoding procedure is terminated. When the current order is 0, the meaning that the error correction codeword can be determined immediately may mean that the signal to noise ratio (SNR) of the received signal is very large and there are very few bits in which errors occur.

As such, even if it is assumed that the operation speed is the fastest in the decoding method according to FIGS. 2 to 5, at least, a process of sorting received signals in order of reliability magnitude, a process of substituting the generation matrix G according to the ordered order, Gaussian It is necessary to perform a process of generating the permuted generation matrix G'through erasure and a process of determining an error correction codeword through cost calculation for the current order 0.

In this way, the amount of computation occupied by Gaussian elimination in the minimum required computation process exceeds about 40%. An embodiment of the present invention proposes a method of quickly determining an error correction codeword using bit matching without an operation process such as Gaussian erasure when the SNR of a received signal is very large and an error occurs small.

Referring to FIG. 12, a method for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention includes the step of hard-determining a received signal to obtain a hard-decision signal (S400). Extracting a message signal from the hard decision signal (S410), obtaining an error correction candidate word based on the extracted message signal and an error vector according to the current order (S420), the obtained error correction candidate word and the hard decision signal Computing a Hamming distance between (S430), comparing the calculated Hamming distance with a bit matching-based threshold (S440), and determining the error correction candidate word as an error correction coder according to the comparison result (S450) It may include.

The method of high-speed decoding of a linear code based on bit matching will be sequentially described again. In the above method, a hard decision signal may be obtained by first hard-determining a signal received by the decoder (S400). For example, when r = (r ₀ , r ₁ , …, r _n-1 ) is a received signal (where n can be the length of the codeword), the hard decision signal is R = (R ₀ , It may be R ₁ , …, R _n-1 ).

Next, a message signal may be extracted from the obtained hard decision signal (S410). Here, the message signal may be extracted by extracting component values as many as the number corresponding to the rank (variable k) of the generation matrix from the hard decision signal. In more detail, the message signal may be extracted by extracting k component values of a preset position from the hard decision signal. Here, the preset position may vary according to a method of generating a message as a code word using a generation matrix, as shown in FIG. 1. For example, if the generation matrix is in the form according to Equation 13 above, since the received signal components at positions corresponding to the identity matrix I _k become message signals, the hard decision signal R = (R ₀ , R ₁ , ..., The _first k component values in R _n-1 ) are the message signal R _m = (R ₀ , R ₁ , R ₂ , …,R _k-1 ) = (m ₀ , m ₁ , m _{2 ,,} m _{k- 1} ) can be.

Next, an error correction candidate word may be obtained based on the extracted message signal and an error vector according to the current order (S420). Here, the error vector may be defined as a vector having the same length as the message signal and a hamming weight of the current order. For example, if the current degree is 0 (in the case of the first trial), the error vector may be a vector in which all components are 0 and length k. In addition, the description of Equations 3 and 4 of FIG. 2 may be referred to for error vectors.

In the step of obtaining the error correction candidate word (S420), the error correction candidate word may be obtained by multiplying a value obtained by adding the message signal and the error vector by a generation matrix. For example, the error correction candidate word may be obtained according to Equation 14 below.

In Equation 14, when the current order is o, E _o is an error correction candidate word, Rm is a message signal, G is a generation matrix, and k _o may be an error vector. In the step of obtaining the error correction candidate word, if the current degree is 0 (in the case of the first trial), since all components of the error vector are 0, error correction is performed by multiplying the message signal and the generation matrix without adding the error vector to the message signal. It may be interpreted that the candidate word is obtained.

After step S420, a Hamming distance between the obtained error correction candidate word and the hard decision signal may be calculated (S430), and the calculated Hamming distance may be compared with a threshold based on bit matching (S440). Here, the error correction candidate word may be directly determined as an error correction code word according to the comparison result (S450). For example, if the calculated Hamming distance is less than or equal to the threshold based on bit matching, it is assumed that an error has occurred in the received signal, and an error correction candidate word may be immediately determined as an error correction coder. Here, the bit matching-based threshold may be determined differently according to a user's setting.

On the other hand, if the calculated Hamming distance is greater than the bit matching-based threshold, the current order is increased (S445a) and the step of obtaining the error correction candidate word (S420) may be performed again. When the step of acquiring the error correction candidate word is performed again, an error correction candidate word may be obtained using an error vector in which the Hamming weight increases by one as the current order increases by one.

In addition, if the calculated Hamming distance is greater than the bit matching-based threshold, the step (S420) of obtaining the error correction candidate word by changing the generation matrix (S445b) instead of increasing the current order may be performed again. For example, when there are a plurality of generation matrices that generate the same codeword for a specific message, error correction may be performed by obtaining an error correction candidate word using another generation matrix. When the error correction codeword is not determined up to the maximum order (o' _max ), one of the methods of FIGS. 2 to 5 is performed, so that processes such as sorting, obtaining a substituted generation matrix through Gaussian elimination, and calculating cost are performed. I can. Here, the maximum order (o' _max ) may be determined according to a user's setting.

As described above, in the present invention, by using bit matching in a method of calculating a Hamming distance between an error correction candidate word and a hard decision signal, all procedures such as signal alignment and Gaussian erasure are omitted, and error correction can be performed at a high speed. have.

13 is a graph showing a substantial ratio of Gaussian elimination in a method for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention.

In FIG. 13, the vertical axis represents the ratio of the time used for the Gaussian erasure operation when the FSSD according to FIG. 5 is performed compared to the time used for the Gaussian erasure operation when the method of fast decoding the bit matching-based linear code according to FIG. 12 is applied. Is shown.

In addition, as for the coded word, a BCH (Bose-Chaudhuri-Hocquenghem) code with a code length (n) of 127, a dimension (k) of 64, and a minimum distance (d) of 21 was used. In addition, in the FSSD according to FIG. 5, the first threshold is 25, the order (o) is 5, and the second threshold is 10, and the bit matching-based threshold used in the method according to FIG. 12 is 10, and the order ( o) used 2.

When the error correction codeword is determined according to the method according to FIG. 12, since the Gaussian erasure operation is omitted, the degree to which the Gaussian erasure operation is omitted can be determined by referring to the graph of FIG. 13.

For example, when the SNR is 3.0, the ratio occupied by the Gaussian erasure operation in the graph of FIG. 13 is 88.6% (or 0.886). That is, in the case of the existing algorithm (FSSD, Fig. 5), the time spent in Gaussian erasure operation is 15.20 μs, and the method according to FIG. 12 performs one Gaussian erasure for 13.46 μs, which is 88.6% of the previously consumed time. Can be interpreted. Therefore, it means that a number of operations including Gaussian erasure have been omitted.

In addition, when the SNR is 5.5, the ratio occupied by the Gaussian erasure operation in the graph according to FIG. 13 is 28.9% (or 0.289). That is, when the method according to FIG. 12 is used, it means that one Gaussian erasure is performed on average during 4.40 μs, which is 28.9% of the Gaussian erasure operation time according to the existing algorithm (FSSD, FIG. 5).

In addition, as can be seen from the Gaussian erasure ratio according to the SNR in FIG. 13, it can be seen that the method according to FIG. 12 skips various operations including Gaussian erasure as the SNR increases, thereby increasing the speed more and more. Accordingly, the method according to FIG. 12 does not have a large performance improvement when the SNR is low, but there is an advantage that the operation speed can be greatly improved when the SNR is large.

14 is a hardware configuration diagram of an apparatus for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention.

Referring to FIG. 14, the apparatus 100 for high-speed decoding of a linear code based on bit matching includes at least one processor 110 and the at least one processor 110 performing at least one step. It may include a memory (memory, 120) that stores instructions (instructions) to be executed.

In addition, the apparatus 100 for high-speed decoding of a linear code based on bit matching may include a transceiver 130 that communicates with a base station through a wired or wireless network. In addition, the apparatus 100 for high-speed decoding of a linear code based on bit matching may further include an input interface device 140, an output interface device 150, and a storage device 160. Each component included in the apparatus 100 for high-speed decoding of a linear code based on bit matching may be connected by a bus 170 to perform communication with each other.

Here, the processor 110 may refer to a central processing unit (CPU), a graphics processing unit (GPU), or a dedicated processor in which methods according to embodiments of the present invention are performed. Each of the memory 120 and the storage device 160 may be configured with at least one of a volatile storage medium and a nonvolatile storage medium. For example, the memory 120 may be formed of at least one of read only memory (ROM) and random access memory (RAM).

The at least one step may include obtaining a hard decision signal by hard-determining the received signal, extracting a message signal from the obtained hard decision signal, and correcting an error based on the extracted message signal and an error vector according to the current order. Obtaining a corrected codeword candidate, calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal, comparing the calculated Hamming distance with a threshold based on bit matching, and according to the comparison result It may include the step of determining the error correction candidate word as an error corrected codeword.

The error vector may be defined as a vector having the same length as the message signal and a hamming weight of the current order.

In the obtaining of the error correction candidate word, the error correction candidate word may be obtained by multiplying a value obtained by adding the message signal and the error vector by a generation matrix.

In the step of extracting the message signal, the message signal may be extracted by extracting component values by a number corresponding to the rank of the generation matrix from the hard decision signal.

After the comparing step, if the calculated Hamming distance is greater than the bit matching-based threshold value, the step of increasing the current order and obtaining the error correction candidate word may be performed again.

After the comparing step, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of obtaining the error correction candidate word by changing the generation matrix may be performed again.

The step of determining the error correction candidate word as a corrected codeword may include determining the error correction candidate word as the error correction code word if the calculated Hamming distance is less than or equal to the bit matching-based threshold value. have.

Examples of the apparatus 100 for high-speed decoding of linear codes based on bit matching include a desktop computer, a laptop computer, and a notebook capable of communicating according to error correction coding. Smartphone (smart phone), tablet PC (tablet PC), mobile phone (mobile phone), smart watch (smart watch), smart glass (smart glass), e-book reader, PMP (portable multimedia player), portable game console, Navigation device, digital camera, digital multimedia broadcasting (DMB) player, digital audio recorder, digital audio player, digital video recorder, digital video It may be a player (digital video player), PDA (Personal Digital Assistant), or the like.

Meanwhile, the apparatus having a hardware component according to FIG. 14 may also be used as an apparatus for performing a fast Gaussian elimination method in the method of decoding a linear code described in FIG. 11.

For example, an apparatus for performing Gaussian elimination at high speed in a decoding method of a linear code may allow at least one processor 110 and the at least one processor 110 to perform at least one step. It may include a memory (memory, 120) that stores instructions (instructions).

The at least one step may include generating a heat-exchanged generation matrix by performing column exchange in the generation matrix, and row exchange so that columns located in front of the heat-exchanged generation matrix form a unit matrix. ) To generate a row-swapped generation matrix, and performing Gaussian erasure on the remaining columns of the row-swapped generation matrix except for columns forming the identity matrix.

The generating of the heat-exchanged generation matrix includes, in the replaced generation matrix, columns that are unit vectors among columns corresponding to MRB (Most Reliable Bases) of the received signal are a front end of the heat-exchanged generation matrix. It may include the step of exchanging heat to be located at.

In the generating of the heat exchanged generation matrix, at least one column having a low reliability among columns corresponding to the MRB of the received signal may be excluded from the heat exchange.

The methods according to the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like alone or in combination. The program instructions recorded on the computer-readable medium may be specially designed and configured for the present invention, or may be known and usable to those skilled in computer software.

Examples of computer-readable media may include hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions may include high-level language codes that can be executed by a computer using an interpreter or the like as well as machine language codes such as those created by a compiler. The above-described hardware device may be configured to operate as at least one software module to perform the operation of the present invention, and vice versa.

In addition, the above-described method or apparatus may be implemented by combining all or part of its configuration or function, or may be implemented separately.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

Claims (17)

A method of high-speed decoding of a linear code based on bit matching,
Hard-determining the received signal to obtain a hard-decision signal;
Extracting a message signal from the obtained hard decision signal;
Obtaining a corrected codeword candidate based on the extracted message signal and an error vector whose order is determined according to a Hamming weight;
Calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal;
Comparing the calculated Hamming distance with a threshold based on bit matching; And
And determining the error correction candidate word as an error corrected codeword according to a comparison result, a method for fast decoding a linear code based on bit matching. In claim 1,
The error vector is,
A method of fast decoding a linear code based on bit matching, having the same length as the message signal. In claim 1,
Obtaining the error correction candidate word,
A method for fast decoding a linear code based on bit matching, wherein the error correction candidate word is obtained by multiplying the sum of the message signal and the error vector by a generation matrix. In claim 3,
The step of extracting the message signal,
A method for high-speed decoding of a linear code based on bit matching, in which the message signal is extracted by extracting values of components in the hard decision signal by a number corresponding to the rank of the generation matrix from the hard decision signal. In claim 3,
After the comparing step,
If the calculated Hamming distance is greater than the bit matching-based threshold, increasing the order according to the Hamming weight of the error vector and re-performing the step of obtaining the error correction candidate word, a method of fast decoding a linear code based on bit matching . In claim 3,
After the comparing step,
If the calculated Hamming distance is greater than the bit matching-based threshold, re-performing the step of obtaining the error correction candidate word by changing the generation matrix to another generation matrix that generates the same codeword for a specific message. A method for high-speed decoding of linear codes with a method. In claim 5,
The step of determining the error correction candidate word as a corrected codeword,
If the calculated Hamming distance is less than or equal to the bit matching-based threshold value, determining the error correction candidate word as the error correction coder, a method for high-speed decoding of a linear code based on bit matching. delete delete delete As a device for high-speed decoding of a linear code based on bit matching,
At least one processor; And
Including a memory (memory) for storing instructions (instructions) instructing the at least one processor to perform at least one step,
The at least one step,
Hard-determining the received signal to obtain a hard-decision signal;
Extracting a message signal from the obtained hard decision signal;
Obtaining a corrected codeword candidate based on the extracted message signal and an error vector whose order is determined according to a Hamming weight;
Calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal;
Comparing the calculated Hamming distance with a threshold based on bit matching; And
And determining the error correction candidate word as an error corrected codeword according to a comparison result, and fast decoding a linear code based on bit matching. In claim 11,
The error vector is,
An apparatus for fast decoding a linear code based on bit matching, having the same length as the message signal. In claim 11,
Obtaining the error correction candidate word,
An apparatus for high-speed decoding of a linear code based on bit matching, wherein the error correction candidate word is obtained by multiplying the sum of the message signal and the error vector by a generation matrix. In claim 13,
The step of extracting the message signal,
An apparatus for high-speed decoding of a linear code based on bit matching, wherein the message signal is extracted by extracting values of components in the hard decision signal by a number corresponding to the rank of the generation matrix from the hard decision signal. In claim 13,
After the comparing step,
If the calculated Hamming distance is greater than the bit matching-based threshold, increasing the order according to the Hamming weight of the error vector and re-performing the step of obtaining the error correction candidate word, an apparatus for high-speed decoding of a linear code based on bit matching . In claim 13,
After the comparing step,
If the calculated Hamming distance is greater than the bit matching-based threshold, re-performing the step of obtaining the error correction candidate word by changing the generation matrix to another generation matrix that generates the same codeword for a specific message. A device that decodes linear codes at high speed. In claim 13,
The step of determining the error correction candidate word as a corrected codeword,
When the calculated Hamming distance is less than or equal to the bit matching-based threshold value, the error correction candidate word is determined as the error correction coder, and a fast decoding apparatus for a linear code based on bit matching.

Images