KR102269322B1 - A method and apparatus for fast decoding a linear code based on bit matching - Google Patents

Abstract

A method and apparatus for high-speed decoding of a linear code based on bit matching are disclosed. A method of high-speed decoding of a linear code based on bit matching includes obtaining a hard decision signal by making a hard decision on a received signal, extracting a message signal from the obtained hard decision signal, the extracted message signal and the current obtaining a corrected codeword candidate based on an error vector according to an order, calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal, and setting the calculated Hamming distance as a bit matching-based threshold The method may include comparing the value with the value and determining the error correction candidate word as a corrected codeword according to the comparison result.

Description

A method and apparatus for fast decoding a linear code based on bit matching {A METHOD AND APPARATUS FOR FAST DECODING A LINEAR CODE BASED ON BIT MATCHING}

The present invention relates to a method and apparatus for high-speed decoding of a linear code based on bit matching, and more particularly, to a technique for quickly determining an error-correcting codeword through simple bit matching when the SNR of a received signal is high. .

In digital communication, the decision means a threshold decision according to quantization in the demodulator immediately before the decoder. In this case, the decision method includes a hard decision and a soft decision.

The hard decision means that the waveform output by the demodulator is demodulated only with a binary signal (eg, 0 or 1) and then decoded. On the other hand, soft decision means that the output of a demodulator is demodulated into two or more quantized signals and then decoded instead of performing a firm integer decision like hard decision.

Hard decisions can cause irreversible loss of information at the receiver, but require less data processing and are simple to implement. On the other hand, the soft decision requires more data processing and is complex to implement, but is widely used because it has better decoding performance than the hard decision.

Meanwhile, the process of decoding the soft-determined signal into the original signal is performed through a combination of information such as conditional probability or likelihood of the soft-determined signal. An ordered statistics decoder (OSD), which is one of such soft decision-based decoding methods, has received a lot of attention because it exhibits a performance that is close to a maximum likelihood (ML).

However, since the OSD is similar to the method of finding the codeword most similar to received data among all codewords, the computational complexity due to the process of examining all combinations is very high. For example, the amount of computation required for a Gaussian cancellation operation that is generally performed in a process of decoding a received signal is very high.

Accordingly, there is a need for a method capable of maintaining high decoding performance while lowering computational complexity.

An object of the present invention for solving the above problems is to provide a method for high-speed decoding of a linear code based on bit matching.

Another object of the present invention to solve the above problems is to provide an apparatus for high-speed decoding of a linear code based on bit matching.

Another object of the present invention to solve the above problems is to provide a method of performing Gaussian elimination at high speed in a decoding method of a linear code.

Another object of the present invention to solve the above problems is to provide an apparatus for performing Gaussian elimination at high speed in a method of decoding a linear code.

One aspect of the present invention for achieving the above object provides a method for high-speed decoding of a linear code based on bit matching.

A method of high-speed decoding of a linear code based on bit matching includes obtaining a hard decision signal by making a hard decision on a received signal, extracting a message signal from the obtained hard decision signal, the extracted message signal and the current obtaining a corrected codeword candidate based on an error vector according to an order, calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal, and setting the calculated Hamming distance as a bit matching-based threshold The method may include comparing the value with the value and determining the error correction candidate word as a corrected codeword according to the comparison result.

The error vector may be defined as a vector having the same length as the message signal and having a hamming weight of the current order.

The obtaining of the error correction candidate word may include obtaining the error correction candidate word by multiplying a value obtained by adding the message signal and the error vector by a generation matrix.

The extracting of the message signal may include extracting the message signal by extracting the number of component values corresponding to the rank of the generation matrix from the hard decision signal.

After the comparing, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of increasing the current order and obtaining the error correction candidate word may be performed again.

After the comparing, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of obtaining the error correction candidate word by changing the generation matrix may be performed again.

The determining of the error correction candidate word as the error correction codeword may include determining the error correction candidate word as the error correction codeword when the calculated Hamming distance is less than or equal to the bit matching-based threshold value. have.

Another aspect of the present invention for achieving the above object is to provide an apparatus for high-speed decoding of a linear code based on bit matching.

An apparatus for high-speed decoding of a linear code based on bit matching includes at least one processor and a memory for storing instructions instructing the at least one processor to perform at least one step. memory) may be included.

The at least one step may include: obtaining a hard decision signal by hard decision on the received signal; extracting a message signal from the obtained hard decision signal; error correction based on the extracted message signal and an error vector according to the current order obtaining a corrected codeword candidate, calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal, comparing the calculated Hamming distance with a bit matching-based threshold, and according to the comparison result and determining the error correction candidate word as an error correction codeword.

The error vector may be defined as a vector having the same length as the message signal and having a hamming weight of the current order.

The obtaining of the error correction candidate word may include obtaining the error correction candidate word by multiplying a value obtained by adding the message signal and the error vector by a generation matrix.

The extracting of the message signal may include extracting the message signal by extracting the number of component values corresponding to the rank of the generation matrix from the hard decision signal.

After the comparing, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of increasing the current order and obtaining the error correction candidate word may be performed again.

After the comparing, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of obtaining the error correction candidate word by changing the generation matrix may be performed again.

The determining of the error correction candidate word as the error correction codeword may include determining the error correction candidate word as the error correction codeword when the calculated Hamming distance is less than or equal to the bit matching-based threshold value. .

Another aspect of the present invention for achieving the above object provides a method of performing Gaussian elimination at high speed in a method of decoding a linear code.

A method of performing Gaussian elimination at high speed in a decoding method of a linear code includes generating a heat-exchanged generative matrix by performing column exchange on a permuted generative matrix, the front end of the heat-exchanged generative matrix generating a row-exchanged generative matrix by performing row exchange so that the columns located in α form a partial identity matrix, and Gaussian for the remaining columns in the row-exchanged generative matrix except for the columns constituting the partial identity matrix It may include performing erasing.

The generating of the heat-exchanged generating matrix may include, in the permuted generating matrix, columns that are unit vectors among columns corresponding to Most Reliable Bases (MRB) of the received signal, the front end of the heat-exchanged generating matrix. It may include the step of exchanging heat to be located in the.

In the generating of the heat-exchanged generation matrix, at least one column having low reliability among columns corresponding to the MRB of the received signal may be excluded from the heat exchange.

Another aspect of the present invention for achieving the above object is to provide an apparatus for performing Gaussian elimination at high speed in a method of decoding a linear code.

An apparatus for performing Gaussian elimination at high speed in a decoding method of a linear code stores at least one processor and instructions for instructing the at least one processor to perform at least one step It may include a memory (memory).

The at least one step may include generating a heat-exchanged generative matrix by performing column exchange on the substituted generating matrix, and row exchange such that columns located at the front end of the heat-exchanged generating matrix form a partial identity matrix. exchange) to generate a row-exchanged generator matrix, and performing Gaussian cancellation on remaining columns except for columns constituting the identity matrix in the row-exchanged generator matrix.

The generating of the heat-exchanged generating matrix may include, in the permuted generating matrix, columns that are unit vectors among columns corresponding to Most Reliable Bases (MRB) of the received signal, the front end of the heat-exchanged generating matrix. It may include the step of exchanging heat to be located in the.

In the generating of the heat-exchanged generation matrix, at least one column having low reliability among columns corresponding to the MRB of the received signal may be excluded from the heat exchange.

When the method and apparatus for high-speed decoding of a linear code based on bit matching according to the present invention as described above are used, it is possible to reduce the computational complexity while maintaining the decoding performance according to the OSD as much as possible.

In addition, by using the bit matching method of calculating the Hamming distance, there is an advantage in that all procedures such as an alignment process and Gaussian cancellation can be omitted and error correction can be performed at a high speed.

On the other hand, in the case of using the method and apparatus for performing Gaussian elimination at high speed in the decoding method of a linear code according to the present invention, the decoding speed is greatly increased because Gaussian elimination is performed at high speed using the characteristics of the generative matrix. There are advantages to be improved.

1 is an exemplary diagram for explaining the concept of linear encoding according to an embodiment of the present invention.
2 is a flowchart illustrating a decoding method of an ordered statistics decoder (OSD) according to an embodiment of the present invention.
3 is a flowchart illustrating a method of decoding probabilistic necessary conditions (PNC) according to an embodiment of the present invention.
4 is a flowchart illustrating a method of decoding probabilistic sufficient conditions (PSC) according to an embodiment of the present invention.
5 is a flowchart illustrating a method for fast decoding a linear code based on a soft decision according to an embodiment of the present invention.
6A to 6J are graphs in which decoding performance and speed of the proposed methods according to an embodiment of the present invention are analyzed for each order.
7A to 7D are graphs analyzing decoding performance and speed according to method 2 among the proposed methods according to an embodiment of the present invention.
8A to 8H are graphs comparing decoding performance and speed of the proposed methods according to an embodiment of the present invention under different experimental conditions.
9A to 9D are graphs in which decoding performance and speed according to method 2 among the proposed methods according to an embodiment of the present invention are analyzed under different experimental conditions.
10 is a conceptual diagram for explaining a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention.
11 is a flowchart illustrating a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention.
12 is a flowchart of a method of fast decoding a linear code based on bit matching according to an embodiment of the present invention.
13 is a graph illustrating a practical ratio of Gaussian elimination in a method of fast decoding a linear code based on bit matching according to an embodiment of the present invention.
14 is a hardware configuration diagram of an apparatus for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention.

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals have been used for like elements.

Terms such as first, second, A, and B may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It should be understood that this does not preclude the existence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary diagram for explaining the concept of linear encoding according to an embodiment of the present invention.

Block coding may refer to a coding method in which data is bundled in a predetermined block unit and encoding and decoding are performed for each block. Linear encoding may mean a code in which a codeword set forms a linear vector space (or satisfies a linear condition).

Referring to FIG. 1 , a general linear encoding process may be expressed using a generation matrix (G). If a message m to be transmitted is expressed as a 1×k vector, a codeword x expressed as a 1Хn vector can be derived by multiplying the message m by a generation matrix having a size of kХn. Hereinafter, k may mean a dimension (or rank, rank of a generating matrix), and n may mean the length of a codeword.

Here, the generation matrix for generating the codeword may be predetermined according to the type or method of the codeword used. In general, the greater the minimum distance between codewords, the higher the error correction capability is, which is advantageous. Here, the minimum distance may mean the smallest distance among Hamming distances between codewords. Also, the Hamming distance may mean the number of different symbols between two codewords.

In addition, the generation matrix for converting a message into a codeword is not limited to a single one, but may be plural. In this case, all of the plurality of generation matrices may convert a specific message into the same codeword. As the number of generation matrices increases, the possibility of error correction in the current order increases, but the amount of calculation performed using a plurality of generation matrices may increase. Accordingly, the number of generation matrices may be determined differently according to a user input or a codeword method used.

Through the above process, the linearly coded codeword is transmitted from the transmitting side of the wired/wireless communication system to the receiving side, and the receiving side recovers the original waveform through a demodulator, and uses a decoder to detect errors mixed in the recovered waveform. It can detect and recover a valid codeword (or data symbol).

Hereinafter, a method and apparatus for fast decoding a linear code based on soft decision according to an embodiment of the present invention will be described based on these concepts.

In the following, for convenience of explanation, the transmission channel is AWGN (Additive white Gaussian noise) and the modulation method is described on the assumption that BPSK (Binary Phase Shift Keying) is used, but it is interpreted that the channel or the modulation method is limited. should not

2 is a flowchart illustrating a decoding method of an ordered statistics decoder (OSD) according to an embodiment of the present invention.

Referring to FIG. 2 , in the OSD according to an embodiment of the present invention, an alignment signal may be obtained by first arranging signals received from a decoder in order of magnitude ( S100 ). For example, let r = (r ₀ , r ₁ , ..., r _n-1 ) be the received signal (where n may be the length of the codeword), then the individual components of the received signal (r ₀ , r ₁ , ..., r _n-1 ) are taken absolute values and sorted in the order of magnitude of the absolute values to obtain the sort signal y = (y ₀ , y ₁ , ..., y _n-1 ) (the alignment signal may be referred to as y hereinafter). Here, the sort order may be sorted in descending order, but is not limited thereto, and the sort order is not necessarily arranged in an exact size order.

After step S100, a hard decision signal may be obtained by hard decision on the alignment signal y (S110). For example, a hard decision signal Y = (Y ₀ , Y ₁ , ..., Y _n-1 ) may be obtained by making a hard decision on the alignment signal y (hereafter, the hard decision signal may be referred to as Y ). ). When the hard decision signal Y is obtained, an upper signal corresponding to Most Reliable Bases (MRB) may be obtained from the hard decision signal (S120, hereinafter, the upper signal may be referred to as α). Specifically, in the hard decision signal, the upper k components (where k may be the dimension described in FIG. 1 ) having a large magnitude are divided into MRBs and the remaining nk components are classified as LRBs, and the upper signal having k components ( α) can be obtained.

After step S120, a substituted error correction candidate word may be obtained using an error vector according to the upper signal α and an order (hereinafter, denoted as o) (S130). Specifically, for example, if the error vector for an arbitrary order o is k _o and the permuted generation matrix is G', the error correction candidate word Eo substituted for the arbitrary order o is expressed in Equation 1 below. can be defined as

Referring to Equation 1, the permuted error correction candidate word E _o may be obtained by multiplying the upper signal α and the error vector k _{o according to the order by the permuted generation matrix G′.} In a more detailed expression, a permuted error correction candidate word (E _o ) is obtained by multiplying a value obtained by adding an upper signal (α) and an error vector (k _o ) according to an order with a permuted generative matrix (G′), or It can be obtained as a sum of a value obtained by multiplying a signal α by a permuted generation matrix G′ and a value obtained by multiplying an error vector k _{o by a permuted generation matrix G′.} At this time, the permuted generating matrix is obtained by substituting the columns of the generating matrix G described in FIG. 1 in the same order as the sorting order that generated the preceding sorting signal y, and performing Gaussian elimination can be Here, the method according to FIG. 10, which will be described later, may be applied to the process of performing Gaussian cancellation.

In addition, the substituted error correction candidate has a substituted order according to the substitution order of the substituted generation matrix, and may be defined as a candidate of an error-corrected codeword. In this case, the permuted generation matrix G' may have a standard form as shown in Equation 2 below.

Referring to Equation 2, I may be an identity matrix having a size of k × k, and P may be a matrix having a size of k × (n-k). Here, if the form is not the same as in Equation 2, the form according to Equation 2 may be derived by appropriately substituting the column of the generating matrix G according to FIG. 1, and in this case, to derive the substituted generating matrix G' The order of the substitution order and the order of the sorting signal may be the same.

On the other hand, the error vector is interpreted as a vector indicating a component predicted to have an error (or a vector indicating a component in which the substituted error correction candidate word and the hard decision signal are predicted to be different from each other among components corresponding to the MRB of the alignment signal) Specifically, the error vector may be defined as a vector having the same length (length of k) as the MRB and having a Hamming weight (the number of non-zero components in the codeword) of the current order (o). For example, in the case of order 0, the error vector k ₀ has a Hamming weight of 0, so it can be derived as in Equation 3 below.

That is, the error vector according to the case where the degree is 0 may be a vector in which k components are all 0. Also, the error vector for the case of order 1 may be derived as in Equation 4 below.

In Equation 4, a position of a component having a value of 1 (or a position of a component predicted to have an error) may vary. That is, a total of k _{k 1} may be derived according to the selected location. In addition, the error vector (k ₂ ) for the case of order 2 is derived by selecting two positions from among the MRBs, having only a component value of 1 (or a value other than 0) for the selected position, and setting the remaining component values as 0. can be

A permuted error correction candidate word is a candidate that is likely to become a permuted and corrected codeword like a permuted generation matrix, and may be evaluated through a cost function according to an error vector. For example, as shown in Equation 4, the error vector is a vector having 1 in the j-th component (that is, it is predicted that the error correction candidate word substituted in the j-th component among the components corresponding to the MRB of the alignment signal is different from the hard decision signal) ), the cost function can be defined as in Equation 5 below.

Referring to Equation 5 above, the cost function is the size of the j-th component in the alignment signal y, and the substituted error correction candidate word E _i and the hard decision signal (E i ) among the components corresponding to the remaining nk LRBs. Y _i ) may be defined as a value obtained by adding the sizes of components corresponding to positions having different values. Also, as in Equation 3, the cost function for an error vector in which all components are 0 has no component indicated by the error vector, so it can be defined as in Equation 6 below.

Specifically, referring to Equation 6, according to Equation 3, a cost function for an error vector having a degree of 0 has a value in which a substituted error correction candidate word and a hard decision signal have different values among components corresponding to nk LRBs. It may be defined as a value obtained by adding the sizes of components corresponding to positions.

In the same way as in Equations 5 and 6, if the non-zero component indicated by the error vector of order 2 is the l-th component and the m-th component, the cost function can be defined as in Equation 7 below .

That is, by summarizing Equations 5 to 7, the cost function can be defined as an operation of adding the sizes of components corresponding to positions where the substituted error correction candidate word and the hard decision signal have different values in the alignment signal.

Therefore, after step S130, the cost for the current order may be calculated using the cost function (S140). Here, the current order may be a variable that starts from 0 and increases by one every time step S130 is passed.

When the cost for the current order is calculated in step S140, the permuted error correction candidate word may be determined as a permuted and corrected codeword according to the result of comparing the calculated cost with the minimum cost (S150) . Here, the minimum cost may mean a minimum value among costs calculated from the order 0 to the current order. To describe step S150 in more detail, if the calculated cost is less than the minimum cost, the substituted error correction candidate word may be determined as the substituted error correction codeword. Also, if the cost calculated in step S150 is smaller than the minimum cost, updating the calculated cost to the minimum cost may be included. Meanwhile, when the degree is 0, the cost calculated in step S140 may be determined as the minimum cost, and the substituted error correction candidate word may be determined as the substituted error correction codeword.

After step S150, it is determined whether there is a changeable error vector in the current order (S160), and if there is a changeable error vector in the current order, the error vector is changed (S180) and the process according to step S130 can be performed again. . Here, the change of the error vector may be performed by changing the position of a non-zero component (or a 1 component) in the error vector.

After step S160, it is determined whether the current order has reached a preset maximum order (S170), and if the maximum order has been reached, the encoding process may be terminated. However, if the maximum order is not reached, the current order may be increased by one (S190), and the process may be performed again from step S130. Here, the maximum order is a value that can be input by a user, and can generally be derived by the following Equation (8).

In Equation 8, d may mean a minimum distance of a codeword, and k may mean a dimension.

3 is a flowchart illustrating a method of decoding probabilistic necessary conditions (PNC) according to an embodiment of the present invention.

Since the OSD described in FIG. 2 continuously calculates the cost function up to a preset maximum order and derives a substituted error correction candidate word, there is a problem in that computational complexity is high and unnecessary operations are repeatedly performed.

In order to reduce the computational complexity, a method of speeding up decoding by omitting an operation for a subsequent order even if the maximum order is not reached may be considered. In this case, probabilistic necessary conditions (PNC) is a method of determining an error correction codeword only from the results investigated so far if there is no possibility that a cost lower than the minimum cost exists even if the order is increased.

Referring to FIG. 3 , the PNC may first perform the determination according to step S165 instead of performing up to step S160 according to FIG. 2 and determining whether the maximum order has been reached ( S170 ). That is, in step S165, the sum of components with small magnitudes (which may be referred to as a speeding threshold hereinafter) among the components of the alignment signal corresponding to the MRB may be compared with the minimum cost determined up to the current order (S165). Here, since the number of components corresponding to the cost function calculation for the next order of the current order should be considered, the number of components having a small size may be selected by one more than the current order and added to each other.

For example, if the current order is o, the speedup threshold S _PNC for determining whether to perform the operation on the next order o+1 may be defined as in Equation 9 below.

Referring to Equation 9, assuming that the sorting signal is sorted in descending order, the acceleration threshold value (S) by adding o+1 components backwards from the k-1th component, which is the last component, among the components corresponding to the MRB of the alignment signal. _PNC ) can be determined. On the other hand, if the sort signals are sorted in ascending order, j=0 to j=o can be added.

As a result of the comparison in step S165, if the sum of the small components is greater than the minimum cost, subsequent orders have no choice but to be greater than the minimum cost according to the current order, so there is little or no possibility of becoming an error correction codeword. Therefore, as a result of the comparison in step S165, if the sum of the components having small sizes is greater than the minimum cost, the process of repeating calculations (S130 to S150) by increasing the order (S190) may be omitted, and decoding may be terminated.

4 is a flowchart illustrating a method of decoding probabilistic sufficient conditions (PSC) according to an embodiment of the present invention.

According to an embodiment of the present invention, it is possible to provide another embodiment (PSC, probabilistic sufficient conditions) in which the amount of computation is reduced by improving the OSD shown in FIG. 2 .

Referring to FIG. 4 , after performing step S130 according to FIG. 2 , the PSC may perform the process according to step S135 instead of step S140 . That is, in step S135, the Hamming distance between the hard decision signal Y and the substituted error correction candidate word E _o according to the current order o is compared with a preset first threshold value (S135), and according to the comparison result, An error correction candidate may be obtained (S130) by omitting the operations (S140 to S150) on the current error vector and changing the error vector of the current order (S180).

Specifically, if the Hamming distance between the hard decision signal and the substituted error correction codeword is greater than (or greater than or equal to) a preset first threshold value, the substituted error correction code is unlikely to become an actual error correction codeword. Operations on the current error vector may be omitted and other candidate words of the current order may be calculated.

5 is a flowchart illustrating a method for fast decoding a linear code based on a soft decision according to an embodiment of the present invention.

Referring to FIG. 5 , a method for fast decoding a linear code based on soft decision includes obtaining an alignment signal by arranging a received signal in an order of magnitude (S200), and hard decision on the alignment signal to obtain an alignment signal. Acquiring a decision signal (S210), obtaining a higher-order signal corresponding to most reliable bases (MRB) from the hard decision signal (S220), an error substituted using the higher-order signal and an error vector according to the current order Obtaining a permuted and corrected codeword candidate (S230), calculating the cost for the current order using a cost function (S240), and comparing the calculated cost with the minimum cost. The method may include determining the permuted error correction candidate word as a permuted and corrected codeword ( S250 ) and determining a predefined acceleration condition ( S260 ).

The step of obtaining the error correction candidate word ( S230 ) may include obtaining a permuted error correction candidate word by multiplying the upper signal and the error vector according to the current order by a permuted generation matrix. For example, the substituted error correction candidate word may be obtained according to Equation 1 above. In addition, the permuted generating matrix is obtained by substituting the columns of the generating matrix G described in FIG. 1 in the same order as the sorting order that generated the preceding sorting signal y, and performing Gaussian elimination can be

Here, the method according to FIG. 10, which will be described later, may be applied to the process of performing Gaussian cancellation.

The cost function may be defined as an operation of adding the sizes of components corresponding to positions at which the substituted error correction candidate word and the hard decision signal have different values in the alignment signal. For example, the cost function may refer to Equations 5 to 7.

The error vector may be defined as a vector having the same length as the MRB and having a hamming weight of the current order. For example, the error vector may refer to Equations 3 to 4.

The step of determining the predefined speeding condition (S260) includes calculating a speedup threshold by adding components having a small size among the components of the alignment signal corresponding to the MRB, and combining the calculated speedup threshold with the minimum cost. Comparing may be included. For example, the step of determining the predefined speeding condition ( S260 ) may refer to the description according to FIG. 3 , and the speedup threshold may refer to Equation (9).

After the comparing, only when the speedup threshold is smaller than the minimum cost as a result of the comparison, obtaining the substituted error correction candidate word for the next order of the current order may be performed.

After obtaining the substituted error correction candidate word (S230), the method may include comparing a Hamming distance between the hard decision signal and the substituted error correction candidate word with a preset first threshold value. For example, the step of comparing the Hamming distance with a preset first threshold may refer to the description of FIG. 4 .

After the step of comparing the Hamming distance with a preset first threshold value, if the comparison result shows that the Hamming distance is greater than the preset first threshold value, the operation on the error vector is omitted, and the error vector according to the current order may be changed to obtain the substituted error correction candidate word. In more detail, reference may be made to the description according to FIG. 4 .

On the other hand, when it is determined to perform step S130 for the next order o+1 as a result of determining step S165 as a predefined speeding condition for the current order o by applying the PNC according to FIG. 3, step S140 in the order o+1 The cost calculated in can be expressed as in Equation 10 below.

Referring to Equation 10, the front end is an operation for adding the magnitudes of o+1 components indicated by the error vector in the alignment signal y according to the MRB, and may correspond to the front end in Equations 5 to 7 can In addition, the rear end in Equation 10 is a partial sum for reliability of symbols corresponding to the LRB, and may correspond to the rear end in Equations 5 to 7.

In general, since LRBs are low reliability values, an error probability is higher than that of components corresponding to MRB. Accordingly, γ in Equation 10 can be expected to have a value greater than 0. Using this point, the acceleration threshold defined in Equation 9 (threshold value for determining whether to omit the operation for the next order o+1) can be changed as shown in Equation 11 below.

Referring to Equation 11, the newly defined speeding threshold (S _proposed ) is the speeding threshold (S _PNC ) defined in Equation (9) with a signal to noise ratio (SNR), an order, and an error correction code (code) as factors. It can be defined as the added value of the function (f) with

Accordingly, the calculating of the speedup threshold includes calculating the speedup threshold by adding a function having a signal to noise ratio (SNR), an order, and an error correction code as factors to the sum of the components with small magnitudes. You may.

Meanwhile, the acceleration threshold defined in Equation 9 (threshold value for determining whether to omit the operation for the next order o+1) may be changed as shown in Equation 12 below.

Referring to Equation 12, the newly defined acceleration threshold (S _proposed ) is a function (f') having a received vector (represented as a received vector) as a factor in the _{acceleration threshold (S PNC} ) defined in Equation 9. It can also be defined as an added value.

Here, the received vector may be a vector obtained by permuting a column vector of a received signal or a column vector of a received signal in the same order as the permuted generation matrix G'.

Here, the function f' having the received vector as a factor is the component of vectors corresponding to the parity of the received vector (the matrix P included in the permuted generation matrix G' according to Equation 2 and the components of the vectors to be operated on) ) or an operation of adding all components corresponding to the LRB of the reception vector or adding all components of the reception vectors, and may further include an operation of multiplying the addition operation by a proportional constant.

Accordingly, the calculating of the speedup threshold may include calculating the speedup threshold by adding a function having a reception vector as a factor to the sum of the components having small magnitudes.

Meanwhile, by replacing or adding the step of comparing the Hamming distance with a preset first threshold value, a preset second threshold value may be used. Specifically, after the step of obtaining the substituted error correction candidate word (S230) (or after the step of comparing with the preset first threshold value), between the hard decision signal and the substituted error correction candidate word Comparing the Hamming distance with a preset second threshold value and, if the Hamming distance is smaller than the second threshold value, omitting the step of calculating the cost and immediately applying the substituted error correction candidate word to the substituted error correction The method may further include determining a codeword. That is, if the Hamming distance is smaller than the second threshold value, all subsequent processes including the step of calculating the cost are omitted, and the substituted error correction candidate word is immediately determined as the substituted error correction coded word and the decoding procedure can be terminated. .

The method of fast decoding a linear code based on the soft decision according to FIG. 5 may be referred to as Fast and Scalable Soft Decision decoding methods for linear codes (FSSD) hereinafter.

6A to 6J are graphs in which decoding performance and speed of the proposed methods according to an embodiment of the present invention are analyzed for each order.

In the graphs below, HDD means general hard decision decoding, PNC means a case where step S165 according to FIG. 3 is applied, and PSC means step S135 according to FIG. 4 is additionally applied to PNC. means the case. In addition, proposed 1 (method 1) applies a process of determining a speeding condition using a newly defined speeding threshold according to Equation 11 in the flowchart according to FIG. 5, and comparing the second threshold with the Hamming distance to cost It may mean a method in which the calculation step is omitted.

In addition, proposed2 (method 2) refers to a method in which operation on the current error vector is omitted by applying step S135 according to FIG. 4 in addition to method 1 together.

For the coded words used in FIGS. 6A to 6J, a Bose-Chaudhuri-Hocquenghem (BCH) code having a code length n of 127, a dimension k of 64, and a minimum distance d of 21 was used. In addition, considering that the minimum distance (d) of the HDD is 21 points, all errors less than 10 are fixed. Also, in the graph, the vertical axis indicates a code error rate (WER) or a decoding speed (Speed-up) indicating decoding performance. Also, in the graph, the horizontal axis represents SNR (Signal-to-Noise Ratio). In this case, the decoding speed is a relative indication of how fast it is compared to the full ssearch algorithm of the OSD described with reference to FIG. 2 . In each experiment, all data was quantized to 7 bits, and the first threshold value preset according to the PSC of FIG. 4 was set to 25, and the second threshold value according to the description of FIG. 5 was set to 10. In addition, in method 1 (proposed 1) and method 2 (proposed 2), the function (f) value having SNR (Signal to Noise Ratio), order, and error correction code as factors is 346.5, 346.5, 321.3, 346.5, 346.5, 321.3, 270.9 and 270.9 were used.

Referring to FIGS. 6A to 6J , a result of comparing decoding performance and speed for orders 1 to 5 can be confirmed. As can be seen from the graph, Methods 1 and 2 are almost identical to PNC and PSC in decoding performance. In addition, the decoding speed of Methods 1 and 2 is significantly faster than that of PNC and PSC. In the case of Method 1, although there is a section in which the decoding speed is slower than that of PSC at low SNR, it can be seen that the decoding speed of Method 2 rapidly converges as the SNR increases. It can be seen that method 2 exhibits a significantly faster decoding speed than all other methods.

Specifically, Method 1 and Method 2 are about 13770 times faster (Method 1) and 14609 times (Method 2) faster than OSD-FS for each order, and up to about 336 times faster than PNC (Method 1) , and 797 times faster (Method 2). And compared to PSC, it is up to about 61 times faster (Method 1) and 139 times faster (Method 2).

7A to 7D are graphs analyzing decoding performance and speed according to method 2 among the proposed methods according to an embodiment of the present invention.

The experimental conditions in FIGS. 7A to 7B are the same as those of FIGS. 6A to 6J .

Referring to FIGS. 7A to 7B , the decoding performance and speed of Method 2 according to each order can be confirmed. Here, the decoding speed (Relative Speed) shown in FIG. 7B represents a relative speed compared to the OSD-FS (full search) of order 1. Specifically, method 2 converges to the speed of the OSD-FS according to order 1 irrespective of the order as the SNR increases. That is, when the SNR is higher than a certain level, the higher the order, the better the decoding performance and the lower the computational complexity.

7c to 7d, when the signal to noise ratio (SNR), the order, and the function value (represented by β in the graph) having the error correction code as factors in method 2 (proposed 2) are changed, You can check the decryption performance and speed. In this case, the decoding speed represents a relative speed compared to the OSD-FS in order 4. From the viewpoint of decoding performance, the same performance is exhibited before the β value exceeds a specific value, and as the β value increases, the decoding performance gradually deteriorates. The decoding speed exhibits a characteristic that becomes faster as the value of β increases. That is, a fine trade-off relationship between the decoding performance and the decoding speed is established according to the β value, so that the user can change the parameters to suit the system environment.

8A to 8H are graphs comparing decoding performance and speed of the proposed methods according to an embodiment of the present invention under different experimental conditions.

8A to 8H, a BCH code having a length of 255, a dimension of 131, and a minimum distance of 37 is used for the codeword. In addition, since the minimum distance of the HDD is 37, all errors less than 18 are set to be fixed. In this case, the decoding speed is a relative indication of how fast it is compared to the full ssearch algorithm (OSD-FS) of the OSD described in FIG. 2 . In each experiment, all data was quantized to 7 bits, and the first threshold value preset according to the PSC of FIG. 4 was set to 46, and the second threshold value according to the description of FIG. 5 was set to 18. In addition, in method 1 (proposed 1) and method 2 (proposed 2), the function (f) value with SNR (Signal to Noise Ratio), order, and error correction code as factors is 706.8, 706.8, 706.8, 706.8, 706.8, 706.8, respectively, from orders 1 to 7 706.8, 706.8, 644.8, 620.0 were set.

The decoding performance of the codewords used in FIGS. 6A to 6J is no longer improved even if the order exceeds 5, but the decoding performance of the codewords used in FIGS. 8A to 8H is significantly improved when the order is increased to 7. However, in the case of PSC or PNC, since it takes an enormous amount of time even in order 5, the performances up to order 4 are compared in FIGS. 8A to 8H.

Referring to FIGS. 8A to 8H , Methods 1 and 2 show almost the same performance as PNC and PSC in decoding performance. In contrast, the decoding speed of Methods 1 and 2 is up to about 5287 times (Method 1) and 7420 times (Method 2) faster than OSD-FS for each order, and up to about 747 times faster than PNC (Method 1). ), and 1775 times faster (Method 2). And, compared to PSC, it is up to about 101 times faster (Method 1) and 240 times faster (Method 2). In addition, when comparing by increasing the order of 5 or more, methods 1 and 2 can be predicted to be significantly faster than PNC or PSC.

9A to 9D are graphs in which decoding performance and speed according to method 2 among the proposed methods according to an embodiment of the present invention are analyzed under different experimental conditions.

The experimental conditions of FIGS. 9A to 9D are the same as those of FIGS. 8A to 8H.

Referring to FIGS. 9A to 9B , the decoding performance and decoding speed of Method 2 according to each order can be checked. In this case, the decoding speed (Relative Speed) of FIG. 9B represents a relative speed compared to the OSD-FS of order 1.

As can be seen from FIG. 9A , it can be seen that the decoding performance of Method 2 significantly increases as the order increases. As in FIGS. 6A to 6J , Method 2 rapidly converges to the OSD-FS speed of order 1 as the SNR increases regardless of the order. That is, when the SNR exceeds a certain level, it can be seen that the computational complexity always maintains a constant level (the lowest level) regardless of the order.

9c to 9d, when the signal to noise ratio (SNR), the order, and the function value (represented by β in the graph) having the error correction code as factors in method 2 (proposed 2) are changed for order 4 You can check the decryption performance and speed. Here, the decoding speed represents a relative speed compared to the OSD-FS in order 4. 7A to 7D , the same decoding performance is exhibited before the β value exceeds a specific value, and the decoding performance gradually deteriorates after the β value exceeds the specific value. In contrast, the decoding speed exhibits a characteristic that the speed increases as the value of β increases. By utilizing these characteristics, the user can change the parameters to suit the system environment.

10 is a conceptual diagram for explaining a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention. 11 is a flowchart illustrating a method of performing Gaussian elimination at high speed in a method of decoding a linear code according to an embodiment of the present invention. As described in FIGS. 1 and 2 , the permuted generating matrix G' is the sorting order (or the received signal of) preceding the column of the generating matrix G described in FIG. 1 for generating the sorting signal y. It can be obtained by substituting in the same order as the reliability magnitude order) and performing Gaussian elimination.

As such, the soft decision-based linear code decoding method is Gaussian cancellation for a matrix (eg, a generation matrix G or a parity check matrix, etc.) having a size of k×n (or n×k if rows and columns are configured in reverse). includes the process of performing In this case, k may mean a dimension (or rank, rank of the generating matrix), and n may mean the length of a codeword.

Here, the generative matrix G has a maximum dimension (full rank), and generally has a systematic shape. The meaning that the code format has systematic characteristics may mean that a message (or information bit stream) having a length of k is included in a codeword having a length of n without modification as it is. Accordingly, in the systematic codeword, the message sequence and the parity sequence may be separated from each other. For example, the message sequence may be positioned before or after the codeword and the parity sequence may be positioned in the remaining columns. In addition, in the systematic code, the generation matrix has an identity matrix having a size of k×k in a portion corresponding to the message column of the systematic codeword, and a parity matrix having a size of k×(nk) in the remaining portion. can have

For example, the generation matrix G according to the systematic codeword may be expressed as Equation 13 below.

In Equation 13, the matrix I _k corresponds to the message column and may be a unit matrix having a size of k×k, and the matrix P may be a parity matrix having a size of k×(nk). Also, u ₀ to u _k-1 may be a unit vector in which the k-th component value is 1 and the remaining component values are 0. In FIG. 11, such a generation matrix G is expressed as an exemplary matrix.

The permuted generation matrix G' used in the decoding method (represented as Previous Method) according to FIGS. 2 to 5 is a column of the generation matrix G expressed as Equation 13 as described in FIG. 2 . ) can be generated by heat exchanging according to the order of the reliability magnitude of the received signal. In this case, columns corresponding to k components having a large degree of reliability in the received signal (which may be components corresponding to the message signal in the received signal and may be referred to as MRBs of the received signal hereinafter) are denoted as MRBs in FIG. 11 . and columns corresponding to the remaining components (which may be referred to as LRBs of a received signal hereinafter) are denoted as LRBs. That is, a specific column in the permuted generation matrix G' may be a unit vector corresponding to the message column in Equation 13, or may be a column (parity vector) belonging to the parity matrix P. Accordingly, since the previous method according to FIGS. 2 to 5 performs Gaussian cancellation on the entire permuted generation matrix G' as it is, it is difficult to utilize the characteristic according to Equation 13.

According to an embodiment of the present invention, a method of performing Gaussian cancellation at high speed by minimizing the amount of calculation required for Gaussian cancellation by using the characteristics of the generation matrix expressed as Equation 13 can be proposed.

Referring to FIG. 11 , the high-speed Gaussian cancellation method according to an embodiment of the present invention generates a heat-exchanged generative matrix Gc by performing column exchange on a permuted generating matrix G'. (S300), generating a row-exchanged generative matrix by performing row exchange so that the columns located at the front end of the column-exchanged generating matrix form a partial identity matrix (S310) and in the row-exchanged generating matrix The method may include performing Gaussian cancellation on the remaining columns except for the columns constituting the partial identity matrix ( S320 ).

Here, the permuted generation matrix G' may be generated by column exchanging each column of the generation matrix according to the order of the reliability magnitude of the received signal.

Here, the step (S300) of generating the heat exchanged matrix Gc includes, among the columns corresponding to the Most Reliable Bases (MRB) of the received signal in the permuted generation matrix G', the columns that are the unit vectors. , it may include the step of exchanging heat so as to be located at the front end of the heat-exchanged generating matrix (Gc). For example, referring to FIG. 10 , among the columns indicated by MRB of the substituted generating matrix G', columns corresponding to the unit vector are heat-exchanged so that they are located at the front end of the heat-exchanged generating matrix Gc. can be checked

Therefore, according to an embodiment of the present invention, Gaussian cancellation is performed at high speed by performing Gaussian cancellation on only the remaining columns except for the columns constituting the partial identity matrix in the _{row-exchanged matrix (G r ).} can do. Referring to FIG. 10 , the partial identity matrix may be a matrix partially having the form of the identity matrix (E).

As a result, since Gaussian elimination is performed only on the remaining parts except for the partial identity matrix, in the Gaussian elimination process, the leading non-zero coefficient of each row is set as the pivot, and elimination for other rows is performed based on the determined pivot. Since the process of performing (forward elimination) and back-substitution can be omitted to a large extent, Gaussian elimination can be performed quickly.

On the other hand, among the columns corresponding to the MRB of the received signal in the permuted generation matrix G', m columns having low reliability have a high probability of error, so it may be desirable to be subjected to Gaussian cancellation. Here, the variable m may be determined differently according to a user's setting.

That is, in generating the heat-exchanged generation matrix ( S300 ), at least one column having low reliability among columns corresponding to the MRB of the received signal may be excluded from the heat exchange. When the method of performing Gaussian elimination at high speed described above is applied to the method and apparatus for decoding a linear code, the experimental effects are shown in Table 1 below.

In Table 1, the speed is the speed implemented using C language in the i7-4790K PC, the existing speed is the speed to which Gaussian cancellation in the decoding method according to FIGS. 2 to 5 is applied, and the proposed speed is according to FIG. It may be a speed when fast Gaussian cancellation is applied to the decoding method according to FIGS. 2 to 5 . In addition, in the fast Gaussian elimination in Table 1, the variable m (the number of columns with low reliability) is set to 5. As can be seen in Table 1, a method of performing Gaussian elimination at high speed according to an embodiment of the present invention is described. When applied to the decoding method according to FIGS. 1 to 5 , there is a speed improvement effect of at least 30% to 50% or more.

12 is a flowchart of a method of fast decoding a linear code based on bit matching according to an embodiment of the present invention.

A case in which the operation speed is the fastest in the decoding method according to FIGS. 2 to 5 may be a case in which an error correction codeword is determined immediately when the current degree is 0 and the decoding procedure is terminated. The ability to immediately determine the error correction codeword when the current order is 0 may mean a case in which the signal-to-noise ratio (SNR) of the received signal is very large, so that the number of bits in which an error occurs is very small.

As such, even if it is assumed that the operation speed is the fastest in the decoding method according to FIGS. 2 to 5 , at least the process of arranging the received signals in the order of the reliability magnitude, the process of substituting the generation matrix G according to the sorted order, the Gaussian It is necessary to perform a process of generating a permuted generation matrix G' through cancellation and a process of determining an error correction codeword through cost calculation for the current order 0.

The amount of computation occupied by Gaussian elimination out of the minimum required computation process exceeds about 40%. An embodiment of the present invention proposes a method of quickly determining an error correction codeword using bit matching without an operation process such as Gaussian cancellation when the SNR of the received signal is very large and the occurrence of an error is small.

Referring to FIG. 12 , the method for fast decoding a linear code based on bit matching according to an embodiment of the present invention includes the steps of hard decision making by hard decision on a received signal (S400), the obtained hard decision signal Extracting a message signal from the hard decision signal (S410), obtaining an error correction candidate word based on the extracted message signal and an error vector according to the current order (S420), the obtained error correction candidate word and the hard decision signal Calculating a Hamming distance between them (S430), comparing the calculated Hamming distance with a bit matching-based threshold value (S440), and determining the error correction candidate word as an error correction codeword according to the comparison result (S450) may include.

A method of high-speed decoding of a linear code based on bit matching will be sequentially described again. In this method, a hard decision signal can be obtained by first hard-determining a signal received from a decoder ( S400 ). For example, when r = (r ₀ , r ₁ , …, r _n-1 ) is a received signal (where n may be the length of the codeword), the hard decision signal is R = (R ₀ , R ₁ , ..., R _n-1 ) may be.

Next, a message signal may be extracted from the obtained hard decision signal (S410). Here, the message signal may be extracted by extracting component values as many as the number corresponding to the rank (variable k) of the generation matrix from the hard decision signal. More specifically, the message signal may be extracted by extracting k component values of preset positions from the hard decision signal. Here, the preset position may vary according to a method of generating a message as a codeword using a generation matrix, as shown in FIG. 1 . For example, when the generation matrix is in the form according to Equation 13, _{received signal components at positions corresponding to the unit matrix (I k} ) become message signals, so the hard decision signal R = (R ₀ , R ₁ , ..., In R _n-1 ), the leading k component values are the message signal R _m = (R ₀ , R ₁ , R ₂ , …,R _k-1 ) = (m ₀ , m ₁ , m ₂ , m _{k- 1} ) can be

Next, an error correction candidate word may be obtained based on the extracted message signal and the error vector according to the current order ( S420 ). Here, the error vector may be defined as a vector having the same length as the message signal and having a hamming weight of the current order. For example, if the current degree is 0 (for the first trial), the error vector may be a vector of length k with all components 0. For other error vectors, reference may be made to the description of Equations 3 and 4 of FIG. 2 .

In the step of obtaining the error correction candidate word ( S420 ), the error correction candidate word may be obtained by multiplying a value obtained by adding the message signal and the error vector by a generation matrix. For example, the error correction candidate word may be obtained according to Equation 14 below.

In Equation 14, when the current order is o, E _o may be an error correction candidate word, Rm may be a message signal, G may be a generation matrix, and k _o may be an error vector. In the step of obtaining the error correction candidate word, when the current order is 0 (the first trial), all components of the error vector are 0, so error correction is performed by multiplying the message signal and the generation matrix without adding the error vector to the message signal. It may be interpreted that the candidate word is obtained.

After step S420, a Hamming distance between the obtained error correction candidate word and the hard decision signal may be calculated (S430), and the calculated Hamming distance may be compared with a bit matching-based threshold value (S440). Here, the error correction candidate word may be directly determined as the error correction codeword according to the comparison result ( S450 ). For example, if the calculated Hamming distance is less than or equal to the bit matching-based threshold value, it is considered that almost no error has occurred in the received signal, and the error correction candidate word may be directly determined as the error correction codeword. Here, the bit matching-based threshold may be determined differently according to a user's setting.

Meanwhile, if the calculated Hamming distance is greater than the bit matching-based threshold value, the current order may be increased (S445a) and the step of obtaining the error correction candidate word (S420) may be re-performed. When the step of obtaining the error correction candidate word is re-performed, the error correction candidate word may be obtained by using an error vector in which the Hamming weight is increased by one as the current order increases by one.

Also, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of obtaining the error correction candidate word ( S420 ) may be re-performed by changing the generation matrix ( S445b ) instead of increasing the current order. For example, when there are a plurality of generation matrices generating the same codeword for a specific message, error correction may be performed by obtaining an error correction candidate word using a different generation matrix. When the error correction codeword is not determined up to the maximum order (o' _max ), one method of FIGS. 2 to 5 is performed, and processes such as sorting, obtaining a permuted generation matrix through Gaussian elimination, and calculating the cost are performed. can Here, the maximum order (o' _max ) may be determined according to a user's setting.

As such, in the present invention, by using the bit matching method of calculating the Hamming distance between the error correction candidate word and the hard decision signal, all procedures such as signal alignment and Gaussian cancellation are omitted and error correction can be performed at a high speed. have.

13 is a graph illustrating a practical ratio of Gaussian elimination in a method of fast decoding a linear code based on bit matching according to an embodiment of the present invention.

In FIG. 13 , the vertical axis represents the ratio of the time used for the Gaussian erasure operation when the FSSD of FIG. 5 is performed versus the time used for the Gaussian erasure operation when the method of fast decoding the bit-matching-based linear code according to FIG. 12 is applied. is shown.

Also, for the coded word, a Bose-Chaudhuri-Hocquenghem (BCH) code having a code length (n) of 127, a dimension (k) of 64, and a minimum distance (d) of 21 was used. In addition, in the FSSD according to FIG. 5, the first threshold value is 25, the order (o) is 5, and the second threshold value is 10, and the bit matching-based threshold value used in the method according to FIG. 12 is 10, the order ( o) is 2 used.

When the error correction codeword is determined according to the method of FIG. 12 , since the Gaussian cancellation operation is omitted, the degree to which the Gaussian cancellation operation is omitted can be understood by referring to the graph of FIG. 13 .

For example, when the SNR is 3.0, the ratio occupied by the Gaussian cancellation operation in the graph of FIG. 13 is 88.6% (or 0.886). That is, in the case of the existing algorithm (FSSD, FIG. 5), the time consumed for the Gaussian cancellation operation is 15.20 μs, and the method according to FIG. 12 performs one Gaussian cancellation for 13.46 μs, which is 88.6% of the previously consumed time can be interpreted. Therefore, it means that many of various operations including Gaussian cancellation are omitted.

In addition, when the SNR is 5.5, the ratio occupied by the Gaussian cancellation operation in the graph according to FIG. 13 is 28.9% (or 0.289). That is, when the method according to FIG. 12 is used, it means that one Gaussian cancellation is performed on average for 4.40 μs, which is 28.9% of the Gaussian elimination operation time according to the existing algorithm (FSSD, FIG. 5 ).

In addition, as can be seen from the Gaussian cancellation ratio according to the SNR in FIG. 13 , the method according to FIG. 12 omits various operations including Gaussian cancellation as the SNR increases, and it can be seen that the speed is gradually improved. Accordingly, the method according to FIG. 12 does not significantly improve performance when the SNR is low, but has an advantage that the operation speed can be greatly improved when the SNR is large.

14 is a hardware configuration diagram of an apparatus for high-speed decoding of a linear code based on bit matching according to an embodiment of the present invention.

Referring to FIG. 14 , in the apparatus 100 for high-speed decoding of a linear code based on bit matching, at least one processor 110 and the at least one processor 110 perform at least one step. It may include a memory 120 for storing instructions instructing to be performed.

Also, the apparatus 100 for high-speed decoding of a linear code based on bit matching may include a transceiver 130 that communicates with a base station through a wired/wireless network. Also, the apparatus 100 for high-speed decoding of a linear code based on bit matching may further include an input interface device 140 , an output interface device 150 , a storage device 160 , and the like. Each component included in the apparatus 100 for high-speed decoding of a linear code based on bit matching may be connected by a bus 170 to communicate with each other.

Here, the processor 110 may mean a central processing unit (CPU), a graphics processing unit (GPU), or a dedicated processor on which methods according to embodiments of the present invention are performed. Each of the memory 120 and the storage device 160 may be configured as at least one of a volatile storage medium and a non-volatile storage medium. For example, the memory 120 may be configured as at least one of a read only memory (ROM) and a random access memory (RAM).

The at least one step may include: obtaining a hard decision signal by hard decision on the received signal; extracting a message signal from the obtained hard decision signal; error correction based on the extracted message signal and an error vector according to the current order obtaining a corrected codeword candidate, calculating a Hamming distance between the obtained error correction candidate word and the hard decision signal, comparing the calculated Hamming distance with a bit matching-based threshold, and according to the comparison result and determining the error correction candidate word as an error correction codeword.

The error vector may be defined as a vector having the same length as the message signal and having a hamming weight of the current order.

The obtaining of the error correction candidate word may include obtaining the error correction candidate word by multiplying a value obtained by adding the message signal and the error vector by a generation matrix.

The extracting of the message signal may include extracting the message signal by extracting the number of component values corresponding to the rank of the generation matrix from the hard decision signal.

After the comparing, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of increasing the current order and obtaining the error correction candidate word may be performed again.

After the comparing, if the calculated Hamming distance is greater than the bit matching-based threshold, the step of obtaining the error correction candidate word by changing the generation matrix may be performed again.

The determining of the error correction candidate word as the error correction codeword may include determining the error correction candidate word as the error correction codeword when the calculated Hamming distance is less than or equal to the bit matching-based threshold value. have.

For example of the apparatus 100 for high-speed decoding of a linear code based on bit matching, a desktop computer, a laptop computer, a notebook computer, which can communicate according to error correction encoding, Smart phone, tablet PC, mobile phone, smart watch, smart glass, e-book reader, PMP (portable multimedia player), portable game machine, Navigation device, digital camera, DMB (digital multimedia broadcasting) player, digital audio recorder, digital audio player, digital video recorder, digital video It may be a digital video player, a personal digital assistant (PDA), or the like.

On the other hand, the device having the hardware components according to FIG. 14 may be used as a device for performing the method of performing Gaussian elimination at high speed in the decoding method of the linear code described in FIG. 11 .

For example, an apparatus for performing Gaussian elimination at high speed in a method of decoding a linear code is configured so that at least one processor 110 and the at least one processor 110 perform at least one step. It may include a memory (memory, 120) for storing instructions (instructions) to indicate.

The at least one step may include generating a heat-exchanged product matrix by performing column exchange on the generation matrix, and row exchange such that columns located at the front end of the heat-exchanged product matrix form an identity matrix. ) to generate a row-exchanged generative matrix, and performing Gaussian cancellation on remaining columns except for columns forming the form of the identity matrix in the row-exchanged generating matrix.

The generating of the heat-exchanged generating matrix may include, in the permuted generating matrix, columns that are unit vectors among columns corresponding to Most Reliable Bases (MRB) of the received signal, the front end of the heat-exchanged generating matrix. It may include the step of exchanging heat to be located in the.

In the generating of the heat-exchanged generation matrix, at least one column having low reliability among columns corresponding to the MRB of the received signal may be excluded from the heat exchange.

The methods according to the present invention may be implemented in the form of program instructions that can be executed by various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the computer-readable medium may be specially designed and configured for the present invention, or may be known and available to those skilled in the art of computer software.

Examples of computer-readable media may include hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions may include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as at least one software module to perform the operations of the present invention, and vice versa.

In addition, the above-described method or apparatus may be implemented by combining all or part of its configuration or function, or may be implemented separately.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be done.

Claims (3)

As a method of performing Gaussian elimination at high speed in a decoding method of a linear code,
generating a column-exchanged generative matrix by performing column exchange on the permuted generative matrix;
generating a row-exchanged generative matrix by performing row exchange such that columns located at the front end of the column-exchanged generating matrix form a partial identity matrix; and
and performing Gaussian elimination on the remaining columns except for columns constituting the partial identity matrix in the row-exchanged generative matrix. In claim 1,
The generating of the heat exchanged generative matrix comprises:
In the permuted generation matrix, columns that are unit vectors among columns corresponding to Most Reliable Bases (MRB) of the received signal are heat-exchanged so that they are located at the front end of the heat-exchanged generation matrix. How to perform Gaussian elimination with In claim 2,
The generating of the heat exchanged generative matrix comprises:
A method of performing Gaussian elimination at high speed, in which at least one column having low reliability among columns corresponding to the MRB of the received signal is excluded from the heat exchange.

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