KR102176926B1 - Display Device and Method of manufacturing the same - Google Patents

Abstract

By embedding a sensing electrode for sensing a user's touch inside the display panel, there is no need to configure a separate touch screen on the upper surface of the display panel as in the prior art, so that the thickness is reduced and the manufacturing cost is reduced. The display device includes: a thin film transistor formed in a pixel region defined by a cross arrangement of gate lines and data lines, and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A first passivation layer and a second passivation layer sequentially formed on the thin film transistor and having holes exposing portions of the source electrode and the drain electrode; A pixel electrode patterned on the second passivation layer and connected to the drain electrode exposed through the hole; A sensing line patterned on the second passivation layer; A common electrode connected to the sensing line; A data pad connected to one end of the data line; First and second connection electrodes sequentially patterned on the data pad; And a data pad electrode formed of the same material as the common electrode and connected to the data pad through the first and second connection electrodes.

Description

Display device and method of manufacturing the same

The present invention relates to a display device, and more particularly, to a display device including a sensing electrode for sensing a user's touch.

Until now, various display devices such as a liquid crystal display device, a plasma display panel, and an organic light emitting display device have been developed.

In such a display device, a mouse or keyboard is generally used as an input means, but in the case of navigation, portable terminals and home appliances, a touch screen capable of directly inputting information using a finger or a pen is widely applied. .

Hereinafter, a conventional display device to which a touch screen is applied will be described in detail by taking a liquid crystal display as an example.

1 is a schematic cross-sectional view of a conventional liquid crystal display device.

As can be seen from FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 10 and a touch screen 20.

The liquid crystal panel 10 displays an image, and includes a lower substrate 12, an upper substrate 14, and a liquid crystal layer 16 formed between the substrates 12 and 14.

The touch screen 20 is formed on an upper surface of the liquid crystal panel 10 to sense a user's touch, and includes a touch substrate 22, a first sensing electrode 24 formed on a lower surface of the touch substrate 22, And a second sensing electrode 26 formed on the upper surface of the touch substrate 22.

The first sensing electrodes 24 are arranged in a horizontal direction from a lower surface of the touch substrate 22, and the second sensing electrodes 26 are arranged in a vertical direction from an upper surface of the touch substrate 22. Therefore, when the user touches a predetermined position, the capacitance between the first sensing electrode 24 and the second sensing electrode 26 at the touched position is changed, and eventually, the capacitance is changed by sensing the position. The user's touch position can be sensed.

However, since such a conventional liquid crystal display has a structure in which a separate touch screen 20 is formed on the upper surface of the liquid crystal panel 10, the overall thickness is increased due to the touch screen 20, and the manufacturing cost is also increased. There is a drawback.

The present invention was devised to solve the above-described conventional problem, and by embedding a sensing electrode for sensing a user's touch inside the display panel, there is no need to configure a separate touch screen on the upper surface of the display panel as in the prior art. An object of the present invention is to provide a display device and a method of manufacturing the same.

A display device according to an aspect of the present invention for achieving the above object is formed in a pixel region defined by a cross arrangement of gate lines and data lines, and includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. Thin film transistor; A first passivation layer and a second passivation layer sequentially formed on the thin film transistor and having a first contact hole for exposing the drain electrode; A pixel electrode formed on the second passivation layer and connected to the drain electrode through the first contact hole; A third protective layer formed on the pixel electrode; A first sensing line formed on the third passivation layer; A connection electrode formed of the same material as the pixel electrode between the second passivation layer and the third passivation layer; A second contact hole exposing the connection electrode in the third passivation layer; And a common electrode directly connected to the first sensing line on the first sensing line and connected to the connection electrode exposed through the second contact hole.

A method of manufacturing a display device according to another aspect of the present invention for achieving the above object includes: forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode on a substrate; Sequentially forming a first passivation layer and a second passivation layer on the thin film transistor in which a first contact hole is formed for exposing the drain electrode; Forming a pixel electrode layer on the second passivation layer; Forming a connection electrode by patterning the pixel electrode layer, and forming a pixel electrode connected to the drain electrode through the first contact hole; Sequentially forming a third protective layer and a metal layer for forming a sensing line on the entire surface of the substrate including the pixel electrode and the connection electrode; The third passivation layer and the metal layer are patterned through a patterning process using a halftone mask to form a first sensing line and a second sensing line on the third passivation layer, and form a second contact hole exposing the connection electrode to the third passivation layer. Forming on a protective film; And forming a pattern of a common electrode directly connected to the first sensing line on the first sensing line and connected to the connection electrode exposed through the second contact hole.

According to the present invention as described above has the following effects.

In the present invention, by using the common electrode as a sensing electrode for sensing a user's touch, it is not necessary to configure a separate touch screen on the upper surface of the display panel, thereby reducing the thickness of the display panel.

In addition, the present invention can reduce the number of masks required during the manufacturing process of the display panel, thereby simplifying the manufacturing process and reducing manufacturing cost.

1 is a schematic cross-sectional view of a conventional liquid crystal display device.
2 is a schematic plan view of a substrate for a display device according to an embodiment of the present invention.
3 is a cross-sectional view of a display device according to a first embodiment of the present invention.
4A to 4F are schematic cross-sectional views of a manufacturing process of the display device according to the first embodiment of the present invention.
5 is a cross-sectional view showing an example of a common electrode divided into a plurality of regions.
6 is a cross-sectional view of a display device according to a second embodiment of the present invention.
7A to 7F are schematic cross-sectional views of a manufacturing process of a display device according to a second exemplary embodiment of the present invention.

The term "on" as used herein means including not only a case where a certain structure is formed directly on the upper surface of another structure, but also a case where a third structure is interposed between these elements.

Modifiers such as "first" and "second" described in the present specification do not mean the order of the corresponding components, but are intended to distinguish the corresponding components from each other.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

2 is a schematic plan view of a substrate for a display device according to an embodiment of the present invention. For reference, an enlarged view drawn with an arrow in FIG. 2 is for showing a pixel area in which the sensing line 600 and the common electrode 700 are electrically connected.

As can be seen from FIG. 2, the display device according to an embodiment of the present invention includes a substrate 100, a gate line 200, a data line 300, a thin film transistor T, a pixel electrode 500, and a sensing line. 600, a common electrode 700, a driving integrated circuit 1, a built-in gate circuit 2, and a touch driver 3 are included.

The substrate 100 may be made of glass or transparent plastic.

The gate lines 200 are arranged on the substrate 100 in a first direction, for example, in a horizontal direction. One end of the gate line 200 is connected to the built-in gate circuit 2, and the built-in gate circuit 2 is connected to the driving integrated circuit 1 through a gate pad 215, so that the driving integrated circuit ( The gate signal applied from 1) is transferred to the gate line 200 through the gate pad 215 and the built-in gate circuit 2.

The data lines 300 are arranged on the substrate 100 in a second direction different from the first direction, for example, in a vertical direction. In this way, the gate line 200 and the data line 300 are arranged to cross each other to define a plurality of pixel regions. One end of the data line 300 is connected to the driving integrated circuit 1 through a data pad 315. Accordingly, the data signal applied from the driving integrated circuit 1 is transmitted to the data line 300 through the data pad 315. The data lines 300 are arranged in a straight straight line, but are not necessarily limited thereto, and may be arranged in a curved straight line such as a zigzag form.

The thin film transistor T is a switching element and is formed in each of the plurality of pixel regions. Although not specifically shown, the thin film transistor includes a gate electrode connected to the gate line 200, a semiconductor layer functioning as a channel through which electrons move, a source electrode connected to the data line 300, and the source electrode. It includes a drain electrode formed to face each other. The thin film transistor T may be formed in various forms known in the art, such as a top gate structure or a bottom gate structure.

The pixel electrode 500 is patterned in each of the plurality of pixel regions. The pixel electrode 500 is connected to the drain electrode of the thin film transistor T.

The sensing line 600 is connected to the common electrode 700 and serves to transmit a user's touch signal sensed by the common electrode 700 to the touch driver 3. In order to transmit such a user's touch signal, a plurality of sensing lines 600 are connected to each other while forming a pair with a plurality of common electrodes 700. That is, each of the plurality of sensing lines 600 is connected to the plurality of common electrodes 700 in a one-to-one manner.

In order to prevent a decrease in light transmittance due to the sensing line 600, the sensing line 600 is formed to overlap the data line 300.

The common electrode 700 serves as a sensing electrode for sensing a user's touch position. In addition, in the case of a liquid crystal display, the common electrode 700 forms an electric field together with the pixel electrode 500 to drive the liquid crystal. That is, the common electrode 700 may form a fringe field together with the pixel electrode 500, and for this purpose, a plurality of slits 710 are formed in the common electrode 700. Accordingly, a fringe field is formed between the pixel electrode 500 and the common electrode 700 through the slit 710, and the orientation direction of the liquid crystal can be adjusted by the fringe field. That is, a fringe field switching mode liquid crystal display can be implemented.

In addition, a plurality of common electrodes 700 are spaced apart from each other by a predetermined distance on the substrate 100 so that the common electrode 700 can function as a sensing electrode for sensing a user's touch position. Each of the plurality of common electrodes 700 is formed to have a size corresponding to one or more pixel areas, in particular, a size corresponding to a plurality of pixel areas in consideration of a user's touch area.

The driving integrated circuit 1 receives a gate control signal from a timing controller (not shown) and then applies a gate signal to the gate line 200 through the gate pad 215 and the built-in gate circuit 2. .

In addition, after receiving a data control signal from a timing controller (not shown), the driving integrated circuit 1 applies the data signal to the data line 300 through the data pad 315.

The built-in gate circuit 2 applies a gate signal transmitted from the driving integrated circuit 1 to the gate line 200, and the built-in gate circuit 2 is a GIP (gate) formed together with the transistor manufacturing process of each pixel. In Panel) method may be formed on the left and/or right non-display area of the substrate 100. In another embodiment, the built-in gate circuit 2 may have a structure of a tape carrier package (TCP) or a chip on film (COF), or a chip on glass (COG) structure mounted on the substrate 100. It can be done.

The touch driver 3 is connected to the sensing line 600 and receives a user's touch signal from the sensing line 600. The touch driver 3 senses a change in capacitance changed by the user's touch to detect whether the user touches or not and the touch position.

Hereinafter, a display device according to embodiments of the present invention will be described in more detail through a cross-sectional structure.

Embodiment 1

<Display device>

3 is a cross-sectional view of the display device according to the first embodiment of the present invention, which is a cross-sectional view of lines A-A, B-B, and C-C of FIG. 2. Lines A-A of FIG. 2 show thin film transistor areas, lines B-B of FIG. 2 show gate pad areas, and lines C-C of FIG. 2 show data pad areas.

As can be seen in FIG. 3, a gate electrode 210 and a gate pad 215 are patterned on the substrate 100. The gate electrode 210 is formed in a thin film transistor region, and the gate pad 215 is formed in a gate pad region. The gate electrode 210 may be formed to protrude from the above-described gate line 200, and the gate pad 215 is connected to one end of the above-described gate line 200 through a built-in gate circuit 2. .

A gate insulating layer 220 is formed on the gate electrode 210 and the gate pad 215. The gate insulating layer 220 is formed on the entire surface of the substrate except for the third contact hole CH3 area.

A semiconductor layer 230 is patterned on the gate insulating layer 220. The semiconductor layer 230 is formed in a thin film transistor region and a data pad region, and may be made of a silicon semiconductor material or an oxide semiconductor material.

A source electrode 310, a drain electrode 320, and a data pad 315 are patterned on the semiconductor layer 230. The source electrode 310 and the drain electrode 320 are formed on the semiconductor layer 230 in the thin film transistor region, and the data pad 315 is formed on the semiconductor layer 230 in the data pad region. In this case, the data pad 315 is connected to one end of the data line 300 described above. The source electrode 310 is connected to the data line 300, and the drain electrode 320 faces the source electrode 310 and is spaced apart from the source electrode 310.

In the case of the display device according to the first embodiment, a material layer (not shown) for forming the semiconductor layer 230 and a source electrode layer (not shown) for forming the source electrode 310/drain electrode 320 are sequentially formed. After stacking, the material layer for forming the semiconductor layer 230 and the source-drain electrode layer are simultaneously patterned in a single process using a half tone mask, so that the semiconductor layer 230 is applied not only to the thin film transistor region but also to the data pad region. It is formed under the data pad 315.

In addition, in the case of the display device according to the first embodiment, as described above, the source-drain electrode layer and the material layer are simultaneously stacked using a halftone mask after stacking the source-drain electrode layer on the material layer for forming the semiconductor layer 230. Since patterning is performed, the tail region of the semiconductor layer 230 can be minimized.

In the case of the above-described embodiment, although not shown in FIG. 3, the data line 300 is also formed in a structure in which the semiconductor layer 230 and the source-drain electrode layer are stacked.

A first passivation layer 410 is formed on the data line 300, the source electrode 310, and the drain electrode 320. The first passivation layer 410 includes an area excluding the first contact hole CH1 in the thin film transistor area, an area excluding the third contact hole CH3 in the gate pad area, and a fourth contact hole CH4 in the data pad area. It is formed in the area except for. The first passivation layer 410 may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.

A second passivation layer 420 is patterned on the first passivation layer 410. The second protective layer 420 may be formed of an organic insulating material such as an acrylic resin including photoacryl (PAC). The second passivation layer 420 may be formed to have a thickness thicker than that of the first passivation layer 410 and may serve to planarize the substrate. The second passivation layer 420 includes an area excluding the first contact hole CH1 in the thin film transistor area, an area excluding the third contact hole CH3 in the gate pad area, and a fourth contact hole CH4 in the data pad area. It is formed in the area except for.

That is, a part of the drain electrode 320 is exposed through the first contact hole CH1 formed through the first passivation layer 410 and the second passivation layer 420, and the gate insulating layer, the first passivation layer 410, and The gate pad 215 is exposed through the third contact hole CH3 formed through the second passivation layer 420, and a fourth contact hole formed through the first passivation layer 410 and the second passivation layer 420 ( The data pad 315 is exposed through CH4).

A pixel electrode 510, a connection electrode 520, a first protective electrode 530, and a second protective electrode 540 are patterned on the second protective layer 420. The pixel electrode 510 is formed to connect the drain electrode 320 exposed through the first contact hole CH1 in the thin film transistor region, and the connection electrode 520 is formed with the gate line 200 in the thin film transistor region. It is formed to overlap. The first protective electrode 530 is formed to cover the gate pad 215 exposed through the third contact hole CH3 in the gate pad region to protect the gate pad 215, and the second protective electrode 540 Is formed to cover the data pad 230 exposed through the fourth contact hole CH4 in the data pad area to protect the data pad 230.

The pixel electrode 510, the connection electrode 520, the first protective electrode 530, and the second protective electrode 540 are formed on the same layer by using the same material by a single process.

A third protective layer 440 is formed on the pixel electrode 510, the connection electrode 520, the first protective electrode 530, and the second protective electrode 540. The third protective layer 440 includes a second contact hole CH2 for exposing the connection electrode 520, a fifth contact hole CH5 for exposing the first protective electrode 530, and a second protective electrode ( It is formed on the entire surface of the substrate except for the region of the sixth contact hole CH6 for exposing the 540. The third passivation layer 440 may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.

A sensing line 600 is patterned on the third passivation layer 440. The sensing line 600 is formed in a thin film transistor region.

In an embodiment, the third passivation layer 440 and the sensing line 600 may be simultaneously formed through a patterning process using a halftone mask.

A common electrode 700 directly connected to the sensing line 600 is patterned on the sensing line 600. That is, in the display device according to the first embodiment, the sensing line 600 and the common electrode 700 are not connected through the contact hole through the insulating layer, but the common electrode 700 does not mediate the insulating layer and the sensing line ( Since it is formed directly on 600), it is formed in a structure in which the common electrode 600 and the sensing line 600 are directly connected. Through this, the deposition process of the insulating layer and the mask process for patterning the insulating layer, which were required for connecting the common electrode 600 and the sensing line 600, can be omitted, thereby simplifying the process and reducing manufacturing cost.

The common electrode 700 is patterned so that a plurality of slits 710 are provided therein. The common electrode 700 is connected to the connection electrode 520 through a second contact hole CH2 provided in the third passivation layer 440.

In the case of the display device according to the first embodiment, since the sensing line 600 and the common electrode 700 are directly connected, the common electrode 700 is formed to correspond to the first region 800 as shown in FIG. 2. In the case of ), the sensing line 600 for sensing the touch signal generated in the first region 800 may be directly connected to the other sensing line 610 for sensing the touch signal generated in the second region 900. Thus, in the case of the display device according to the present invention, as shown in FIG. 5, in order to electrically separate the common electrode 700 corresponding to the first region 800 from the other sensing line 610, the common electrode 700 By cutting along the left and right sides with respect to the other sensing line 610, it can be formed by dividing into a plurality of regions 700a and 700b. According to this embodiment, the common electrode regions 700a may be electrically connected to each other through the above-described connection electrode 520 in order to apply a common voltage, through which the sensing line 600 shown in FIG. The common electrode 700 formed in is also electrically connected to the common electrode regions 700a so that the common electrodes 700 corresponding to the first region 800 are electrically connected to each other.

On the first protective electrode 530 exposed through the fifth contact hole CH5, a gate pad electrode 750 formed at the same time as the common electrode 700 using the same material as the common electrode 700 is a first protective electrode It is formed to be connected to 530.

On the second protection electrode 540 exposed through the sixth contact hole CH6, a data pad electrode 760 formed at the same time as the common electrode 700 using the same material as the common electrode 700 is a second protection electrode. It is formed to be connected to 540.

<Display device manufacturing method>

4A to 4F are schematic cross-sectional views of a manufacturing process of the display device according to the first embodiment of the present invention, which are related to the manufacturing process of the display device shown in FIG. 3.

First, as can be seen in FIG. 4A, a gate electrode 210 and a gate pad 215 are patterned on the substrate 100. The gate electrode 210 is formed in a thin film transistor region, and the gate pad 215 is formed in a gate pad region.

After depositing a thin film layer on the substrate 100 by a sputtering method for the gate electrode 210 and the gate pad 215, a series of mask processes such as photoresist coating, exposure, development, etching, and stripping Through the pattern can be formed. The pattern formation process of the components described below may also be performed through deposition of such a thin film layer and a series of mask processes.

Next, as shown in FIG. 4B, a material for forming a gate insulating layer 220 on the gate electrode 210 and the gate pad 215 and forming the semiconductor layer 230 on the gate insulating layer 220 After forming the layer (not shown) and the source-drain electrode layer (not shown) for forming the source-drain electrode, the material layer and the source-drain electrode layer for forming the semiconductor layer 230 are formed in a single process using a halftone mask. By patterning, the semiconductor layer 230 and the source electrode 310 and the drain electrode 320 formed on the semiconductor layer 230 are formed. Accordingly, the semiconductor layer 230 is formed not only in the thin film transistor region but also in the data pad region, and the data pad 315 is formed on the semiconductor layer 230 formed in the data pad region.

The gate insulating layer 220 is formed on the entire surface of the substrate by PECVD (Plasma Enhanced Chemical Vapor Deposition).

In one embodiment, in the process of forming the semiconductor layer 230, the source electrode 310, and the drain electrode 320, or the data pad 315 or the data line 300, the source-drain electrode layer is first wet etched ( After performing wet etching, dry etching of the semiconductor layer 230, an ashing process of the halftone mask, the source-drain electrode layer is subjected to secondary wet etching, and thus the semiconductor layer 230 and the source electrode ( 310) and a drain electrode 320 may be formed.

In another embodiment, after performing the first wet etching of the source-drain electrode layer and an ashing process of the halftone mask, after dry etching the semiconductor layer 230, the source-drain electrode layer The semiconductor layer 230, the source electrode 310, and the drain electrode 320 may be formed by performing the secondary wet etching.

In the above-described embodiments, when the semiconductor layer 230 is dry-etched, the semiconductor layer 230 is first dry-etched using the first process gas composed of SF _{6 /} He/Cl ₂ and then SF ₆ /O ₂ / The semiconductor layer 230 may be subjected to a second dry etching using a second process gas composed of Cl ₂ . The tail region of the semiconductor layer 230 can be minimized through a two-step etching process using the first process gas and the second process gas as described above.

Next, as shown in FIG. 4C, after sequentially forming the first passivation layer 410 and the second passivation layer 420 on the entire surface of the substrate including the source electrode 310 and the drain electrode 320, a halftone mask A first contact hole CH1, a gate insulating layer 220, and a first protective layer exposing the drain electrode 320 by simultaneously removing portions of the first and second protective layers 410 and 420 through a patterning process using The third contact hole CH3 exposing the gate pad 215 by removing a portion of the 410 and the second passivation layer 420, and a portion of the first passivation layer 410 and the second passivation layer 420 are removed. Thus, a fourth contact hole CH4 exposing the data pad 230 is formed.

The first protective layer 410 is formed on the entire surface of the substrate by PECVD.

The second passivation layer 420 is formed by applying an organic insulating material including photoacryl (PAC) on the entire surface of the substrate.

Next, as shown in FIG. 4D, after forming a pixel electrode layer (not shown) on the entire surface of the substrate, the pixel electrode layer is patterned to be connected to the drain electrode 320 exposed through the first contact hole CH1. 510, a connection electrode 520 formed to overlap a gate line (not shown), a first for protecting the gate pad 215 on the gate pad 215 exposed through the third contact hole CH3 A second protective electrode 540 for protecting the data pad 315 is formed on the protective electrode 530 and the data pad 230 exposed through the fourth contact hole CH4.

Next, as shown in FIG. 4E, a third protective layer 440 is formed on the entire surface of the substrate including the pixel electrode 510, the connection electrode 520, the first protective electrode 530, and the second protective electrode 540. ) And a metal layer (not shown) for forming the sensing line 600, and then patterning at least one of the third passivation layer 440 and the metal layer through a single process using a halftone mask to form the third passivation layer 440 A second contact hole CH2 for exposing the connection electrode 520, a fifth contact hole CH5 for exposing the first protective electrode 530, and a second protection A sixth contact hole CH6 for exposing the electrode 540 is formed.

To explain this in more detail, after applying the third protective film 440 and the metal layer to the entire surface of the substrate through a photo process, a photoresist having a first thickness (for example, a full photoresist) is applied to the region where the sensing line 600 will be formed. And the second contact hole CH2, the fifth contact hole CH5, and the sixth contact hole CH6 are formed, a photoresist is not formed, and a region in which the sensing line 600 is to be formed is 2 A photoresist having a second thickness (eg, half photoresist) that is thinner than the first thickness is formed in the areas excluding the areas where the contact hole CH2, the fifth contact hole CH5, and the sixth contact hole CH6 will be formed. do.

Thereafter, first wet etching of the metal layer and dry etching of the third passivation layer 440 are performed to form a second contact hole CH2, a fifth contact hole CH5, and a sixth contact hole CH6.

Thereafter, the ashing process is performed to remove the photoresist except for the photoresist formed in the region where the sensing line 600 is to be formed, and the metal layer is removed by secondary wet etching of the metal layer to form the sensing line 600. . In one embodiment, only the metal layer is etched according to the selectivity of the wet etching by using a superaqueous etchant during the second wet etching of the metal layer. For example, when the metal layer is formed of copper (Cu), only the metal layer formed of copper may be selectively etched by using a superaqueous etchant to etch only copper.

Thereafter, the photoresist remaining on the sensing line 600 is removed.

Next, as shown in FIG. 4F, a material layer (not shown) for forming the common electrode 700 is directly formed on the sensing line 600 on the entire surface of the substrate including the sensing line 600, and then the common By patterning a material layer for forming the electrode 700, the common electrode 700 and the fifth contact hole CH5 are directly connected to the sensing line 600 and connected to the connection electrode 520 through the second contact hole CH2. A gate pad electrode 750 connected to the first protective electrode 530 exposed through ), and a data pad electrode 760 connected to the second protective electrode 540 exposed through the sixth contact hole CH6 Simultaneously form.

The common electrode 700 is patterned so that a plurality of slits 710 are provided therein in the thin film transistor region, and in particular, a pattern is formed to be connected to the connection electrode 520 through the second contact hole CH2. .

As described above, in the case of the manufacturing method of the display device according to the first embodiment, since the sensing line 600 and the common electrode 700 are directly connected, the first region 800 as shown in FIG. 2 In the case of the common electrode 700 formed to correspond to the sensing line 600 for sensing the touch signal generated in the first region 800, other sensing for sensing the touch signal generated in the second region 900 Since it can be directly connected to the line 610, in the case of the manufacturing method of the display device according to the present invention, in order to electrically separate the common electrode 700 corresponding to the first region 800 from the other sensing line 610, As shown, by cutting the common electrode 700 along the left and right sides with respect to the other sensing line 610, the common electrode 700 is divided into a plurality of regions 700a and 700b to be formed. According to this embodiment, the common electrode regions 700a may be electrically connected to each other through the above-described connection electrode 520 in order to apply a common voltage, through which the sensing line 600 shown in FIG. The common electrode 700 formed in is also electrically connected to the common electrode regions 700a so that the common electrodes 700 corresponding to the first region 800 are electrically connected to each other.

According to the method of FIGS. 4A to 4F described above, compared to the prior art in which a display device was manufactured through nine mask processes, a source-drain electrode layer and a material layer for forming the semiconductor layer 230 are sequentially stacked, Since patterning is performed through the process, the number of masks is reduced by one compared to the conventional technology in which the semiconductor layer 230 and the source/drain electrodes are separately formed, and a metal layer for forming the third protective layer 440 and the sensing line 600 is formed. After sequentially stacking and patterning through a single process, the number of masks is further reduced by one, and since the insulating film interposed between the sensing line 600 and the common electrode 700 is omitted, the formation and patterning of the insulating film are not performed. The mask required for this can be further reduced, and as a result, it is possible to manufacture a display device with only six masks. Therefore, the effect of maximizing productivity through a reduction in manufacturing time occurs.

Embodiment 2

<Display device>

6 is a cross-sectional view of a display device according to a second embodiment of the present invention, which is a cross-sectional view of lines A-A, B-B, and C-C of FIG. 2. Lines A-A of FIG. 2 show thin film transistor areas, lines B-B of FIG. 2 show gate pad areas, and lines C-C of FIG. 2 show data pad areas.

As can be seen from FIG. 6, a gate electrode 210 and a gate pad 215 are patterned on the substrate 100. The gate electrode 210 is formed in a thin film transistor region, and the gate pad 215 is formed in a gate pad region. The gate electrode 210 may be formed to protrude from the above-described gate line 200, and the gate pad 215 is connected to one end of the above-described gate line 200 through a built-in gate circuit 2. .

First protective electrodes 530 are respectively formed on the gate electrode 210 and the gate pad 215. The first protective electrode 530 is formed of a transparent conductive material such as Indium Tin Oxide (ITO). The first protective electrode 530 is for preventing the gate pad 215 from being etched during patterning of the third protective layer 440 to be described later.

A gate insulating layer 220 is formed on the gate electrode 210 and the gate pad 215 on which the first protective electrode 530 is formed. The gate insulating layer 220 is formed on the entire surface of the substrate except for the fifth contact hole CH5.

A semiconductor layer 230 is patterned on the gate insulating layer 220. The semiconductor layer 230 is formed in a thin film transistor region and a data pad region, and may be made of a silicon semiconductor material or an oxide semiconductor material.

A source electrode 310, a drain electrode 320, and a data pad 315 are patterned on the semiconductor layer 230. The source electrode 310 and the drain electrode 320 are formed on the semiconductor layer 230 in the thin film transistor region, and the data pad 315 is formed on the semiconductor layer 230 in the data pad region. In this case, the data pad 315 is connected to one end of the data line 300 described above. The source electrode 310 is connected to the data line 300, and the drain electrode 320 faces the source electrode 310 and is spaced apart from the source electrode 310.

In the case of the display device according to the second embodiment, a material layer (not shown) for forming the semiconductor layer 230 and the source electrode 310/drain electrode 320 are formed in the same manner as the display device according to the first embodiment. Since the source and drain electrode layers (not shown) are sequentially stacked and then the material layer and the source drain electrode layer for forming the semiconductor layer 230 are simultaneously patterned in a single process using a half tone mask, the thin film transistor region In addition, the semiconductor layer 230 is formed under the data pad 315 in the data pad area as well.

In addition, in the case of the display device according to the second embodiment, as described above, the source-drain electrode layer and the material layer are simultaneously stacked using a halftone mask after laminating the source-drain electrode layer on the material layer for forming the semiconductor layer 230. Since patterning is performed, the tail region of the semiconductor layer 230 can be minimized.

In the case of the above-described embodiment, although not shown in FIG. 6, the data line 300 is also formed in a structure in which the semiconductor layer 230 and the source-drain electrode layer are stacked.

A first passivation layer 410 is formed on the data line 300, the source electrode 310, and the drain electrode 320. The first passivation layer 410 is formed only in a region other than the first contact hole CH1 in the thin film transistor region, and is not formed in the gate pad region and the data pad region. The first passivation layer 410 may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.

A second passivation layer 420 is patterned on the first passivation layer 410. The second protective layer 420 may be formed of an organic insulating material such as an acrylic resin including photoacryl (PAC). The second passivation layer 420 may be formed to have a thickness thicker than that of the first passivation layer 410 and may serve to planarize the substrate. The second passivation layer 420 is formed only in a region other than the first contact hole CH1 in the thin film transistor region, and is not formed in the gate pad region and the data pad region.

That is, a part of the drain electrode 320 is exposed through the first contact hole CH1 formed through the first passivation layer 410 and the second passivation layer 420.

A pixel electrode 510 and a connection electrode 520 are formed on the second passivation layer 420. The pixel electrode 510 is formed to connect the drain electrode 320 exposed through the first contact hole CH1 in the thin film transistor region, and the connection electrode 520 overlaps the gate line 200 in the thin film transistor region. Is formed to be.

Meanwhile, in the data pad area, a second protective electrode 540 for protecting the data pad 315 is patterned on the data pad 315 to be connected to the data pad 315. The second protective electrode 540 is formed on the data pad 315 to cover the entire data pad 315.

The pixel electrode 510, the connection electrode 520, and the second protective electrode 540 are formed on the same layer using the same material by a single process.

A third protective layer 440 is formed on the pixel electrode 510, the connection electrode 520, and the second protective electrode 540. The third protective layer 440 includes a second contact hole CH2 for exposing the connection electrode 520, a fifth contact hole CH5 for exposing the first protective electrode 530, and a second protective electrode ( It is formed on the entire surface of the substrate except for the region of the sixth contact hole CH6 for exposing the 540. The third passivation layer 440 may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.

A sensing line 600 is patterned on the third passivation layer 440. The sensing line 600 is formed in a thin film transistor region.

In an embodiment, the third passivation layer 440 and the sensing line 600 may be simultaneously formed through a patterning process using a halftone mask.

A common electrode 700 directly connected to the sensing line 600 is patterned on the sensing line 600. That is, in the display device according to the second embodiment, similar to the display device according to the first embodiment, the sensing line 600 and the common electrode 700 are not connected through a contact hole through an insulating layer, but a common electrode. The common electrode 600 and the sensing line 600 are directly connected to each other because 700 is formed directly on the sensing line 600 without intervening the insulating layer. Through this, the deposition process of the insulating layer and the mask process for patterning the insulating layer, which were required for connecting the common electrode 600 and the sensing line 600, can be omitted, thereby simplifying the process and reducing manufacturing cost.

The common electrode 700 is patterned so that a plurality of slits 710 are provided therein. The common electrode 700 is connected to the connection electrode 520 through a second contact hole CH2 provided in the third passivation layer 440.

In the case of the display device according to the second embodiment, the sensing line 600 and the common electrode 700 are directly connected in the same way as the display device according to the first embodiment. As shown in FIG. In the case of the common electrode 700 formed to correspond to the first region 800, the touch signal generated in the second region 900 is not the sensing line 600 for sensing the touch signal generated in the first region 800. The display device according to the second embodiment can also be directly connected to the other sensing line 610 for sensing, so that the common electrode 700 corresponding to the first region 800 is similar to the display device according to the first embodiment. 5, the common electrode 700 is cut along the left and right sides with respect to the other sensing line 610 in order to electrically separate it from the other sensing line 610, thereby forming a plurality of regions 700a and 700b. ) Can be formed. According to this embodiment, the common electrode regions 700a may be electrically connected to each other through the above-described connection electrode 520 in order to apply a common voltage, through which the sensing line 600 shown in FIG. The common electrode 700 formed in is also electrically connected to the common electrode regions 700a so that the common electrodes 700 corresponding to the first region 800 are electrically connected to each other.

On the first protective electrode 530 exposed through the fifth contact hole CH5, a gate pad electrode 750 formed at the same time as the common electrode 700 using the same material as the common electrode 700 is a first protective electrode It is formed to be connected to 530.

On the second protection electrode 540 exposed through the sixth contact hole CH6, a data pad electrode 760 formed at the same time as the common electrode 700 using the same material as the common electrode 700 is a second protection electrode. It is formed to be connected to 540.

<Display device manufacturing method>

7A to 7F are schematic cross-sectional views of a manufacturing process of a display device according to a second exemplary embodiment of the present invention, which relates to a process of manufacturing the display device shown in FIG. 6.

First, as shown in FIG. 7A, a gate electrode layer (not shown) for forming the gate electrode 210 and the gate pad 215 and a material layer (not shown) for forming the first protective electrode 530 are formed on a substrate ( 100) and then patterning the gate electrode 210, the first protective electrode 530 formed on the gate electrode 210, the gate pad 215, and the first formed on the gate pad 215 A protective electrode 530 is formed. The first protective electrode 530 is for preventing the first protective electrode 530 from being etched during patterning of the third protective layer 440 to be described later. Although not shown in FIG. 7A, the first protective electrode 530 is also formed on the gate line 200.

The gate electrode 210 is formed in a thin film transistor region, and the gate pad 215 is formed in a gate pad region.

The material layer for forming the first protective electrode 530 may be formed of a transparent conductive material such as ITO.

The gate electrode 210, the first protective electrode 530 formed on the gate electrode 210, the gate pad 215, and the first protective electrode 530 formed on the gate pad 215 are the substrate 100 After depositing a gate electrode layer (not shown) and a material layer (not shown) for forming the first protective electrode 530 by a sputtering method, photoresist coating, exposure, development, etching, and stripping are used. The pattern can be formed through a series of mask processes. The pattern formation process of the components described below may also be performed through deposition of such a thin film layer and a series of mask processes.

Next, as can be seen in FIG. 7B, the gate insulating layer 220 on the gate electrode 210 on which the first protective electrode 530 is formed and the gate pad 215 on which the first protective electrode 530 is formed. After forming a material layer (not shown) for forming the semiconductor layer 230 and a source-drain electrode layer (not shown) for forming the source-drain electrode on the gate insulating layer 220, the semiconductor layer ( The source electrode 310 and the drain electrode 320 formed on the semiconductor layer 230 and the semiconductor layer 230 are formed by patterning the material layer and the source drain electrode layer for forming 230 in a single process using a halftone mask. To form. Accordingly, the semiconductor layer 230 is formed not only in the thin film transistor region but also in the data pad region, and the data pad 315 is formed on the semiconductor layer 230 formed in the data pad region.

The gate insulating layer 220 is formed on the entire surface of the substrate by PECVD (Plasma Enhanced Chemical Vapor Deposition).

In one embodiment, in the process of forming the semiconductor layer 230, the source electrode 310, and the drain electrode 320, or the data pad 315 or the data line 300, the source-drain electrode layer is first wet etched ( After performing wet etching, dry etching of the semiconductor layer 230, an ashing process of the halftone mask, the source-drain electrode layer is subjected to secondary wet etching, and thus the semiconductor layer 230 and the source electrode ( 310) and a drain electrode 320 may be formed.

In another embodiment, after performing the first wet etching of the source-drain electrode layer and an ashing process of the halftone mask, after dry etching the semiconductor layer 230, the source-drain electrode layer The semiconductor layer 230, the source electrode 310, and the drain electrode 320 may be formed by performing the secondary wet etching.

In the above-described embodiments, when the semiconductor layer 230 is dry-etched, the semiconductor layer 230 is first dry-etched using the first process gas composed of SF ₆ /He/Cl ₂ , and then SF ₆ /O ₂ / The semiconductor layer 230 may be subjected to a second dry etching using a second process gas composed of Cl ₂ . The tail region of the semiconductor layer 230 can be minimized through a two-step etching process using the first process gas and the second process gas as described above.

Next, as shown in FIG. 7C, after sequentially patterning the first passivation layer 410 and the second passivation layer 420 on the thin film transistor region including the source electrode 310 and the drain electrode 320, A first contact hole CH1 exposing the drain electrode 320 is formed by removing portions of the first passivation layer 410 and the second passivation layer 420.

That is, in the method of manufacturing the display device according to the second embodiment, unlike the first embodiment, the first passivation layer 410 and the second passivation layer 420 are not formed on the gate pad area and the data pad area.

Accordingly, in the method of manufacturing the display device according to the second exemplary embodiment, the halftone mask is not used for patterning the first and second passivation layers 410 and 420.

Next, as can be seen in FIG. 7D, after forming a pixel electrode layer (not shown) on the entire surface of the substrate, the pixel electrode layer is patterned to be connected to the drain electrode 320 exposed through the first contact hole CH1. 510, a connection electrode 520 formed to overlap a gate line (not shown), and a data pad 310 to protect the data pad 315 on the data pad 315 formed in the data pad region A second protective electrode 540 covering the is formed.

Next, as shown in FIG. 7E, a third protective layer 440 and a sensing line 600 are formed on the entire surface of the substrate including the pixel electrode 510, the connection electrode 520, and the second protective electrode 540. After applying a metal layer (not shown) for forming a sensing line 600 on the third passivation layer 440 by patterning at least one of the third passivation layer 440 and the metal layer through a single process using a halftone mask And a second contact hole CH2 for exposing the connection electrode 520, a fifth contact hole CH5 for exposing the first protective electrode 530, and the second protective electrode 540. A sixth contact hole CH6 is formed.

To explain this in more detail, after applying the third protective film 440 and the metal layer to the entire surface of the substrate through a photo process, a photoresist having a first thickness (for example, a full photoresist) is applied to the region where the sensing line 600 will be formed. And the second contact hole CH2, the fifth contact hole CH5, and the sixth contact hole CH6 are formed, a photoresist is not formed, and a region in which the sensing line 600 is to be formed is 2 A photoresist having a second thickness (eg, half photoresist) that is thinner than the first thickness is formed in the areas excluding the areas where the contact hole CH2, the fifth contact hole CH5, and the sixth contact hole CH6 will be formed. do.

Thereafter, first wet etching of the metal layer and dry etching of the third passivation layer 440 are performed to form a second contact hole CH2, a fifth contact hole CH5, and a sixth contact hole CH6.

Thereafter, the ashing process is performed to remove the photoresist except for the photoresist formed in the region where the sensing line 600 is to be formed, and the metal layer is removed by secondary wet etching of the metal layer to form the sensing line 600. . In one embodiment, only the metal layer is etched according to the selectivity of the wet etching by using a superaqueous etchant during the second wet etching of the metal layer. For example, when the metal layer is formed of copper (Cu), only the metal layer formed of copper may be selectively etched by using a superaqueous etchant to etch only copper.

Thereafter, the photoresist remaining on the sensing line 600 is removed.

Next, as shown in FIG. 7F, a material layer (not shown) for forming the common electrode 700 is directly formed on the sensing line 600 on the entire surface of the substrate including the sensing line 600, and then the common By patterning a material layer for forming the electrode 700, the common electrode 700 and the fifth contact hole CH5 are directly connected to the sensing line 600 and connected to the connection electrode 520 through the second contact hole CH2. A gate pad electrode 750 connected to the first protective electrode 530 exposed through ), and a data pad electrode 760 connected to the second protective electrode 540 exposed through the sixth contact hole CH6 Simultaneously form.

The common electrode 700 is patterned so that a plurality of slits 710 are provided therein in the thin film transistor region, and in particular, a pattern is formed to be connected to the connection electrode 520 through the second contact hole CH2. .

In the case of the manufacturing method of the display device according to the second embodiment, since the sensing line 600 and the common electrode 700 are directly connected to each other, as shown in FIG. 2, so that it corresponds to the first region 800. In the case of the formed common electrode 700, other sensing lines 610 for sensing a touch signal generated in the second region 900 instead of the sensing line 600 for sensing a touch signal generated in the first region 800 ) Can also be directly connected, in the case of the manufacturing method of the display device according to the second embodiment, the above-described in order to electrically separate the common electrode 700 corresponding to the first region 800 from the other sensing line 610. As shown in FIG. 5, the common electrode 700 is cut along the left and right sides with respect to the other sensing line 610 to form a division into a plurality of regions 700a and 700b. According to this embodiment, in order to apply a common voltage, the common electrode regions 700a may be electrically connected to each other through the above-described connection electrode 520, through which the sensing line 600 shown in FIG. The common electrode 700 formed in is also electrically connected to the common electrode regions 700a so that the common electrodes 700 corresponding to the first region 800 are electrically connected to each other.

In the method illustrated in FIGS. 7A to 7F described above, a source-drain electrode layer and a material layer for forming the semiconductor layer 230 are sequentially stacked compared to the prior art in which the display device is manufactured through nine mask processes. Since patterning is performed through the process of, the number of masks is reduced by one compared to the conventional technology in which the semiconductor layer 230 and the source/drain electrodes are separately formed, and a metal layer for forming the third protective layer 440 and the sensing line 600 The number of masks is reduced by one additionally since the layers are sequentially stacked and then patterned through a single process, and since the insulating layer interposed between the sensing line 600 and the common electrode 700 is omitted, the formation and patterning of an insulating layer It is possible to further reduce the mask required for this, and as a result, it is possible to manufacture a display device with only six masks. Therefore, the effect of maximizing productivity through a reduction in manufacturing time occurs.

In the above, a substrate constituting a display device and a method for manufacturing the same have been described. The present invention relates to various display devices that can use the above-described substrate and the method for manufacturing the same, for example, a liquid crystal display device and a plasma display device. And a plasma display panel, an organic light emitting display device, and a manufacturing method thereof.

100: substrate 200: gate line
210: gate electrode 215: gate pad
220: gate insulating film 230: semiconductor layer
300: data line 315: data pad
310: source electrode 320: drain electrode
410, 420, 440: first, second, third protective layer
510: pixel electrode 520: connection electrode
530: first protective electrode 540: second protective electrode
600: sensing line 700: common electrode
710: slit 750: gate pad electrode
760: data pad electrode

Claims (11)

A thin film transistor formed in a pixel region defined by a cross arrangement of gate lines and data lines and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode;
A first passivation layer and a second passivation layer sequentially formed on the thin film transistor and having a first contact hole for exposing the drain electrode;
A pixel electrode formed on the second passivation layer and connected to the drain electrode through the first contact hole;
A third protective layer formed on the pixel electrode;
A first sensing line formed on the third passivation layer;
A connection electrode formed of the same material as the pixel electrode between the second passivation layer and the third passivation layer;
A second contact hole exposing the connection electrode in the third passivation layer; And
A display device comprising: a common electrode directly connected to the first sensing line on the first sensing line and connected to the connection electrode exposed through the second contact hole. The method of claim 1,
Further comprising a second sensing line formed between the third passivation layer and the common electrode,
The first sensing line is connected to a common electrode corresponding to a first region including the pixel region, and the second sensing line is connected to a common electrode corresponding to a second region adjacent to the first region,
The common electrode includes a plurality of regions cut along left and right sides of each of the first sensing line and the second sensing line, and a region of the common electrode directly connected to the first sensing line, and the first and second sensing lines. Areas of the common electrode that are not directly connected to the second sensing line are electrically connected to each other through the connection electrode exposed through the second contact hole. The method of claim 1,
A gate pad connected to one end of the gate line;
A data pad connected to one end of the data line;
A first protective electrode connected to the gate pad exposed through a third contact hole formed in the first and second protective layers;
A second protective electrode connected to the data pad exposed through a fourth contact hole formed in the first and second protective layers;
A gate pad electrode connected to the first protective electrode exposed through a fifth contact hole formed in the third protective layer; And
Further comprising a data pad electrode connected to the second protective electrode exposed through a sixth contact hole formed in the third protective layer,
The gate pad electrode and the data pad electrode are formed of the same material as the common electrode,
The first protective electrode and the second protective electrode are formed of the same material as the pixel electrode. The method of claim 1,
A gate pad connected to one end of the gate line;
A data pad connected to one end of the data line;
A first protective electrode formed on the gate pad;
A second protective electrode formed on the data pad;
A gate pad electrode connected to the first protective electrode exposed through a fifth contact hole formed in the third protective layer; And
Further comprising a data pad electrode connected to the second protective electrode exposed through a sixth contact hole formed in the third protective layer,
The gate pad electrode and the data pad electrode are formed of the same material as the common electrode. The method according to claim 3 or 4,
The data line and the data pad,
A first material layer formed of the same material as the semiconductor layer; And
A display device comprising a second material layer formed of the same material as the source electrode and the drain electrode on the first material layer. Forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode on a substrate;
Sequentially forming a first passivation layer and a second passivation layer on the thin film transistor in which a first contact hole is formed for exposing the drain electrode;
Forming a pixel electrode layer on the second passivation layer;
Forming a connection electrode by patterning the pixel electrode layer, and forming a pixel electrode connected to the drain electrode through the first contact hole;
Sequentially forming a third protective layer and a metal layer for forming a sensing line on the entire surface of the substrate including the pixel electrode and the connection electrode;
The third passivation layer and the metal layer are patterned through a patterning process using a halftone mask to form a first sensing line and a second sensing line on the third passivation layer, and form a second contact hole exposing the connection electrode to the third passivation layer. Forming on a protective film; And
And forming a pattern of a common electrode directly connected to the first sensing line on the first sensing line and connected to the connection electrode exposed through the second contact hole. The method of claim 6,
The common electrode is composed of a plurality of regions corresponding to a first region including a plurality of pixel regions, cut along left and right sides of the first sensing line and the second sensing line to form a pattern,
The first sensing line is formed to be connected to the common electrode corresponding to the first region, the second sensing line is formed to be connected to another common electrode corresponding to a second region adjacent to the first region,
A method of manufacturing a display device in which regions of the common electrode that are not directly connected to the first and second sensing lines are electrically connected to each other through the connection electrode exposed through the second contact hole. The method of claim 6,
The step of forming a thin film transistor,
Forming a gate electrode and a gate pad on the substrate;
Sequentially forming a gate insulating layer, a first material layer, and a second material layer on the entire surface of the substrate including the gate electrode and the gate pad; And
Data consisting of the first and second material layers and the thin film transistor including a semiconductor layer, a source electrode, and a drain electrode by simultaneously patterning the first material layer and the second material layer through a patterning process using a halftone mask Forming a pad,
The patterning process using the halftone mask is performed by sequentially using a first process gas composed of SF ₆ /He/Cl ₂ and a second process gas composed of SF ₆ /O ₂ /Cl ₂ . The method of claim 8,
In the step of sequentially forming the first and second protective layers, a third contact hole for exposing the gate pad and a fourth contact hole for exposing the data pad are additionally formed through a patterning process using a halftone mask Forming the first protective film and the second protective film as possible,
In forming the pixel electrode, the pixel electrode layer is patterned to connect the first protective electrode connected to the gate pad exposed through the third contact hole and the data pad exposed through the fourth contact hole. Forming a second protective electrode,
In the step of forming the second contact hole in the third protective layer, the third protective layer and the metal layer are patterned to expose the fifth contact hole and the second protective electrode to expose the first protective electrode to the third protective layer. Forming an additional sixth contact hole,
In forming the common electrode, a gate pad electrode connected to the first protective electrode exposed through the fifth contact hole and a data pad electrode connected to the second protective electrode exposed through the sixth contact hole Display device manufacturing method for further forming. The method of claim 8,
In the step of forming the gate pad, a first protective electrode is patterned between the gate pad and the gate insulating layer,
In the step of forming the pixel electrode, a second protective electrode is additionally formed on the data pad by patterning the pixel electrode layer,
In the step of forming the second contact hole in the third protective layer, the third protective layer and the metal layer are patterned to expose the fifth contact hole and the second protective electrode to expose the first protective electrode to the third protective layer. Forming an additional sixth contact hole,
In forming the common electrode, a gate pad electrode connected to the first protective electrode exposed through the fifth contact hole and a data pad electrode connected to the second protective electrode exposed through the sixth contact hole Display device manufacturing method for further forming. The method of claim 6,
In the step of forming the second contact hole in the third passivation layer, the third passivation layer and the metal layer are selectively patterned using a superaqueous etchant.

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