KR102170395B1 - Response unstability detection apparatus and method based on response decision time for complementary physical unclonable function - Google Patents

Abstract

A semiconductor chip is provided that detects the unstability of a response signal generated by a physically unclonable function (PUF) circuit. The semiconductor chip executes a predetermined digital operation using an output signal output from the physical copy prevention function circuit and an inversion signal of the output signal, and outputs a result of the digital operation to a sampling circuit, an operation signal In response to, a reference signal generation circuit for outputting a reference signal for determining a sampling time of the sampling circuit to the sampling circuit and a result value of the digital operation are sampled according to the reference signal, and the physical When it is determined that the response signal of the copy-prevention function circuit is determined, a sampling circuit for storing the first signal and the second signal when it is determined that the response signal of the physical copy-prevention function circuit is determined may be included.

Description

A device and method for detecting instability of a response signal using a response decision time applicable to a physical copy prevention function circuit with complementary responses {RESPONSE UNSTABILITY DETECTION APPARATUS AND METHOD BASED ON RESPONSE DECISION TIME FOR COMPLEMENTARY PHYSICAL UNCLONABLE FUNCTION}

The following embodiments relate to an apparatus and method for detecting instability of a response signal. More specifically, it relates to a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response.

A physical unclonable function (PUF) system based on a CMOS (complementary metal-oxide semiconductor) process, which has the advantage of high integration and low cost, provides a unique value (ID or Response ) Can be generated randomly and quickly. Such random eigenvalues are generated due to process mismatch even if a semiconductor chip having the same structure (same layout) is produced when a semiconductor chip including a physical copy protection function circuit using CMOS is manufactured. Physical copy protection function The fact that the circuit has the same physical value by the same input regardless of changes in the external environment can be expressed as a probabilistic property called Reproducibility or Stability, and this probabilistic property is a physical copy protection function. It is one of the important performance indicators of the circuit. However, the existing physical copy protection circuit has a problem in that it has poor performance in terms of reproducibility due to external environment (temperature change, supply voltage change, malicious attack, etc.).

Korean Patent Application Publication No. 10-2018-0050276 is an invention related to a silicon integrated circuit for testing the reliability of intrinsic values provided by a PUF circuit. Specifically, the target patent includes a configuration including an abnormal response and an inconsistent response based on a predefined response distribution in order to detect an error of a PUF circuit.

According to one side, there is provided a semiconductor chip that detects the unstability of a response signal generated by a physically unclonable function (PUF) circuit. The semiconductor chip executes a predetermined digital operation using an output signal output from the physical copy prevention function circuit and an inversion signal of the output signal, and outputs a result of the digital operation to a sampling circuit, an operation signal In response to, a reference signal generation circuit for outputting a reference signal for determining a sampling time of the sampling circuit to the sampling circuit and a result value of the digital operation are sampled according to the reference signal, and the physical When it is determined that the response signal of the copy-prevention function circuit is determined, a sampling circuit for storing the first signal and the second signal when it is determined that the response signal of the physical copy-prevention function circuit is determined may be included.

According to an embodiment, the operation circuit may include an XOR gate, and a result of an XOR operation performed on the output signal and an inverted signal of the output signal may be output to the sampling circuit as a result value of the digital operation. .

According to another embodiment, the reference signal generation circuit determines a delayed sampling time of the sampling circuit based on an input select signal, and outputs a reference signal corresponding to the delayed sampling time to the sampling circuit. can do.

According to another embodiment, the sampling circuit may include a D-flip-flop, and may sample a result value of the digital operation by using the reference signal as a clock signal.

According to another embodiment, when it is determined that the response signal of the physical copy prevention function circuit is determined based on the delayed sampling time, the sampling circuit prevents the first signal and the physical copy with a high value. When it is determined before the response signal of the functional circuit is determined, a second signal having a low value may be output as a stability check bit of the physical copy prevention function circuit.

1 is a block diagram of a response instability detection circuit applicable to a physical copy protection function circuit according to an embodiment.
FIG. 2 is a block diagram illustrating a configuration and operation of a response instability detection circuit applicable to a physical copy protection function circuit according to another embodiment.
3 is a flow chart illustrating the operation of an embodiment of a response instability detection circuit applicable to a physical copy prevention function circuit according to an embodiment.
4 shows a simulation result of an embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response.
5 shows a simulation result of another embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only, and may be changed in various forms and implemented. Accordingly, the embodiments are not limited to a specific disclosure form, and the scope of the present specification includes changes, equivalents, or substitutes included in the technical idea.

Although terms such as first or second may be used to describe various components, these terms should be interpreted only for the purpose of distinguishing one component from other components. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

When a component is referred to as being "connected" to another component, it is to be understood that it may be directly connected or connected to the other component, but other components may exist in the middle.

Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate that the specified features, numbers, steps, actions, components, parts, or combinations thereof exist, but one or more other features or numbers, It is to be understood that the presence or addition of steps, actions, components, parts, or combinations thereof, does not preclude the possibility of preliminary exclusion.

Unless otherwise defined, all terms, including technical or scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the relevant technical field. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this specification. Does not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same reference numerals are assigned to the same components regardless of the reference numerals, and redundant descriptions thereof will be omitted.

Embodiments to be described below are that it is possible to solve the problem that the existing physical replication impossible function has a reproducibility error due to an external environment (temperature change, supply voltage change, malicious attack, etc.). When a unique value of a physically non-replicable function with a complementary response is generated, the response stability information of each cell determined according to the threshold (sampling time) specified by the system designer is generated together. Accordingly, the error can be resolved inside the chip through an additional circuit, or the instability information can be transmitted to the outside of the chip along with the intrinsic value of the physically replicable function to resolve the error through post-processing.

1 is a block diagram of a response instability detection circuit applicable to a physical copy protection function circuit according to an embodiment. Referring to FIG. 1, a physical copy protection function circuit (Complementary PUF) 110 for generating a complementary response may generate a complementary response signal PUF_OUT. In this case, the response instability detection circuit 100 may include a comparison circuit 120 and a memory 130. The comparison circuit 120 may compare the response signal and the reference signal (response determination threshold time). More specifically, the comparison circuit 120 compares until the time when the response signal is generated and determined, determines whether the response is a stable response or an unstable response according to the response determination time, and stores response stability information in the memory 130 do.

The memory 130 may transmit response stability information as a stability check bit, and allow a physical copy protection function circuit to use only a stable response as a key.

)를 이용하여 미리 지정된 디지털 연산을 실행하고, 디지털 연산의 결과값을 샘플링 회로로 출력할 수 있다. 보다 구체적으로, 연산 회로(220)는 XOR 게이트를 포함하고, 상기 출력 신호와 상기 출력 신호의 반전 신호에 대해 수행된 XOR 연산의 결과를 상기 디지털 연산의 결과값으로서 상기 샘플링 회로로 출력할 수 있다.FIG. 2 is a block diagram illustrating a configuration and operation of a response instability detection circuit applicable to a physical copy protection function circuit according to another embodiment. Referring to FIG. 2, the response instability detection circuit 200 may include an operation circuit 220, a reference signal generation circuit 230, and a sampling circuit 240. The physical copy protection function circuit (Complementary PUF) 210 may generate a response signal by an operation signal (SE signal). In this case, the calculation circuit 220 includes an output signal PUF_OUT output from the physical copy prevention function circuit 210 and an inversion signal of the output signal (

) To execute a pre-designated digital operation and output the result of the digital operation to a sampling circuit. More specifically, the operation circuit 220 may include an XOR gate, and may output a result of an XOR operation performed on the output signal and an inverted signal of the output signal to the sampling circuit as a result value of the digital operation. .

The reference signal generation circuit 230 may output a reference signal for determining a sampling time of the sampling circuit to the sampling circuit in response to an operation signal. More specifically, the reference signal generation circuit 230 may determine a delayed sampling time of the sampling circuit based on a select signal, and may output a reference signal corresponding to the delayed sampling time to the sampling circuit. . The selection signal may be input from the outside, and in some cases, a method of generating inside a circuit is also possible. In this case, an operation signal delayed by the determined sampling time may be represented as an output signal of the reference signal generation circuit 230. In addition, the signal may be used as a clock signal of the D-flip-flop in the sampling circuit 240 to be described later.

)의 XOR 연산 결과를 기준 신호 생성 회로(230)를 통해 결정된 샘플링 시간에 D-플립플롭이 샘플링하게 된다.The sampling circuit 240 samples the result value of the digital operation according to the reference signal, and when it is determined that the response signal of the physical copy prevention function circuit is determined according to the sampling result, the first signal and the physical copy protection If it is determined before the response signal of the functional circuit is determined, the second signal may be stored. As follows, the output signal PUF_OUT and the inverted signal of the output signal (

The D-flip-flop samples the XOR operation result of) at the sampling time determined through the reference signal generation circuit 230.

More specifically, the sampling circuit 240 includes a D-flip-flop, and may sample a result value of the digital operation by using the reference signal as a clock signal. When it is determined that the response signal of the physical copy prevention function circuit is determined based on the delayed sampling time, the sampling circuit 240 includes a first signal having a high value and a response signal of the physical copy prevention function circuit. If it is determined before the determination, a second signal having a low value may be output as a stability check bit of the physical copy prevention function circuit. Therefore, if the response of the physical copy prevention function circuit 210 is determined relatively faster than the sampling time, the D-flip-flop stores 1. Conversely, if the response of the physically replicable function is determined relatively later than the sampling time, the D-flip-flop stores zero. As described above, the output signal of the D-flip-flop is stored under the name of "stability check bit" and is input to the physical copy protection function circuit so that an unstable response is not used as a key, and only a stable response is used as a key. The modern physically replicable function having a large-scale array format can determine whether the response of a specific bit is stable or unstable using the circuit proposed in this embodiment, and take follow-up measures through this.

3 is a flow chart illustrating the operation of an embodiment of a response instability detection circuit applicable to a physical copy prevention function circuit according to an embodiment.

In step 310, the operation circuit may perform an XOR operation on the output signal of the complementary PUF.

In step 320, the sampling circuit may sample the result of the XOR operation using the flip-flop.

In step 330, the response instability detection circuit may determine whether the response signal is determined based on the sampling time.

When the response signal is determined, the memory stores "1" in the flip-flop in step 341, detects a stable response signal in step 342, and in step 343, the physical copy prevention circuit key the corresponding response signal. Can be used as.

If the response signal is not determined, in step 351 the memory stores "0" in the flip-flop, detects an unstable response signal in step 352, and in step 353, the physical copy prevention circuit returns the corresponding response signal May not be used as a key.

)이 생성되고, 생성된 응답의 XOR 연산(XOR_OUT), 그리고 XOR 연산 결과를 D-플립플롭이 기준 신호를 통해 샘플링하는 과정을 나타내며, 샘플링 시간은 1ns로 설정되었다. 물리적 복제 방지 기능 회로의 응답 신호는 5ns 때 생성이 시작되며, 대략 0.6ns~0.8ns 정도 후에 논리 값 1 또는 0으로 구분되기 시작한다. 응답 생성 시작 때부터 두 응답을 입력으로 한 XOR 연산이 시작되며 연산 결과 출력은 논리 값 0에서 1로 점진적으로 상승한다. 샘플링 시간은 1ns로 설정되었으므로, 6ns 때 D-플립플롭의 클록 신호(도 4의 기준 신호)가 논리 값 0에서 1로 상승한다. D-플립플롭의 샘플링 시간보다 응답 생성에 소요되는 시간이 짧으므로 D-플립플롭은 6ns 때의 XOR 연산 결과 논리 값 1을 저장하며, 이는 안정된 응답이 생성됐음을 의미한다.4 shows a simulation result of an embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response. FIG. 4 shows a simulation result when the response determination time of the physical replication impossible function is relatively fast using an embodiment of the response instability detection circuit proposed in this embodiment. Response of the physically non-replicable function (PUF_OUT,

) Is generated, the XOR operation (XOR_OUT) of the generated response, and the XOR operation result are sampled by the D-flip-flop through the reference signal, and the sampling time is set to 1 ns. The response signal of the physical copy protection function circuit starts to be generated at 5 ns, and after about 0.6 ns to 0.8 ns, it starts to be divided into logical values of 1 or 0. From the start of response generation, XOR operation with two responses as inputs starts, and the output of the operation result gradually rises from 0 to 1. Since the sampling time is set to 1 ns, at 6 ns, the clock signal of the D-flip-flop (the reference signal in Fig. 4) rises from a logic value of 0 to 1. Since the time required to generate the response is shorter than the sampling time of the D-flip-flop, the D-flip-flop stores a logical value of 1 as a result of the XOR operation at 6 ns, which means that a stable response is generated.

)이 생성되고, 생성된 응답의 XOR 연산(XOR_OUT), 그리고 XOR 연산 결과를 D-플립플롭이 기준 신호를 통해 샘플링하는 과정을 나타내며, 샘플링 시간은 1ns로 설정되었다. 물리적 복제 불가능 함수의 응답은 5ns 때 생성이 시작되며, 대략 1.8ns~2ns 정도 후에 논리 값 1 또는 0으로 구분되기 시작한다. 응답 생성 시작 때부터 두 응답을 입력으로 한 XOR 연산이 시작되며 연산 결과 출력은 논리 값 0에서 1로 점진적으로 상승한다. 샘플링 시간은 1ns로 설정되었으므로, 6ns 때 D-플립플롭의 클록 신호(도 5의 기준 신호)가 논리 값 0에서 1로 상승한다. D-플립플롭의 샘플링 시간보다 응답 생성에 소요되는 시간이 기므로 D-플립플롭은 6ns 때의 XOR 연산 결과 논리 값 0을 저장하며, 이는 불안정한 응답이 생성됐음을 의미한다. XOR 연산의 결과는 물리적 복제 불가능 함수의 응답이 정상적으로 생성되었다면 항상 0에서 공급전원 레벨로 올라가게 되지만, 응답의 결정시간에 따라 상대적으로 빠르게 또는 느리게 공급전원 레벨로 올라가게 된다. 이 때, '기준 신호'와 '동작 신호'(도 4과 도 5에서는 생략됨, 5ns 때 SE 신호 0에서 1로 상승)의 시간 차이는 레퍼런스 생성기 블록에 의해 생성된 지연(샘플링 시간)이다.5 shows a simulation result of another embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response. FIG. 5 shows a simulation result when the response determination time of the physical replication impossible function is relatively slow using an embodiment of the response instability detection circuit proposed in this embodiment. Response of the physically non-replicable function (PUF_OUT,

) Is generated, the XOR operation (XOR_OUT) of the generated response, and the XOR operation result are sampled by the D-flip-flop through the reference signal, and the sampling time is set to 1 ns. The response of the physically non-replicable function starts to be generated at 5 ns, and begins to be divided into logical values of 1 or 0 after approximately 1.8 ns to 2 ns. From the start of response generation, XOR operation with two responses as inputs starts, and the output of the operation result gradually rises from 0 to 1. Since the sampling time is set to 1 ns, at 6 ns, the clock signal of the D-flip-flop (the reference signal in Fig. 5) rises from a logic value of 0 to 1. Since the time it takes to generate the response is longer than the sampling time of the D-flip-flop, the D-flip-flop stores a logical value of 0 as a result of the XOR operation at 6 ns, which means that an unstable response is generated. The result of the XOR operation always rises from 0 to the supply power level if the response of the physically replicable function is normally generated, but rises to the supply power level relatively quickly or slowly depending on the decision time of the response. At this time, the time difference between the'reference signal' and the'operation signal' (omitted in FIGS. 4 and 5, and the SE signal rises from 0 to 1 at 5 ns) is a delay (sampling time) generated by the reference generator block.

The response instability detection technology using the response decision time applicable to the physically replicable function with complementary responses in this embodiment requires security along with the physically replicable function, but it is difficult to apply a security system using software. Can be used in the field.

Specifically, it is possible to efficiently improve security by applying it to a low-power micro-internet (IoT) device that is difficult to utilize a microprocessor in terms of efficiency. In addition, it can be utilized as a low cost, low power, high efficiency random number generator and an identity authentication system.

The embodiments described above may be implemented as a hardware component, a software component, and/or a combination of a hardware component and a software component. For example, the devices, methods, and components described in the embodiments include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate (FPGA). array), programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions, such as one or more general purpose computers or special purpose computers. The processing device may execute an operating system (OS) and one or more software applications executed on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of software. For the convenience of understanding, although it is sometimes described that one processing device is used, one of ordinary skill in the art, the processing device is a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that it may include. For example, the processing device may include a plurality of processors or one processor and one controller. In addition, other processing configurations are possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of these, configuring the processing unit to behave as desired or processed independently or collectively. You can command the device. Software and/or data may be interpreted by a processing device or to provide instructions or data to a processing device, of any type of machine, component, physical device, virtual equipment, computer storage medium or device. , Or may be permanently or temporarily embodyed in a transmitted signal wave. The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like alone or in combination. The program instructions recorded on the computer-readable medium may be specially designed and configured for the embodiment, or may be known and usable to those skilled in the computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -A hardware device specially configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those produced by a compiler but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

As described above, although the embodiments have been described by the limited drawings, a person of ordinary skill in the art can apply various technical modifications and variations based on the above. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Claims (5)

In a semiconductor chip that detects the unstability of a response signal generated by a physically unclonable function (PUF) circuit having a complementary response,
An operation circuit configured to perform an XOR operation using an output signal output by the physical copy prevention function circuit in response to an operation signal and an inverted signal of the output signal, and output a result value of the XOR operation;
A reference signal generation circuit for determining a sampling time in response to the operation signal and outputting a reference signal corresponding to the sampling time; And
The result of the XOR operation is sampled according to the reference signal, and the response determination time of the response signal of the physical copy preventing function circuit is compared based on the sampling time. When it is determined that the response signal is determined, a sampling circuit that stores the first signal and the second signal when it is determined that the response signal of the physical copy preventing function circuit is determined
Including,
The time for determining the response of the response signal of the physical copy prevention function circuit is determined based on a time when a value of the output signal and an inverted signal of the output signal are distinguished.
The method of claim 1,
The calculation circuit,
And an XOR gate configured to perform an XOR operation on the output signal and an inverted signal of the output signal, and output a result of the XOR operation to the sampling circuit.
delete The method of claim 2,
The sampling circuit,
A semiconductor chip comprising a D-flip-flop and sampling a result value of the XOR operation by using the reference signal as a clock signal.
The method of claim 4,
The sampling circuit,
When it is determined that the response signal of the physical copy protection function circuit is determined based on the sampling time, when it is determined before the first signal having a high value and the response signal of the physical copy protection function circuit are determined A semiconductor chip that outputs a second signal having a low value as a stability check bit of the physical copy prevention function circuit.

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