KR102192845B1 - Response unstability detection apparatus and method based on response multiple comparison for physical unclonable function - Google Patents

Abstract

Related to the response instability detection circuit. According to an embodiment, a physical unclonable function (PUF) circuit for generating a response signal corresponding to a challenge signal; A memory for storing from the first response signal PUF_OUT1 output at a first time point from the physical copy prevention function circuit to an N-1th response signal PUF_OUTN-1 output at a time N-1; Comparison of comparing any one of the plurality of response signals stored in the memory with the Nth response signal PUF_OUTN output at the current Nth time point, and determining whether to perform additional comparison using other output signals according to the comparison result Circuitry.

Description

Response instability detection device and method through response multiple comparison applicable to physical replication impossible functions {RESPONSE UNSTABILITY DETECTION APPARATUS AND METHOD BASED ON RESPONSE MULTIPLE COMPARISON FOR PHYSICAL UNCLONABLE FUNCTION}

The present invention relates to a security technology using hardware, and more particularly, to a response instability detection circuit applicable to a physically replicable function system using a semiconductor.

A physically non-replicable function (PUF) system based on a CMOS process can quickly and randomly generate a unique value (ID or Response) by a specific challenge. Randomly generated unique values are generated by process mismatch even if a chip with the same structure (same layout) is produced when a chip that cannot be physically duplicated using CMOS is made.

It can be expressed as a probabilistic property called Reproducibility or Stability that a function that cannot be physically replicated has the same physical value by the same input regardless of changes in the external environment. It is one of the important performance indicators.

However, the conventional physical replication impossible function has poor performance in terms of reproducibility due to external environment (temperature change, supply voltage change, malicious attack, etc.). Therefore, it is required to develop a function that cannot be physically replicated to complement this.

Korean Patent Publication No. 10-2016-0048114 (published on May 3, 2016) proposes a memory-based PUF. The invention relates to a memory-based PUF for storage in intrusion and duplication attacks.

An object according to an embodiment of the present invention is to solve a reproducibility error caused by an external environment (temperature change, supply voltage change, malicious attack, etc.) of the existing physical replication impossible function.

Another object according to an embodiment of the present invention is to detect a cell generating an unstable eigenvalue by proposing a response instability detection circuit in order to solve a reproducibility error.

According to an embodiment, a physical unclonable function (PUF) circuit for generating a response signal corresponding to a challenge signal; A memory for storing from the first response signal PUF_OUT1 output at a first time point from the physical copy prevention function circuit to an N-1th response signal PUF_OUTN-1 output at a time N-1; Comparison of comparing any one of the plurality of response signals stored in the memory with the Nth response signal PUF_OUTN output at the current Nth time point, and determining whether to perform additional comparison using other response signals according to the comparison result A response instability detection circuit comprising a circuit is disclosed.

According to another embodiment of the present disclosure, the comparison circuit may also include a response instability detection circuit that sequentially compares the first response signal to the N-1th response signal with the Nth response signal.

According to another embodiment, the memory stores the comparison result of the comparison circuit, and when the past response and the current response do not match, a stability check bit in the physical copy protection function circuit It may be a response instability detection circuit that transmits.

According to another embodiment, the comparison circuit compares a plurality of response signals stored in the memory and the N-th response signal for a predetermined number of times, and a comparison result is obtained from the plurality of response signals stored in the memory and the A response instability detection circuit using the Nth response signal as a key signal of the physical copy prevention function circuit in the same case as for the N response signal is also provided.

According to an embodiment, the comparison circuit includes a 2-bit counter that counts the number of falling edges of the enable signal and outputs a signal when the number of falling edges becomes 2; Also disclosed is a response instability detection circuit further comprising a NOR gate for receiving the enable signal, the reset signal, and the output signal of the 2-bit counter and outputting a comparison sampling clock signal XOR_SAMPLING_CLK.

According to an embodiment, when the eigenvalue of the function that cannot be physically replicated is generated, the response stability information of each cell through response multiple comparison is generated together, so an error in the chip through an additional circuit depending on the purpose of the designer or the use of the security chip. Or by transmitting the instability information to the outside of the chip together with the intrinsic value of the physically replicable function, the error can be resolved through post-processing.

The response instability detection method through response multiple comparison applicable to a physically replicable function according to an embodiment requires security along with a physically replicable function, but can be used in various fields where it is difficult to apply a security system using software.

Specifically, it is possible to efficiently improve security by applying it to a low-power micro-internet (IoT) device that is difficult to utilize a microprocessor for efficiency. In addition, it can be used for low-cost, low-power, high-efficiency random number generators, and identity authentication systems.

The objects and effects of the present invention are not limited to the above-described contents as they are exemplary descriptions, and the contents of the present invention are not limited by the above objects and effects and are not interpreted.

1 shows a single cell of a physically non-replicable function with a conventional complementary response according to an embodiment.
2 shows a single cell of a conventional delay-based physical replication impossible function according to an embodiment.
3 is a block diagram showing a system of a response instability detection circuit applicable to a physical replication impossibility function according to an embodiment.
4 illustrates a configuration and operation of a response instability detection circuit applicable to a physically replicable function according to an embodiment.
5 shows a simulation result of instability detection of a response instability detection circuit applicable to a physically replicable function according to an embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the rights is not limited or limited by these embodiments. The same reference numerals in each drawing indicate the same members.

The terms used in the description below have been selected as general and universal in the related technology field, but there may be other terms depending on the development and/or change of technology, customs, preferences of technicians, and the like. Therefore, terms used in the following description should not be understood as limiting the technical idea, but should be understood as exemplary terms for describing embodiments.

In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, detailed meanings will be described in the corresponding description. Therefore, terms used in the following description should be understood based on the meaning of the term and the contents throughout the specification, not just the name of the term.

1 is a diagram illustrating a single cell configuration of a physically replicable function having a complementary response according to the related art according to an embodiment.

When the supply power (VDD) is applied, when a signal of the supply power level is input to the Sense Enable (SE) node, the function that cannot be physically replicated indicates the operation instability characteristic of the power-up state of the digital memory. To start generating responses or unique values.

The generated response is selectively transmitted to the PUF_OUT and PUF_OUT_B buses through a word line operation signal (Word Line, WL). At this time, the response transmitted to the PUF_OUT bus and the response transmitted to the PUF_OUT_B bus have a complement relationship. The determined response (1 or 0) can be determined by various external factors, including process discrepancies.

IN1 and IN2 are bias input terminals, and the operating characteristics of the physically non-replicable function may be changed through the voltages of the two nodes. For example, but not limited to, a voltage of the VDD level may be applied to both nodes.

2 shows a single cell of a conventional delay-based physical replication impossible function according to an embodiment.

In the method of generating a delay-based physically non-replicable function according to an embodiment, a digital race race is formed by creating two identical paths within one chip, and an arbiter circuit at the end First, it is created by determining whether it has arrived at the destination point.

If the two paths are designed identically, the winner of the race game will be determined by the discrepancy in the process that occurs during chip manufacturing, so this can be used as a function that cannot be physically duplicated.

An embodiment in which the above-described concept is implemented as a circuit is shown in FIG. 2. After applying the supply power (VDD) to the circuit, when the rising edge signal is input to the enable node, the two multiplexers (MUX) located in the first stage are the challenge signal (Challenge X[0]). Depending on the logic state, an enable signal connected to input nodes 0 and 1 is selectively output and transmitted to the next stage.

Since the outputs of the two multiplexers (MUX) in each stage are connected to the input nodes 0 or 1 of the two multiplexers in the next stage, the challenge signals (Challenge X[0], X[1], X[2], …, delay between the time when the enable signal of the rising edge arrives at the D node of the Arbiter consisting of the D-flip-flop (DFF) located at the last stage according to X[255]) and the clock node Is produced. The time delay is determined by the challenge signal and the process discrepancy or natural law and cannot be predicted.

As the number of stages of the multiplexer increases, the bit-width of the challenge signal increases, and the time delay increases. In addition, if the physically replicable function system of FIG. 2 is expanded in parallel, the bit width of the response signal may increase.

Therefore, when designing a function that cannot be physically replicated, design a function that cannot be physically replicated having a myriad of challenge signals and response signals or challenge-response pairs within the allowed resources. can do.

In the case of a delay-based physically non-replicable function, the operation speed is slow because it is based on a time delay, but because it has multiple Challenge-Response Pairs, it can be used in an authentication or encryption system for information protection.

As a result, a method for reducing an error in the reproducibility probability of a physically non-replicable function that can be caused by a process discrepancy, a fluctuation in operating temperature, or a noise included in a supply power is described. Specifically, it is a technique to detect unstable responses through multiple comparisons of responses.

3 is a block diagram illustrating a response instability detection circuit 300 applicable to a physical replication impossibility function according to an embodiment. The response instability detection circuit 300 according to an embodiment may include a memory 320 and a comparison circuit 330.

When a physical unclonable function 310 generates a response PUF_OUT, the memory 320 stores the generated response PUF_OUT. The comparison circuit 330 stores the current response (PUF_OUT _t ) of the physically replicable function 310 in the memory 320 and stores the past responses PUF_OUT _{t -1} , PUF_OUT _{t -2} , PUF_OUT _{t -3} , ..., PUF_OUT _tn ) is compared sequentially.

The comparison result is transmitted back to the memory 320 and stored. The memory 320 determines whether to perform the next comparison based on the received comparison result. Specifically, when the past response and the current response do not match, the next comparison is not performed, and a stability check bit is transmitted to the physical replication impossible function 310.

Unstable responses are not used as keys, only stable responses are used as keys. If there is no difference between the past responses ((PUF_OUT _{t -1} , PUF_OUT _{t -2} , PUF_OUT _t-3 , …, PUF_OUT _{t -n} )) and the current response (PUF_OUT _t ) by performing comparison as many times as a preset number of times Since it is a stable response, the response in this case can be used as a key.

In FIG. 4, a specific configuration and operation of the response instability detection circuit 400 applicable to the physically replicable function according to an embodiment will be described as an example.

신호를 이용해 전체 회로(400)를 초기화한다.First of all, power is supplied to the response instability detection circuit 400,

The entire circuit 400 is initialized using the signal.

로 나타난다. PUF_OUT과

는 보수 관계에 있기 때문에 XOR 연산을 수행하면, 상승 에지의 신호가 생성되며 상기 상승 에지의 신호는 디멀티플렉서(1 to 2 DE-MUX)의 입력 신호(DEMUX_EDGE)로 입력된다.Next, a physically replicable function (Complementary PUF) 410 having a complementary response generates a response by rising of the enable signal SE. The response is complementary, so PUF_OUT and

Appears as With PUF_OUT

Since is in the complement relationship, when XOR operation is performed, a rising edge signal is generated, and the rising edge signal is input as an input signal DEMUX_EDGE of the demultiplexer (1 to 2 DE-MUX).

At the same time, the divider (1/2 Divider) receives the enable signal (SE) as an input, and divides the enable signal (SE) by the division ratio 2. The divided enable signal is applied to the selection signal DMX_SEL of the demultiplexer 1 to 2 DE-MUX.

As a result, whenever the enable signal SE rises, one of the two D Flip-Flops connected to the demultiplexer is sequentially selected (DMX_SEL) by the demultiplexer. The selected D flip-flop among the two D flip-flops receives the rising edge signal DEMUX_EDGE as a clock and samples PUF_OUT. The sampled PUF_OUT evaluates the stability of the response by the signal (XOR_OUT) output through the connected XOR gate.

When the logic levels of the two signals are different, the XOR gate outputs a high level signal, so that the response stability of the PUF_OUT sampled through the XOR gate can be evaluated.

However, since the stability of the response should not be determined until both D flip-flops have sampled a specific PUF_OUT, some configurations for this are further included.

신호가 High 레벨일 때에만 상기 응답의 안정성을 판단할 수 있도록 NOR 게이트와 2비트 카운터(2-bit Counter/Comparator)를 더 포함한다.When the enable signal SE is at a low level, when the falling edge of the enable signal is two or more times, and

It further includes a NOR gate and a 2-bit counter (2-bit counter/Comparator) to determine the stability of the response only when the signal is at a high level.

The 2-bit counter counts and compares the number of falling edges of the enable signal, and stops counting when the number of falling edges is 2, and a low level signal CNT_OVERFLOW is output.

신호와 함께 NOR 게이트에 입력한다. 이 경우 상기 조건들에 부합하는 경우에만 NOR 게이트의 출력(XOR_SAMPLING_CLK)으로 상승 에지의 신호가 생성된다.An enable signal of the output low level signal (CNT_OVERFLOW), and

It is input to the NOR gate with the signal. In this case, a rising edge signal is generated as the output of the NOR gate (XOR_SAMPLING_CLK) only when the above conditions are met.

As a result, the response instability determination result (XOR_OUT) can be sampled only when the above conditions are satisfied by applying the output (XOR_SAMPLING_CLK) signal of the NOR gate to the clock of the D flip-flop of the last stage.

신호를 이용하여 전체 회로(400)를 초기화하면, 위 설명한 과정을 처음부터 다시 반복한다. 이를 통해 인에이블 신호,

신호 및 상호 보완적인 응답을 갖는 물리적 복제 불가능 함수의 응답 신호(PUF_OUT,

)만을 이용한 응답 안정성 판단이 가능하다. 즉, 추가적인 제어 신호 없이 응답의 다중 비교를 통한 물리적 복제 불가능 함수의 안정성을 판단할 수 있다. 또한, 회로가 초기화되기 전까지는 연속해서 응답을 비교하므로, 비교 횟수에도 제약이 없다.remind

When the entire circuit 400 is initialized using a signal, the above-described process is repeated from the beginning. This allows the enable signal,

Signal and the response signal of a physically non-replicable function with a complementary response (PUF_OUT,

), it is possible to judge response stability. That is, it is possible to determine the stability of a function that cannot be physically replicated through multiple comparisons of responses without an additional control signal. In addition, the response is continuously compared until the circuit is initialized, so there is no limit to the number of comparisons.

5 shows a simulation result of instability detection of a response instability detection circuit applicable to a physically replicable function according to an embodiment. Specifically, in FIG. 5, a simulation result of the response instability detection circuit illustrated in FIG. 4 is shown as a graph.

Whenever the response (PUF_OUT) of the physical replication impossible function is generated by the rise of the enable signal (SE), if the logic level is different from the response (PUF_OUT) generated in the previous trial, the stability check bit (Stability Check) as shown in FIG. Bit) signal indicates high level. That is, a stability check bit is generated at a point in time when the response (PUF_OUT) of the physical replication impossible function changes.

In FIG. 5, for example, a stability check bit is generated when the response of the physically replicable function changes from "1" to "0".

The modern physically replicable function having a large array format can determine whether a response of a specific bit is stable or unstable using a response instability detection circuit according to an embodiment.

The apparatus described above may be implemented as a hardware component, a software component, and/or a combination of a hardware component and a software component. For example, the devices and components described in the embodiments include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It can be implemented using one or more general purpose computers or special purpose computers, such as a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications executed on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of software. For the convenience of understanding, although it is sometimes described that one processing device is used, one of ordinary skill in the art, the processing device is a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that it may include. For example, the processing device may include a plurality of processors or one processor and one controller. In addition, other processing configurations are possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of these, configuring the processing unit to behave as desired or processed independently or collectively. You can command the device. Software and/or data may be interpreted by a processing device or to provide instructions or data to a processing device, of any type of machine, component, physical device, virtual equipment, computer storage medium or device. , Or may be permanently or temporarily embodyed in a transmitted signal wave. The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -A hardware device specially configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of the program instructions include not only machine language codes such as those produced by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

Although the embodiments have been described by the limited drawings, various modifications and variations are possible from the above description to those of ordinary skill in the art. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and claims and equivalents fall within the scope of the claims to be described later.

Claims (5)

A response (PUF_OUT) and a response (

) To create a physically replicable function (Complementary PUF, 410);
The response (PUF_OUT) and the response (

), an input signal (DEMUX_EDGE) generated by performing an XOR operation and a selection signal (DMX_SEL) from a divider (1/2 Divider) are applied, and one of the two first D flip-flops is applied. A demultiplexer (1 to 2 DE-MUX) for sequentially selecting any one; And
As the response (PUF_OUT) is sampled from each of the two first D flip-flops, the response (PUF_OUT) is generated using a signal (XOR_OUT) generated by performing an XOR operation on the two sampled responses. The second D flip-flop to evaluate stability
Including,
The second D flip-flop,
1) When the enable signal (SE) applied to the n-bit counter is at a low level, 2) When the falling edge of the enable signal (SE) counted by the n-bit counter is 2 or more times, and 3) is applied

To evaluate the stability of the response (PUF_OUT) when the signal is at high level
Response instability detection circuit. The method of claim 1,
A physical unclonable function (PUF) circuit 310 for generating a response signal corresponding to a challenge signal;
A memory 320 for storing from the first response signal PUF_OUT1 output at a first time point from the physical copy protection circuit 310 to an N-1th response signal PUF_OUTN-1 output at a time N-1 ); And
Comparing any one of the plurality of response signals stored in the memory 320 with the N-th response signal PUF_OUTN output at the current N-th time point, and determining whether or not to perform additional comparison using another response signal according to the comparison result Determining comparison circuit 330
Including more,
The memory 320,
Stores the comparison result of the comparison circuit 330, and transmits a stability check bit to the physical copy prevention function circuit 310 when the past response and the current response do not match.
Response instability detection circuit. delete delete The method of claim 2,
The comparison circuit 330,
A plurality of response signals stored in the memory 320 and the N-th response signal are compared for a predetermined number of times, and a comparison result is obtained with respect to the plurality of response signals and the N-th response signal stored in the memory 320 In the same case, the N-th response signal is used as a key signal of the physical copy prevention function circuit 310
Response instability detection circuit.

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