KR20200028661A - Response unstability detection apparatus and method based on response decision time for complementary physical unclonable function - Google Patents

Abstract

Provided is a semiconductor chip for detecting unstability of a response signal generated by a physically unclonable function (PUF) circuit. The semiconductor chip may comprise: an operation circuit configured to execute a predetermined digital operation by using an output signal outputted from the PUF circuit and an inverted signal of the output signal and output a result value of the digital operation to a sampling circuit; a reference signal generation circuit configured to output a reference signal for determining a sampling time of the sampling circuit to the sampling circuit in response to an operation signal; and a sampling circuit configured to sample the result value of the digital operation according to the reference signal, store a first signal when it is determined that a response signal of the PUF circuit has been determined according to a sampling result and store a second signal when it is determined that the response signal of the PUF circuit has not been determined yet according to a sampling result.

Description

Apparatus and method for detecting instability of a response signal using a response decision time applicable to a physical replication prevention function circuit having a complementary response {RESPONSE UNSTABILITY DETECTION APPARATUS AND METHOD BASED ON RESPONSE DECISION TIME FOR COMPLEMENTARY PHYSICAL UNCLONABLE FUNCTION}

The following embodiments relate to an apparatus and method for sensing instability of a response signal. More specifically, it relates to a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response.

A physical unclonable function (PUF) system based on a complementary metal-oxide semiconductor (CMOS) process, which has the advantages of high integration and low cost, has a unique value (ID or Response) by a specific challenge signal. ) Can be generated randomly and quickly. This random eigenvalue is generated by process mismatch even when a semiconductor chip including a physical copy protection function circuit using CMOS is produced, even if a semiconductor chip having the same structure (same layout) is produced. Physical copy protection function The circuit has the same physical value by the same input regardless of changes in the external environment. It can be represented by the probability property of reproducibility or stability, and this probability property is a physical copy protection function It is one of the important performance indicators of the circuit. However, the existing physical copy protection function circuit has a problem in that it has poor performance in terms of reproducibility due to an external environment (temperature change, supply voltage change, malicious attack, etc.).

Republic of Korea Patent Publication No. 10-2018-0050276 is an invention related to a silicon integrated circuit for testing the reliability of the inherent values provided by the PUF circuit. Specifically, the target patent includes a configuration including an abnormal response and an inconsistent response based on a predefined response distribution to detect an error in the PUF circuit.

According to one side, a semiconductor chip is provided that senses the instability of a response signal generated by a physically unclonable function (PUF) circuit. The semiconductor chip performs a predetermined digital operation using an output signal output from the physical copy protection function circuit and an inverted signal of the output signal, an operation circuit outputting the result of the digital operation to a sampling circuit, an operation signal In response, a reference signal generation circuit for outputting a reference signal for determining a sampling time of the sampling circuit to the sampling circuit and a result value of the digital operation are sampled according to the reference signal, and the physical When it is determined that the response signal of the copy protection function circuit is determined, it may include a sampling circuit that stores the first signal and the second signal when it is determined that the response signal of the physical copy protection function circuit is determined.

According to an embodiment, the operation circuit includes an XOR gate, and outputs the result of the XOR operation performed on the output signal and the inversion signal of the output signal as the result value of the digital operation to the sampling circuit. .

According to another embodiment, the reference signal generation circuit determines a delayed sampling time of the sampling circuit based on an input select signal, and outputs a reference signal corresponding to the delayed sampling time to the sampling circuit can do.

According to another embodiment, the sampling circuit includes a D-flip-flop, and the result of the digital operation can be sampled using the reference signal as a clock signal.

According to another embodiment, when the sampling circuit determines that the response signal of the physical copy protection function circuit is determined based on the delayed sampling time, the first signal having a high value and the physical copy protection When it is determined that the response signal of the functional circuit is determined, a second signal having a low value may be output as the stability check bit of the physical copy protection function circuit.

1 is a block diagram of a response instability detection circuit applicable to a physical copy protection function circuit according to an embodiment.
2 is a block diagram illustrating the configuration and operation of a response instability detection circuit applicable to a physical copy protection function circuit according to another embodiment.
3 is a flowchart illustrating the operation of an embodiment of a response instability detection circuit applicable to a physical copy protection function circuit according to an embodiment.
4 shows simulation results of an embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response.
5 shows simulation results of another embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only, and may be implemented in various forms. Accordingly, the embodiments are not limited to a specific disclosure form, and the scope of the present specification includes modifications, equivalents, or substitutes included in the technical spirit.

The terms first or second may be used to describe various components, but these terms should be interpreted only for the purpose of distinguishing one component from other components. For example, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When an element is said to be "connected" to another element, it should be understood that other elements may be present, either directly connected to or connected to the other element.

Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "include" or "have" are intended to designate the presence of a feature, number, step, action, component, part, or combination thereof as described, one or more other features or numbers, It should be understood that the existence or addition possibilities of steps, actions, components, parts or combinations thereof are not excluded in advance.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art. Terms such as those defined in a commonly used dictionary should be interpreted as having meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined herein. Does not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In describing with reference to the accompanying drawings, the same reference numerals are assigned to the same components regardless of reference numerals, and duplicate descriptions thereof will be omitted.

The embodiments to be described below can solve the problem that the existing physical replication impossible function has a reproducibility error due to an external environment (temperature change, supply voltage change, malicious attack, etc.). When a unique value of a non-replicable physical function with a complementary response is generated, response stability information of each cell determined according to a threshold (sampling time) specified by a system designer is generated together, so it is suitable for the purpose of the designer or the purpose of the security chip. Therefore, the error can be solved through an additional circuit, or the post-processing error can be solved by sending the instability information to the outside of the chip along with the unique value of the non-replicable physical function.

1 is a block diagram of a response instability detection circuit applicable to a physical copy protection function circuit according to an embodiment. Referring to FIG. 1, a physical replication protection function circuit (Complementary PUF) 110 generating a complementary response may generate a complementary response signal PUF_OUT. In this case, the response instability detection circuit 100 may include a comparison circuit 120 and a memory 130. The comparison circuit 120 may compare a response signal and a reference signal (response decision threshold time). More specifically, the comparison circuit 120 compares up to a time at which a response signal is generated and determined, and determines whether the response is a stable response or an unstable response according to the response determination time and stores response stability information in the memory 130 do.

The memory 130 transmits response stability information as a stability check bit, and allows the physical copy protection function circuit to use only a stable response as a key.

)를 이용하여 미리 지정된 디지털 연산을 실행하고, 디지털 연산의 결과값을 샘플링 회로로 출력할 수 있다. 보다 구체적으로, 연산 회로(220)는 XOR 게이트를 포함하고, 상기 출력 신호와 상기 출력 신호의 반전 신호에 대해 수행된 XOR 연산의 결과를 상기 디지털 연산의 결과값으로서 상기 샘플링 회로로 출력할 수 있다.2 is a block diagram illustrating the configuration and operation of a response instability detection circuit applicable to a physical copy protection function circuit according to another embodiment. Referring to FIG. 2, the response instability detection circuit 200 may include an operation circuit 220, a reference signal generation circuit 230, and a sampling circuit 240. The physical copy protection function circuit (Complementary PUF) 210 may generate a response signal by an operation signal (SE signal). In this case, the operation circuit 220 includes an output signal (PUF_OUT) output from the physical copy protection function circuit 210 and an inverted signal of the output signal (

) To perform a predetermined digital operation and output the result of the digital operation to the sampling circuit. More specifically, the operation circuit 220 includes an XOR gate, and outputs the result of the XOR operation performed on the output signal and the inverted signal of the output signal as the result value of the digital operation to the sampling circuit. .

The reference signal generation circuit 230 may output a reference signal for determining the sampling time of the sampling circuit to the sampling circuit in response to the operation signal. More specifically, the reference signal generation circuit 230 may determine a delayed sampling time of the sampling circuit based on a select signal, and output a reference signal corresponding to the delayed sampling time to the sampling circuit. . The selection signal may be input from the outside, and in some cases, a method generated inside the circuit is also possible. In this case, the operation signal delayed by the determined sampling time may be represented as the output signal of the reference signal generation circuit 230. In addition, the signal can be used as a clock signal of the D-flip-flop in the sampling circuit 240 to be described later.

)의 XOR 연산 결과를 기준 신호 생성 회로(230)를 통해 결정된 샘플링 시간에 D-플립플롭이 샘플링하게 된다.The sampling circuit 240 samples the result of the digital operation according to the reference signal, and when it is determined that the response signal of the physical copy protection function circuit is determined according to the sampling result, the first signal and the physical copy protection If it is determined that the response signal of the functional circuit is not determined, the second signal may be stored. As follows, the output signal (PUF_OUT) and the inverted signal of the output signal (

), The D-flip-flop is sampled at the sampling time determined by the reference signal generation circuit 230.

More specifically, the sampling circuit 240 may include a D-flip-flop, and sample the result of the digital operation using the reference signal as a clock signal. When it is determined that the response signal of the physical copy protection function circuit is determined based on the delayed sampling time, the sampling circuit 240 includes a first signal having a high value and a response signal of the physical copy protection function circuit. If it is determined before determination, a second signal having a low value may be output as a stability check bit of the physical copy protection function circuit. Therefore, if the response of the physical copy protection function circuit 210 is determined relatively faster than the sampling time, the D-flip-flop stores 1. Conversely, if the response of the non-replicable function is determined relatively later than the sampling time, the D-flip-flop stores 0. As described above, the output signal of the D-flip-flop is stored under the name " stability check bit ", and is input to the physical copy protection function circuit so that an unstable response is not used as a key, but only a stable response is used as a key. A modern physical non-replicable function having a large-scale array format can determine whether a response of a specific bit is stable or unstable by utilizing the circuit proposed in this embodiment, and follow-up actions can be taken.

3 is a flowchart illustrating the operation of an embodiment of a response instability detection circuit applicable to a physical copy protection function circuit according to an embodiment.

In step 310, the operation circuit may perform an XOR operation on the output signal of the complementary PUF.

In step 320, the sampling circuit may sample the result of the XOR operation using the flip-flop.

In step 330, the response instability detection circuit may determine whether a response signal has been determined based on the sampling time.

If a response signal is determined, in step 341, the memory stores a "1" in the flip-flop, in step 342 a stable response signal is detected, and in step 343 the physical copy protection circuitry keys the corresponding response signal. Can be used as

If the response signal has not been determined, in step 351, the memory stores “0” in the flip-flop, in step 352 the unstable response signal is detected, and in step 353 the physical copy protection circuit determines the corresponding response signal. Can be used as a key.

)이 생성되고, 생성된 응답의 XOR 연산(XOR_OUT), 그리고 XOR 연산 결과를 D-플립플롭이 기준 신호를 통해 샘플링하는 과정을 나타내며, 샘플링 시간은 1ns로 설정되었다. 물리적 복제 방지 기능 회로의 응답 신호는 5ns 때 생성이 시작되며, 대략 0.6ns~0.8ns 정도 후에 논리 값 1 또는 0으로 구분되기 시작한다. 응답 생성 시작 때부터 두 응답을 입력으로 한 XOR 연산이 시작되며 연산 결과 출력은 논리 값 0에서 1로 점진적으로 상승한다. 샘플링 시간은 1ns로 설정되었으므로, 6ns 때 D-플립플롭의 클록 신호(도 4의 기준 신호)가 논리 값 0에서 1로 상승한다. D-플립플롭의 샘플링 시간보다 응답 생성에 소요되는 시간이 짧으므로 D-플립플롭은 6ns 때의 XOR 연산 결과 논리 값 1을 저장하며, 이는 안정된 응답이 생성됐음을 의미한다.4 shows simulation results of an embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response. 4 shows a simulation result when a response determination time of a physical non-replicable function is relatively fast, using an embodiment of the response instability detection circuit proposed in this embodiment. Response of non-cloneable function (PUF_OUT,

) Is generated, XOR operation of the generated response (XOR_OUT), and the process of sampling the result of XOR operation by the D-flip-flop through the reference signal, and the sampling time was set to 1 ns. The response signal of the physical copy protection function circuit starts to be generated at 5 ns, and after about 0.6 ns to 0.8 ns, begins to be divided into logical values of 1 or 0. From the beginning of response generation, XOR operation with two responses as input starts, and the output of the operation gradually increases from logical value 0 to 1. Since the sampling time is set to 1 ns, the clock signal of the D-flip-flop (reference signal in FIG. 4) rises from logic value 0 to 1 at 6 ns. Since the time required to generate a response is shorter than the sampling time of the D-flip-flop, the D-flip-flop stores the logical value 1 as a result of the XOR operation at 6 ns, which means that a stable response has been generated.

)이 생성되고, 생성된 응답의 XOR 연산(XOR_OUT), 그리고 XOR 연산 결과를 D-플립플롭이 기준 신호를 통해 샘플링하는 과정을 나타내며, 샘플링 시간은 1ns로 설정되었다. 물리적 복제 불가능 함수의 응답은 5ns 때 생성이 시작되며, 대략 1.8ns~2ns 정도 후에 논리 값 1 또는 0으로 구분되기 시작한다. 응답 생성 시작 때부터 두 응답을 입력으로 한 XOR 연산이 시작되며 연산 결과 출력은 논리 값 0에서 1로 점진적으로 상승한다. 샘플링 시간은 1ns로 설정되었으므로, 6ns 때 D-플립플롭의 클록 신호(도 5의 기준 신호)가 논리 값 0에서 1로 상승한다. D-플립플롭의 샘플링 시간보다 응답 생성에 소요되는 시간이 기므로 D-플립플롭은 6ns 때의 XOR 연산 결과 논리 값 0을 저장하며, 이는 불안정한 응답이 생성됐음을 의미한다. XOR 연산의 결과는 물리적 복제 불가능 함수의 응답이 정상적으로 생성되었다면 항상 0에서 공급전원 레벨로 올라가게 되지만, 응답의 결정시간에 따라 상대적으로 빠르게 또는 느리게 공급전원 레벨로 올라가게 된다. 이 때, '기준 신호'와 '동작 신호'(도 4과 도 5에서는 생략됨, 5ns 때 SE 신호 0에서 1로 상승)의 시간 차이는 레퍼런스 생성기 블록에 의해 생성된 지연(샘플링 시간)이다.5 shows simulation results of another embodiment of a response instability detection circuit applicable to a physical copy protection function circuit having a complementary response. 5 shows a simulation result when a response determination time of a physical non-replicable function is relatively slow, using an embodiment of a response instability detection circuit proposed in this embodiment. Response of non-cloneable function (PUF_OUT,

) Is generated, XOR operation of the generated response (XOR_OUT), and the process of sampling the result of XOR operation by the D-flip-flop through the reference signal, and the sampling time was set to 1 ns. The response of the non-replicable function starts to be generated at 5 ns, and after about 1.8 ns to 2 ns, it starts to be classified as a logical value of 1 or 0. From the beginning of response generation, XOR operation with two responses as input starts, and the output of the operation gradually increases from logical value 0 to 1. Since the sampling time is set to 1 ns, the clock signal of the D-flip-flop (reference signal in FIG. 5) rises from logic value 0 to 1 at 6 ns. Since it takes longer to generate a response than the sampling time of the D-flip-flop, the D-flip-flop stores the logical value 0 as a result of the XOR operation at 6 ns, which means that an unstable response has been generated. As a result of the XOR operation, if the response of the non-replicable function is normally generated, it will always go up from 0 to the supply power level, but depending on the response decision time, it will go up to the supply power level relatively quickly or slowly. At this time, the time difference between the 'reference signal' and the 'operation signal' (omitted in FIGS. 4 and 5, rising from SE signal 0 to 1 at 5 ns) is the delay (sampling time) generated by the reference generator block.

The response instability detection technology using the response decision time applicable to the physical non-replicable function having a complementary response proposed in this embodiment requires security with the physical non-replicable function, but it is difficult to apply the security system using software. Can be used in the field.

 Specifically, it is possible to efficiently improve security by applying it to a low-power ultra-small Internet of Things (IoT) device that is difficult to utilize a microprocessor for efficiency. In addition, it can be used as a low cost, low power, high efficiency random number generator and an identity authentication system.

The embodiments described above may be implemented with hardware components, software components, and / or combinations of hardware components and software components. For example, the devices, methods, and components described in the embodiments include, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors (micro signal processors), microcomputers, and field programmable gates (FPGAs). Arrays, programmable logic units (PLUs), microprocessors, or any other device capable of executing and responding to instructions can be implemented using one or more general purpose computers or special purpose computers. The processing device may run an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, a processing device may be described as one being used, but a person having ordinary skill in the art, the processing device may include a plurality of processing elements and / or a plurality of types of processing elements. It can be seen that may include. For example, the processing device may include a plurality of processors or a processor and a controller. In addition, other processing configurations, such as parallel processors, are possible.

The software may include a computer program, code, instruction, or a combination of one or more of these, and configure the processing device to operate as desired, or process independently or collectively You can command the device. Software and / or data may be interpreted by a processing device, or to provide instructions or data to a processing device, of any type of machine, component, physical device, virtual equipment, computer storage medium or device. , Or may be permanently or temporarily embodied in the transmitted signal wave. The software may be distributed on networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. Computer-readable media may include program instructions, data files, data structures, or the like alone or in combination. The program instructions recorded on the computer-readable medium may be specially designed and configured for the embodiments, or may be known and usable by those skilled in the computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs, DVDs, and magnetic media such as floptical disks. -Hardware devices specially configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language code that can be executed by a computer using an interpreter, etc., as well as machine language codes produced by a compiler. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

As described above, although the embodiments have been described with limited drawings, those skilled in the art can apply various technical modifications and variations based on the above. For example, the described techniques are performed in a different order than the described method, and / or the components of the described system, structure, device, circuit, etc. are combined or combined in a different form from the described method, or other components Alternatively, even if replaced or substituted by equivalents, appropriate results can be achieved.

Claims (5)

In the semiconductor chip for sensing the unstability of the response signal (PUF: Physically Unclonable Function) generated by the circuit,
An operation circuit that performs a predetermined digital operation using an output signal output from the physical copy protection function circuit and an inverted signal of the output signal, and outputs a result of the digital operation to a sampling circuit;
A reference signal generating circuit that outputs a reference signal for determining a sampling time of the sampling circuit to the sampling circuit in response to an operation signal; And
When it is determined that the result value of the digital operation is sampled according to the reference signal and the response signal of the physical copy protection function circuit is determined according to the sampling result, the first signal and the response signal of the physical copy protection function circuit are determined. Sampling circuit that stores the second signal if it is determined before determination
Semiconductor chip comprising a.
According to claim 1,
The operation circuit,
A semiconductor chip including an XOR gate and outputting a result of the XOR operation performed on the output signal and the inverted signal of the output signal to the sampling circuit as a result value of the digital operation.
According to claim 2,
The reference signal generation circuit,
A semiconductor chip that determines a delayed sampling time of the sampling circuit based on an input select signal and outputs a reference signal corresponding to the delayed sampling time to the sampling circuit.
According to claim 3,
The sampling circuit,
A semiconductor chip including a D-flip-flop and sampling the result of the digital operation using the reference signal as a clock signal.
According to claim 4,
The sampling circuit,
When it is determined that the response signal of the physical copy protection function circuit is determined based on the delayed sampling time, it is determined that the first signal having a high value and the response signal of the physical copy protection function circuit are determined. In the case, a semiconductor chip that outputs a second signal having a low value as a stability check bit of the physical copy protection function circuit.

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