KR102144984B1 - Apparatus and method for processing digital signal for next generation active phase ladar - Google Patents

Abstract

The present invention relates to a device and a method for digital transmission/reception signal processing for next-generation active phase radar. In an active phase array radar system, a control unit converts a digital serial signal for sending to a target into a k-bit digital parallel signal, outputs the k-bit digital parallel signal, and converts k-bit digital parallel signals input from n signal conversion units into a serial signal. The n signal conversion units include a DAC performing output after converting the k-bit digital parallel signal into an RF signal and an ADC converting reception signals input from n RF units into a k-bit digital parallel signal and outputting the signal to the control unit. The control unit changes the k-bit digital parallel signal and outputs the signal to the n signal conversion units. For the k-bit digital parallel signal to be shifted by m bit and output to the DAC of each n signal conversion unit every time a beam is sent to the target, the control unit includes an FPGA unit including a scrambler shifting a k-bit reference digital signal by m bit and outputting it every time the beam is sent to the target by using a mapping table in which a k-bit low digital signal preset to be input from the FPGA unit to the DAC and a k-bit reference digital signal input to the DAC through the scrambler of the FPGA unit during the initial beam sending are mapped in advance and n transmission SerDes units converting the k-bit reference digital signal input from the FPGA unit into a k-bit digital parallel signal and outputting it to the DAC.

Description

TECHNICAL FIELD [Apparatus and method for processing digital signal for next generation active phase ladar}

The present invention relates to an apparatus and method for processing digital transmit/receive signals for next-generation active phase radars. More specifically, n DACs for n channels with one logic implemented in an FPGA determine the RF output voltage of each FET driver. The present invention relates to an apparatus and method for processing digital transmission/reception signals for next-generation active-phase radars, which propose a digital transmission/reception signal processing apparatus and method for a next-generation active-phase radar that can be adjusted without using.

In the transmitting and receiving module, which is one of the components of the radar system in the defense ground defense system, the modern radar design trend is based on the active electronically scanned array radar (AESA) structure, and for target detection of the active phase array radar. For each channel of the radiating element, the transmit/receive phase and receive gain of the antenna are controlled.

To this end, a transmission/reception module is used to control the transmission/reception phase and reception gain of the antenna for each channel bundle, and the control method is largely parallel to input k bits of digital input of a k bit DAC (Digital Analog Converter) at a time per clock cycle. ) Method and one or k/2, k/3, k/4... … It is divided in a serial method that divides and inputs k bits of digital input through two input ports. In addition, according to the type of circuit that composes the analog output of the DAC, it is classified into a resistance ladder type, a resistance string type, a delta sigma type, and a current output type.

Unlike the traditional method, the digital transmission/reception module sends the RF output through the digital input to the input of the power amplifier stage using the DAC of the transmitting stage. At the receiving end, the output of the low-noise amplifier end receiving the reflected signal from the target is received as an RF input using an ADC and converted into a digital signal.

The DAC or ADC of each stage is controlled using the FPGA inside the transceiver module. The digital signal output and input of each stage are connected to the FPGA, and each stage transmits and receives the corresponding value to process the signal. To this end, a dynamic element matching (DEM) operation has been implemented inside a DAC of a transmission path.

The DEM function is one of the techniques to reduce the DAC's output noise floor. Typically, the k-bit DAC output consists of 2 ^k -1 FET driver stages. Many FETs may not have the same performance due to process problems. If a problem-prone low-performance FET is turned on, a noise component may occur in the spectrum. If each FET is turned on at random, the probability of turning on a low-performance FET that has a problem in the process is lowered, which can lead to a reduction in noise components.

However, if a DAC with a DEM function is used, the noise characteristic of the transmission signal is improved, but the unit cost is increased, and the mass productivity is degraded due to the expansion of the chip size. In particular, the existing technology is a structure in which logic for the DEM function is implemented for each DAC chip provided in the transmission path. For example, if 100 DAC chips are used, the area of the logic for the DEM function is at least 100 times wider based on a simple chip area. If the function is implemented inside the chip for the DEM function, up to 10% of the chip die space is used more depending on the number of output current cells. In addition, as the chip size increases, the number of chips that can be obtained per wafer decreases, resulting in an increase in unit cost.

Domestic registered patent No. 10-178598 (registered on Oct. 10, 2017)

In order to solve the above-described problem, the technical problem to be achieved by the present invention is not to implement each DEM function in n DACs for n channels when transmitting a beam toward a target, but to the inside of an FPGA (Field Programmable Gate Array). It is to propose a digital transmission/reception signal processing device and method for a next-generation active phase radar that can replace the existing DEM function by adjusting digital signals input to n DACs for n channels with one logic implemented in .

The problem of the present invention is not limited to those mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

As a means for solving the above-described technical problem, according to an embodiment of the present invention, a digital transmission/reception signal processing apparatus for a next-generation active phase radar of an active phase array radar system transmits a digital serial signal to be transmitted as a target. A control unit for converting and outputting a parallel signal, and converting a digital parallel signal of k bits input from the following n signal conversion units into a serial signal; A digital analog converter (DAC) that converts k-bit digital parallel signals input from the control unit into RF signals and outputs them, and converts received signals input from the following n RF units into k-bit digital parallel signals to the control unit. N signal conversion units including an output ADC (Analog Digital Converter); And n RF units for amplifying the power of the RF signals input from the n signal conversion units and transmitting them to the antenna, and amplifying low noise for the received signal reflected from the target, wherein the control unit includes a set rule Depending on the k-bit digital parallel signal is varied and output to the n signal converters, but each time a beam is transmitted as a target, the k-bit digital parallel signal is shifted by m bits to each of the n signal converters. To output to the DAC, a mapping table in which a preset k-bit low digital signal to be input to the DAC from the FPGA unit and a k-bit reference digital signal input to the DAC through the scrambler of the FPGA unit at the time of initial beam transmission is mapped is used. Thus, an FPGA (Field Programmable Gate Array) unit including a scrambler for shifting and outputting the k-bit reference digital signal by m bits each time a beam is transmitted as a target; And n transmission SerDes units for converting a k-bit reference digital signal input from the FPGA unit into a k-bit digital parallel signal and outputting the converted digital parallel signal to the DAC, wherein each DAC of the n signal conversion units includes: The output voltage of the RF signal is regularly varied by generating an on-off control signal mapped to a k-bit digital parallel signal shifted by m bits from the control unit, and the scrambler is a reference digital signal of k bits each time a beam is transmitted. The number of shifts is stored in a memory, or point information at which the k-bit reference digital signal is shifted is stored, and it is checked to which position the reference digital signal is shifted when the next beam is transmitted.

The DAC includes: a decoder for generating and outputting an on-off control signal corresponding to a k-bit digital parallel signal for each of a plurality of drivers when a k-bit digital parallel signal is input from the control unit; A switching unit for transmitting the on-off control signal output from the decoder to a corresponding driver; And a driving unit including the plurality of drivers, wherein the plurality of drivers are individually turned on and off according to an on/off control signal input through the switching unit to output an RF signal.

On the other hand, according to another embodiment of the present invention, a method for processing a digital transmission/reception signal for a next generation active phase radar in an active phase array radar system includes: (A) a digital transmission/reception signal processing apparatus transmits a digital serial signal to be transmitted as a target by k bits. Converting and outputting a digital parallel signal of; (B) converting, by the digital transmission/reception signal processing apparatus, a k-bit digital parallel signal input from the step (A) into an RF signal and outputting an RF signal; And (C) the digital transmission/reception signal processing apparatus, amplifying the power of the RF signal input from the step (B) and transmitting it to a target through an antenna; wherein, the step (A) includes: Accordingly, the digital parallel signal of k bits is varied and output, but each time the digital transmission/reception signal processing apparatus transmits a beam to a target, the digital parallel signal of k bits is shifted by m bits and output to the step (B). , (A1) The digital transmission/reception signal processing apparatus includes a k-bit low digital signal preset to be input from the FPGA to the DAC and a k-bit reference digital signal input to the DAC through the scrambler of the FPGA upon initial beam transmission. Shifting the k-bit reference digital signal by m bits each time a beam is transmitted as a target using the mapped mapping table, and outputting the signal; And (A2) converting the k-bit reference digital signal inputted in the step (A1) into a k-bit digital parallel signal and outputting the converted digital parallel signal to the DAC; wherein the scrambler includes a k-bit reference for each beam transmission. The number of times the digital signal is shifted is stored in the memory, or point information at which the k-bit reference digital signal is shifted is stored to check the position to which the reference digital signal is shifted when the next beam is transmitted, and the above (B) In step (A), the output voltage of the RF signal is regularly varied according to an on-off control signal that is shifted by m bits from step (A) and mapped to an input k-bit digital parallel signal.

The step (B) includes: (B1) generating and outputting, by the digital transmission/reception signal processing apparatus, an on/off control signal corresponding to an input k-bit digital parallel signal for each of a plurality of drivers; (B2) a switching step of transferring the on-off control signal output from step (B1) to a corresponding driver; And (B3) outputting an RF signal by individually turning on and off the plurality of drivers according to the on-off control signal input from step (B2).

According to the present invention, in the case of a chip manufacturer (Fabless), it is possible to provide a solution that can design by reducing the size of a DAC chip without using a space for the existing DEM function.

In addition, according to the present invention, in the case of a radar design company, it is possible to lower the unit cost by designing a radar by selecting a DAC having only a minimum function.

In addition, according to the present invention, a technique for reducing the Spur (unwanted noise in the frequency domain) component can be implemented only with the FPGA installed inside the transceiver module.

In addition, according to the present invention, since it is possible to design a board using a relatively small chip, it is possible to obtain a gain in the size of a printed circuit board (PCB) due to a miniaturized package. It can even reduce the overall radar due to reduction in module size.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a block diagram showing a digital transmission/reception signal processing apparatus for a next-generation active phase radar according to an embodiment of the present invention;
2 is a diagram showing in detail the DAC shown in FIG. 1;
3 is a diagram showing an input/output source of an unmodified decoder when using a 2-bit DAC;
4 to 6 are diagrams showing input/output signals shifted by one bit each time a beam is transmitted
7 is a flowchart illustrating a digital transmission signal processing method of a digital transmission/reception signal processing apparatus for a next generation active phase radar according to an embodiment of the present invention.

Prior to describing specific details for the implementation of the present invention, terms or words used in the specification and claims may be appropriately defined by the inventor in order to describe his or her own invention in the best way. Based on the principle that the present invention should be interpreted as a meaning and a concept corresponding to the technical matters of the present invention.

Terms such as "comprise", "comprise", and "have" described in the present specification mean that the corresponding component can be included unless otherwise stated, and thus other components are not excluded. It means that it can contain more elements.

In addition, terms such as "... unit", "... group", and "module" described in this specification mean a unit that processes at least one function or operation, which can be implemented by hardware or software or a combination of hardware and software. I can. In addition, articles such as "one", "one" and "the" are meant to include both the singular and the plural in the context describing the present invention, unless otherwise indicated in the specification or clearly contradicted by the context. Can be used.

In addition, if an element, component, device, or system is stated to include a program or a component made of software, the element, component, device, or system is executed by the program or software, even if there is no explicit mention. Or, it should be understood as including hardware (eg, memory, CPU, processor, etc.) or other programs or software (eg, a driver required to drive an operating system or hardware) required to operate.

In addition, it should be understood that an element (or component) may be implemented in software, hardware, or any form of software and hardware, unless otherwise specified in the implementation of the element (or component).

Accordingly, the present invention may also provide a program stored in a computer-readable recording medium executed on a computer controlling the digital transmission/reception signal processing apparatus in order to implement a digital transmission/reception signal processing method of the digital transmission/reception signal processing apparatus.

The above objects, other objects, features, and advantages of the present invention will be easily understood through the following preferred embodiments related to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a digital transmission/reception signal processing apparatus 100 for a next generation active phase radar according to an embodiment of the present invention.

The digital transmission/reception signal processing apparatus 100 shown in FIG. 1 is a transmission/reception module that is one of the components of a radar system in a defense ground defense system. The modern radar design trend is based on the active phase array (AESA) structure, and the antenna transmit/receive phase and receive gain control are performed for each radiating element channel for target detection of the active phase array radar. That is, the transmission/reception signal processing apparatus 100 may be arranged to have n channels in front of the first to nth antennas 11, …, 11_n for transmitting and receiving a beam toward a target, and transmit/receive phase control and reception gain Control is carried out, high-power amplification of the transmission signal to be sent to the antenna's radiating element, and low-noise amplification of the received signal reflected by the target.

To this end, the digital transmission/reception signal processing apparatus 100 controls each of n channel bundles, and each DAC (eg, 122) may use a current driving method of k-bit parallel input. This means that each DAC 122 inputs k bits of the digital input of the k-bit DAC at a time in one clock cycle, and the analog output of the DAC uses a current output type.

Referring to FIG. 1, a digital transmission/reception signal processing apparatus 100 for a next-generation active phase radar according to an embodiment of the present invention includes a control unit 110, first to n-th signal conversion units 120, …, 120_n, and first To nRF units 130, ..., 130_n.

The control unit 110 converts the digital serial signal of the beam to be transmitted to the target into a digital parallel signal of k bits, and outputs it, but each time the beam is transmitted, the first digital parallel signal of k bits is varied according to a set rule. Through the n-th signal conversion units 120, ..., 120_n may be output in parallel. The k of k bits applied by the controller 110 may be equally determined by k bits set in each DAC (eg, 122).

The first to nth signal conversion units 120, …, 120_n convert the k-bit digital parallel signal input from the control unit 110 into an RF signal by a digital analog converter (DAC) and output the converted signal. Each of the n-signal conversion units 120, …, 120_n may regularly vary an output voltage of an RF signal according to a k-bit digital parallel signal input from the control unit 110.

The first to nRF units 130, …, 130_n amplify the power of the RF signal input from the first to nth signal conversion units 120, …, 120_n to each of the first to nth antennas 11, …, 11_n) can be transmitted.

According to the above description, the operation of the digital transmission/reception signal processing apparatus 100 can be largely divided into an operation of a transmitting end and a receiving end. In the case of the transmitter, the digital transmission/reception signal processing apparatus 100 converts the digital input into an analog RF output using the DAC 122 and sends it to the input of the power amplifier. In the case of the receiving end, the digital transmission/reception signal processing apparatus 100 receives the output of the low-noise amplifier end receiving the received signal reflected from the target as an RF input using an ADC, converts it into a digital signal, and sends it to the input of the control unit 110.

Hereinafter, a transmission/reception operation of the digital transmission/reception signal processing apparatus 100 using the control unit 110, the first signal conversion unit 120, and the first RF unit 130 will be described in detail.

The control unit 110 may include an FPGA unit 112 and first to n-th SerDes units 114, ..., 114_n, and the first SerDes unit 114 will be described as an example. The first SerDes unit 114 includes a first transmitting SerDes unit 114a and a first receiving SerDes unit 114b.

The first signal conversion unit 120 includes a DAC 122 and an ADC 124.

The first RF unit 130 includes a power amplifier 132 and a low noise amplifier 134.

First, the transmission operation will be described.

Whenever the beam is transmitted as a target, the controller 110 shifts the k-bit digital parallel signal by m bits and outputs the shifted digital parallel signal to each of the first to n-th signal converters 120, ..., 120_n.

In detail, the FPGA unit 112 includes a k-bit low digital signal (hereinafter referred to as'FPGA input signal') set in advance to be input from the FPGA unit 112 to the DAC 122 and the FPGA unit when transmitting the first beam. By using the mapping table 112b to which the k-bit reference digital signal input to the DAC 122 through the scrambler 112a of 112 is mapped, the k-bit reference digital signal is transmitted to the target. It may include a scrambler 112a that shifts and outputs by m bits. m is an integer greater than or equal to 1, and as an initial value, one of odd numbers such as 1, 3, and 5 may be set, and then may be changed to a value (odd or even) desired by the user.

[Table 1] shows an example of a part of the mapping table 112b stored in the FPGA unit 112 or in the memory (not shown) of the controller 110 in the case of the 2-bit DAC 122.

FPGA input
(FPGA input signal) k-bit reference digital signal
(Scrambler output signal) Decoder input
(DAC input signal) B1 B"1 B"0 B0 B'1 B'0 0 0 0 0 0 0 0 One 0 One 0 One One 0 One 0 One 0 One One One One One One

Referring to [Table 1], the mapping table 112b includes a'FPGA input' item and a'k-bit reference digital signal' item, and may further include a'decoder input' item.

In Table 1, the FPGA input signal is raw data previously set to be input from the FPGA unit 112 to the decoder 210. When k = 2 bits, since the DAC 122 is a 2-bit DAC, the FPGA input signal, that is, a digital signal preset to be input from the FPGA unit 112 to the decoder 210 includes 00, 01, 10 and 11. .

The k-bit reference digital signal is a digital serial signal mapped for each FPGA input signal so that it is input to the DAC 122 by the scrambler 112a when the first beam is transmitted. In the case of [Table 1], since '00, 01, 10, 11' is mapped as the reference digital signal to the FPGA input signal '00, 01, 10, 11' when transmitting the first beam, the scrambler 112a is' 00, 01, 10, 11' may be output as serial signals to the first transmission SerDes unit 114a.

Thereafter, when transmitting the second beam, the scrambler 112a may shift the reference digital signal of k bits in [Table 1] by m bits and output it to the first transmission SerDes unit 114a. When m=1, the scrambler 112a first transmits '11, 00, 01, 10' as a reference digital signal of 2 bits shifted by 1 bit to the FPGA input signal '00, 01, 10, 11'. Serial output to the unit 114a.

Thereafter, when the third beam is transmitted, the scrambler 112a subtracts '10, 11, 00, 01' as a reference digital signal of 2 bits shifted by 1 bit to the FPGA input signal '00, 01, 10, 11'. 1 Serial output to the transmission SerDes unit 114a.

In addition, the scrambler 112a counts the number of times the k-bit reference digital signal is shifted each time a beam transmission command is received and stores it in a memory (not shown), or stores point information at which the k-bit reference digital signal is shifted. I can. This is for the scrambler 112a to quickly check to what position the reference digital signal is shifted when the next beam is transmitted.

As described above, the scrambler 112a may not generate a Fully Random Bit like a conventional DEM, but may shift an input bit previously set to be input to the DAC 122 by m bits, which is a preset rule. This is because if a Fully Random bit is generated inside the FPGA unit 112 like a DEM, a problem may occur due to the output of the decoder 210. The decoder 210 is fixed in the form of a chip inside the DAC 122, and the output of the decoder 210 is also fixed to the driver terminal. In this situation, if only k-bit input bits entering the DAC 122 are mixed, an erroneous analog RF output may occur. In order to prevent this, in the present invention, a digital signal of k bits may be shifted by m bits and output.

Meanwhile, the first transmission SerDes unit 114a of the first SerDes unit 114 converts a k-bit reference digital signal input from the scrambler 112a of the FPGA unit 112 into a k-bit digital parallel signal (hereinafter referred to as'DAC input It is called'signal', which can be converted to Digital in[k-1:0]) and output to the DAC 122. In the case of [Table 1], the first transmission SerDes unit 114a receives '00, 01, 10, 11' serially input from the scrambler 112a, and is a 2-bit digital parallel signal '00, 01, 10, 11' 'And input to the DAC 122.

FIG. 2 is a detailed diagram illustrating the DAC 122 shown in FIG. 1.

Referring to FIG. 2, the DAC 122 according to an embodiment of the present invention includes a decoder 210, a switching unit 220 and a driving unit 230.

When a k-bit digital parallel signal is input from the controller 110, the decoder 210 generates an on-off control signal corresponding to the input k-bit digital parallel signal for each of a plurality of drivers (not shown), and the switching unit ( 220). In this case, the decoder 210 may generate ^2k or ^2k -1 on-off control signals. To this end, a decoder output signal for turning on or off each driver (not shown) for each k-bit digital parallel signal may be preset in the decoder 210. The on control signal generated by the decoder 210 may be '1', and the off control signal may be '0'.

In the case of FIG. 3 to be described later, since it is a 2-bit DAC 122, the switching unit 220 includes first to third switches (not shown), and the driving unit 230 includes first to third drivers D0, D1, D2) may be included. Therefore, when '00' is input to the decoder 210, the decoder 210 generates on-off control signals of 0, 0, and 0 to the first to third drivers D2, D1, D0, respectively, When '01' is input, each 0, 0, 1 on-off control signal is generated, when '10' is input, each 0, 1, 1 on-off control signal is generated, and '11' is input In this case, a decoder output signal may be preset to generate on-off control signals of 1, 1, and 1, respectively, and output them to the first to third switches (not shown).

When the on-off control signal of 0, 0, 0 is generated, the output voltage of the RF signal is 0V, so when the decoder 210 receives the digital parallel signal of '00', it does not substantially generate the on-off control signal or Even if it occurs, it may not be output to the driver 230. In this case, the decoder 210 may output ^2k -1 decoder output signals, that is, an on/off control signal.

The switching unit 220 may transmit an on/off control signal output from the decoder 210 to a corresponding driver. The switching unit 220 may include ^2k -1 switches (not shown) capable of transmitting on-off control signals to a plurality of drivers at the same time. ^2k -1 is the number of switches or drivers, and when the RF output signal is 0V, it is not necessary to drive, so one can be subtracted from ^2k .

The driver 230 includes ^2k -1 drivers (not shown), and each driver may be a field effect transistor (FET). The driving unit 230 may individually turn on and off a plurality of drivers according to an on/off control signal input to each driver through the switching unit 220 to output an RF signal to the power amplifier 132.

Referring back to FIG. 1, the power amplifier 132 of the first RF unit 130 amplifies the power of the analog RF signal input from the driving unit 230 and outputs the amplified power to the first antenna 11 corresponding to the first channel. can do. The first antenna 11 transmits a beam toward the target.

Next, the reception operation will be described.

The low noise amplifier 134 of the first to nRF units 130, ..., 130_n amplifies the low noise of the received signal reflected from the target and outputs the amplified low noise to the first to nth signal conversion units 120, ??, 120_n. can do. The first to nth signal conversion units 120, …, 120_n convert the received signals input from the first to nRF units 130, …, 130_n into k-bit digital parallel by an ADC (Analog Digital Converter) 124. It may be converted into a signal and output to the first to nth receiving SerDes units 114b and more. In addition, the first to nth receiving SerDes units 114b of the control unit 110 convert k-bit digital parallel signals input from the first to nth signal conversion units 120, …, 120_n into serial signals. can do. The FPGA unit 112 stores k-bit digital serial signals and, if necessary, performs signal processing.

Hereinafter, an operation of shifting by 1 bit each time a beam is transmitted with reference to FIGS. 3 to 6 will be described using the 2-bit DAC 122 as an example.

3 is a diagram showing the original signal input to the decoder 210 or output from the decoder 210, that is, the original input/output of the unmodified decoder 210 in the case of using the 2-bit DAC 122, FIG. 4 to 6 are diagrams showing input/output signals shifted by one bit each time a beam is transmitted.

Referring to FIG. 3, the FPGA input is an FPGA input of the mapping table 112b and is a low digital signal preset to be input from the FPGA unit 112 to the decoder 210. The decoder input (DAC input) is a parallel 2-bit input signal that passes through the first transmission SerDes unit 114a through the scrambler 112a when transmitting the first beam. The decoder output (driver end input) is an on-off control signal (=output signal of the decoder 210 = 2-bit digital parallel signal) for turning on/off the gates of each driver.

When transmitting a beam for the first time, the scrambler 112a transmits a 2-bit reference digital signal consisting of '00, 01, 10, 11' to the first transmission SerDes unit 114a, as shown in FIG. 3, and transmits the first The SerDes unit 114a may convert a 2-bit reference digital signal consisting of '00, 01, 10, 11' into a 2-bit digital parallel signal and output it to the decoder 210. The decoder 210 receives [B'1, B'0]='00, 01, 10, 11' in parallel, and turns on and off since decoder output signals of 0, 0, and 0 are mapped to '00' first. The first to third switches corresponding to the first to third driving units D2, D1, D0 by generating on-off control signals of 0, 0 and 1 mapped to the next '01' without generating a control signal Each of the on-off control signals 0, 1, and 1 mapped to '10' are output to the first to third switches (not shown), respectively, and 1 mapped to '11' On/off control signals of, 1 and 1 may be output to the first to third switches (not shown), respectively.

Thereafter, when transmitting the second beam, the scrambler 112a shifts the 2-bit reference digital signal by one bit and transfers '11, 00, 01, 10' to the first transmission SerDes unit 114a, and the first The transmission SerDes unit 114a may convert a 2-bit reference digital signal consisting of '11, 00, 01, 10' into a 2-bit digital parallel signal and output it to the decoder 210.

The decoder 210 receives a 2-bit digital reference signal '11, 00, 01, 10' in which the FPGA input of FIG. 3 is shifted by 1 bit, as shown in FIG. 4, and first, 1, 1, 1 mapped to '11'. Generates an on-off control signal and outputs it to the first to third switches (not shown), generates and outputs the 0, 0, 1 on-off control signal mapped to '01', and outputs the 0 mapped to '10'. , 1, 1 On-off control signal can be generated and output.

Thereafter, in the case of transmitting the third beam, the decoder 210 receives a 2-bit digital reference signal '10, 11, 00, 01' in which the FPGA input of FIG. 3 is shifted by 2 bits, as shown in FIG. Generates 0, 1, 1 on-off control signals mapped to '10' and outputs them to the first to third switches (not shown), and generates 1, 1, 1 on-off control signals mapped to '11' And output, and generates and outputs 0, 0, 1 on-off control signals mapped to '01'.

Thereafter, in the case of transmitting the fourth beam, the decoder 210 receives '01, 10, 11, 00', which are 2-bit digital reference signals in which the FPGA input of FIG. 3 is shifted by 3 bits, as shown in FIG. Generates 0, 0, 1 on-off control signals mapped to '01', outputs them to the first to third switches (not shown), and generates 0, 1, 1 on-off control signals mapped to '10' And output, and generate and output 1, 1, 1 on-off control signals mapped to '11'.

Thereafter, when transmitting the fifth beam, the decoder 210 may generate a digital output signal, that is, an on-off control signal, as described with reference to FIG. 3 again.

According to the above description, when the radar transmits the first beam, the truth table in [Fig. 1] is followed, and when the second beam is transmitted, the truth table in [Fig. 2] is followed. That is, each time the beam is transmitted, the present invention is shown in Fig. 3 → Fig. 4 → Fig. 5 → Fig. 6 → Fig. 3 → Fig. 4. Can be operated to repeat the corresponding input at the FPGA stage.

7 is a flowchart illustrating a digital transmission signal processing method of the digital transmission/reception signal processing apparatus 100 for a next generation active phase radar according to an embodiment of the present invention.

The digital transmission/reception signal processing apparatus 100 for performing the digital transmission/reception signal processing method illustrated in FIG. 7 has been described with reference to FIGS. 1 to 6, and thus, a detailed description thereof will be omitted.

Referring to FIG. 7, when the FPGA unit 112 receives a beam transmission command from an upper control device that controls a bundle of transmission/reception modules, the scrambler 112a checks the mapping table 112b to check the reference digital signal of k bits. Do (S705, S710). In step S705, the bundle of transmission/reception modules means that there are a plurality of digital transmission/reception signal processing apparatuses 100 shown in FIG. 1, and the upper control apparatus is a control that gives a beam transmission command to the actual number of digital transmission/reception signal processing apparatuses 100 Device.

If the beam transmission command received in step S705 is the first transmission command (S715-Yes), the scrambler 112a shifts the k-bit reference digital signal identified in step S710 by 0 bit and outputs it to the first to nth transmission SerDes units. It can be done (S720).

The scrambler 112a may count the number of shifts (S=0) of the k-bit reference digital signal and store it in a memory (not shown) (S725).

Each of the first to nth transmission SerDes units converts the k-bit reference digital signal input from the scrambler 112a into a parallel signal, and then inputs it to the DACs of the first to nth signal converters 120, ..., 120_n. Do (S730). Steps S735 to S745 operate in the same manner by each of the DACs of the first to nth signal conversion units 120, ..., 120_n. Hereinafter, the DAC of the first signal conversion unit 120 ( 122) will be used as an example.

The decoder 210 of the DAC 122 outputs on-off control signals corresponding to the k-bit digital parallel signal input from step S730 to the switching unit 220 in parallel (S735).

The switching unit 220 provided as many as the number of drivers constituting the driving unit 230 may switch on and off corresponding drivers based on on/off control signals (0 or 1) input from step S735 (S740). . That is, the switching unit 220 transfers the input on/off control signals to the gates of the corresponding drivers, respectively.

The plurality of drivers are turned on or off according to the input on/off control signal, and the analog output voltage of the DAC 122, that is, the RF output signal, is determined according to the number of on/off drivers (S745). For example, if there are three decoder outputs shown in FIG. 3, assuming that the maximum voltage that the DAC 122 can output is 1.2V, if all three decoder outputs are on (D2, D1, D0 = 1, 1, 1), the output voltage of the DAC 122 becomes 1.2V. On the other hand, if only one decoder output is on (D2, D1, D0 = 0, 0, 1), the output voltage of the DAC 122 becomes 0.4V.

The power amplifier 132 amplifies the power of the RF output signal input from the DAC 122 and then outputs it to the first antenna 11 to be transmitted as a beam.

On the other hand, if the beam transmission command received in step S705 is not the first transmission command (S715-No), the scrambler 112a shifts the k-bit reference digital signal by m bits each time the beam is transmitted, and the first to nth transmission SerDes Output to the negatives (S755) For example, if it is the second transmission command and m=1, the scrambler 112a shifts the k-bit reference digital signal identified in step S710 by one bit and outputs it (S755).

The scrambler 112a may count the number of shifts (S=1) of the k-bit reference digital signal and store it in a memory (not shown) (S760).

Each of the first to n-th transmission SerDes units converts the m-bit-shifted k-bit reference digital signal input from the scrambler 112a into a parallel signal (S765), and then proceeds to step S735.

Accordingly, the digital transmission/reception signal processing apparatus 100 shifts a preset reference digital signal by m bits each time it transmits a beam and outputs it to the DACs, whereby the decoders of the DACs output a decoder output signal according to the shifted reference digital signal. By shifting, the RF output signal can be varied according to a rule.

8 is a flowchart illustrating a digital reception signal processing method of the digital transmission/reception signal processing apparatus 100 for a next-generation active phase radar according to an embodiment of the present invention.

Referring to FIG. 8, the low noise amplifier 134 of the first to nRF units 130, ??, and 130_n amplifies the low noise of a received signal that is reflected from the target and received by the antenna (S810).

The ADC 124 of the first to nth signal conversion units (120, …, 120_n) converts the received signal input from the low noise amplifier 134 into a k-bit digital parallel signal, and the first to nth receiving SerDes units It outputs as (114b and many others) (S820).

The first to nth receiving SerDes units 114b and a plurality of the k-bit digital parallel signals input from the first to nth signal conversion units 120, ..., 120_n are converted into a serial signal (S830).

The FPGA unit 112 stores k-bit digital serial signals input from the first to n-th receiving SerDes units 114b and others (S840).

On the other hand, although it has been described and illustrated in connection with a preferred embodiment for illustrating the technical idea of the present invention, the present invention is not limited to the configuration and operation as illustrated and described as described above, and deviates from the scope of the technical idea. It will be appreciated by those skilled in the art that a number of changes and modifications can be made to the present invention. Accordingly, all such appropriate changes and modifications and equivalents should be regarded as belonging to the scope of the present invention. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the attached registration claims.

100: digital transmission/reception signal processing device 110: control unit
112: FPGA unit
114,… , 114_n: first to nth SerDes units 114a: first transmitting SerDes units
114b: first receiving SerDes unit
120,… , 120_n: first to nth signal conversion units 122: DAC
124: ADC 210: decoder
220: switching unit 230: driving unit
130,… , 130_n: first to nRF units

Claims (4)

A controller for converting and outputting a digital serial signal to be transmitted as a target into a k-bit digital parallel signal, and converting the k-bit digital parallel signal input from the following n signal converters into a serial signal;
A digital analog converter (DAC) that converts and outputs k-bit digital parallel signals input from the control unit into RF signals, and converts received signals input from the following n RF units into k-bit digital parallel signals to the control unit. N signal conversion units including an output ADC (Analog Digital Converter); And
Including; n RF units for amplifying the power of the RF signal input from the n signal converters and transmitting the power to the antenna, and amplifying low noise for the received signal reflected from the target; and
The control unit,
According to a set rule, the k-bit digital parallel signal is varied and output to the n signal converters, but each time a beam is transmitted as a target, the k-bit digital parallel signal is shifted by m bits to the n signal converters. To output to each DAC,
Using a mapping table in which a k-bit low digital signal preset to be input from the FPGA unit to the DAC and a k-bit reference digital signal input to the DAC through the scrambler of the FPGA unit when the first beam is transmitted are mapped, the beam is targeted. A Field Programmable Gate Array (FPGA) unit including a scrambler for shifting and outputting the k-bit reference digital signal by m bits each time the signal is transmitted to each other; And
Including; n transmission SerDes units for converting a k-bit reference digital signal input from the FPGA unit into a k-bit digital parallel signal and outputting it to the DAC,
The DAC of each of the n signal conversion units generates an on-off control signal mapped to a digital parallel signal of k bits shifted by m bits from the control unit and inputted to regularly vary the output voltage of the RF signal,
The scrambler stores the number of shifts of the k-bit reference digital signal in memory each time a beam is transmitted, or stores point information at which the k-bit reference digital signal is shifted, and the reference digital signal is numbered when the next beam is transmitted. A digital transmission/reception signal processing device for a next-generation active phase radar, characterized in that checking whether the position is shifted. The method of claim 1,
The DAC,
A decoder for generating and outputting an on-off control signal corresponding to an input k-bit digital parallel signal for each of a plurality of drivers when a k-bit digital parallel signal is input from the controller;
A switching unit for transmitting the on-off control signal output from the decoder to a corresponding driver; And
And a driving unit that includes the plurality of drivers, and outputs an RF signal by individually turning on and off the plurality of drivers according to an on/off control signal input through the switching unit. Transmission and reception signal processing device. In the method of processing digital transmission/reception signals for next-generation active phase radar in an active phase array radar system,
(A) a step of converting, by a digital transmission/reception signal processing apparatus, a digital serial signal to be transmitted to a target into a digital parallel signal of k bits and outputting a digital parallel signal;
(B) converting, by the digital transmission/reception signal processing apparatus, a k-bit digital parallel signal input from the step (A) into an RF signal and outputting an RF signal; And
(C) the digital transmission/reception signal processing apparatus, amplifying the power of the RF signal input from the step (B) and transmitting it to a target through an antenna; Including,
In the step (A), a digital parallel signal of k bits is varied and output according to a set rule, and each time the digital transmission/reception signal processing apparatus transmits a beam to a target, the digital parallel signal of k bits is transmitted by m bits. To output to step (B) by shifting,
(A1) The digital transmission/reception signal processing device maps a k-bit low digital signal preset to be input from the FPGA to the DAC and a k-bit reference digital signal input to the DAC through the scrambler of the FPGA upon initial beam transmission. Shifting and outputting the k-bit reference digital signal by m bits each time a beam is transmitted to a target using a mapping table; And
(A2) converting a k-bit reference digital signal input in step (A1) into a k-bit digital parallel signal and outputting it to the DAC; and
The scrambler stores the number of shifts of the k-bit reference digital signal in memory each time a beam is transmitted, or stores point information at which the k-bit reference digital signal is shifted, and the reference digital signal is numbered when the next beam is transmitted. Check if it is shifted to the position,
In the step (B), the output voltage of the RF signal is regularly varied according to an on-off control signal mapped to a digital parallel signal of k bits shifted by m bits from the step (A). Digital transmission/reception signal processing method for next-generation active phase radar. The method of claim 3,
The step (B),
(B1) generating and outputting, by the digital transmission/reception signal processing apparatus, an on/off control signal corresponding to an input k-bit digital parallel signal for each of a plurality of drivers;
(B2) a switching step of transferring the on-off control signal output from step (B1) to a corresponding driver; And
(B3) outputting an RF signal by individually turning on and off the plurality of drivers according to the on-off control signal input from step (B2); and processing digital transmission/reception signals for next-generation active-phase radars, comprising: Way.

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