KR102143947B1 - Digital low-dropout regulator and operation method thereof - Google Patents

Abstract

The digital LDO regulator according to an embodiment of the present application includes a main controller and a power array that outputs an output voltage based on a control voltage applied from the main controller, and the main controller includes the output voltage and at least one A detection unit that compares a reference voltage to detect transition information for the output voltage, a status signal generation unit that outputs one of COARSE, FINE, and MIDDLE status signals based on the transition information and the control voltage, and the COARSE status signal In response to, a digital logic unit for adjusting the control voltage through an adaptive SAR algorithm, the adaptive SAR algorithm, according to the transition information, any one of the MSB-FT algorithm and the MODIFIED LSB-FT algorithm This is applied selectively.

Description

Digital LDO regulator and its operation method {DIGITAL LOW-DROPOUT REGULATOR AND OPERATION METHOD THEREOF}

The present application relates to a digital LDO regulator and a method of operating the same, and to a digital LDO regulator using an adaptive SAR-based algorithm and a method of operating the same.

Recently, with the improvement of System-On-a-Chip (SOC) technology, SOC's per-core dynamic voltage and frequency scaling schemes require regulators that provide a wide range of supply voltages up to the near-threshold or sub-threshold range.

Therefore, a digital LDO regulator (Digital Low-Dropout) that operates as a digital circuit without using an analog circuit such as an amplifier sensitive to a supply voltage to be used at a low voltage is being actively studied.

Accordingly, in the present application, advantages such as fast recovery time and simple structure can be obtained through the conventional SAR algorithm, while operating at a low supply voltage, fast transient response can be obtained, and bits generated by initialization of the control voltage. It provides a digital LDO regulator using an adaptive SAR algorithm that can reduce bit cycle losses.

The purpose of this application is to provide a digital LDO regulator and its operation method that can solve the problem of DC accuracy reduction occurring in the dead-zone structure and the loss due to initialization of the control voltage generated through the existing SAR algorithm. About.

The digital LDO regulator according to an embodiment of the present application includes a main controller and a power array that outputs an output voltage based on a control voltage applied from the main controller, and the main controller includes the output voltage and at least one A detection unit that compares a reference voltage to detect transition information for the output voltage, a status signal generation unit that outputs one of COARSE, FINE, and MIDDLE status signals based on the transition information and the control voltage, and the COARSE status signal In response to, a digital logic unit for adjusting the control voltage through an adaptive SAR algorithm, the adaptive SAR algorithm, according to the transition information, any one of the MSB-FT algorithm and the MODIFIED LSB-FT algorithm This is applied selectively.

In an embodiment, the digital logic unit adjusts the control voltage through a barrel shifter algorithm in response to the FINE state signal.

In an embodiment, the digital logic unit adjusts the control voltage through an LSB-FT algorithm in response to the MIDDLE state signal.

In an embodiment, the transition information includes dead zone crossing information and slope information for the output voltage, and the dead zone crossing information is based on time information at which the output voltage and the at least one reference voltage cross each other. Correspondingly, the slope information corresponds to a transition state of one of a heavy transition state and a mild transition state determined according to the dead zone crossing information.

In an embodiment, the digital logic unit sequentially performs an initialization operation, a comparison operation, a setting operation, and a completion operation of the MSB-FT algorithm with respect to the control voltage when the transition information is in a heavy transition state, and the transition information When is in the mild transition state, the control voltage sequentially performs an initialization operation, a setting operation, a comparison operation, and a completion operation of the MODIFIED LSB-FT algorithm.

In an embodiment, the digital logic unit performs the initialization operation by detecting a preset code corresponding to upper bits of the control voltage from a preset lookup table based on the transition information.

In an embodiment, the digital logic unit performs the setting operation of the MODIFIED LSB-FT algorithm when one bit having a different state from the remaining bits of the control voltage is set during the setting operation of the MODIFIED LSB-FT algorithm. When finished, a setting operation of the MSB-FT algorithm, which is a completion operation of the MODIFIED LSB-FT algorithm, is performed on lower bits following the other bit.

In an embodiment, the digital logic unit performs the setting operation of the Modified LSB-FT algorithm when the last bit of bits that can change within a preset transition boundary between the control voltage and the target control voltage is set to the control voltage. When finished, the MSB-FT algorithm setting operation is performed on lower bits following the last bit.

In an embodiment, further comprising a clock generator for generating a clock and a dynamic comparator for receiving the clock, comparing the output voltage with a target output voltage, and outputting an up signal or a down signal, wherein the main controller comprises: A counter is provided with a clock and counts the up signal or the down signal, and the counter counts the number of bit changes to the control voltage after the initialization operation.

In an embodiment, the status signal generation unit outputs the FINE status signal, and when either the up signal or the down signal is continuously counted more than a preset number of times, the FINE status signal is converted to the MIDDLE status signal. And output to the digital logic unit.

In an embodiment, the detection unit comprises: a first detection unit configured to detect a first intersection point of the dead zone crossing information and generate an operation signal at the first intersection point, and in response to the operation signal, the dead zone crossing information A second detection unit that detects a second intersection point of and generates a rising pulse at the second intersection point, a delay unit that digitally delays the operation signal through delay cells and capacitor arrays to generate a delay signal, and the delay And a determination unit determining slope information of the output voltage based on the signal and the rising pulse.

In an embodiment, when the FINE state signal is output, the state signal generator converts the FINE state signal to the COARSE state signal at the first intersection point and outputs it to the digital logic unit.

In an embodiment, the first detection unit includes a pair of static comparators for comparing the at least one reference voltage and the output voltage.

In an embodiment, the second detection unit includes a pair of dynamic comparators for comparing the output voltage and the at least one reference voltage in response to the operation signal.

In an embodiment, the determination unit includes a D flip-flop receiving the delay signal as an input signal and the rising pulse as a trigger signal.

A method of operating a digital LDO regulator including a power array and a main controller according to an embodiment of the present application, the step of outputting an output voltage by the power array based on a control voltage applied from the main controller, the main controller Detecting transition information by comparing the output voltage with at least one reference voltage, the main controller outputting one of COARSE, MIDDLE, and FINE status signals based on the transition information and a control voltage And adjusting, by the main controller, the control voltage to a target control voltage through an algorithm corresponding to the one state signal.

In an embodiment, the adjusting comprises: when the main controller receives the COARSE state signal, selecting an adaptive SAR algorithm for the control voltage and according to the transition information, the main controller is And adjusting the control voltage through one of an algorithm and a MODIFIED LSB-FT algorithm.

In an embodiment, the adjusting includes, when the main controller receives the FINE status signal, adjusting the control voltage through a barrel shifter algorithm.

In an embodiment, the adjusting includes, when the main controller receives the MIDDLE status signal, adjusting the control voltage through an LSB-FT algorithm.

In an embodiment, the detecting of the transition information comprises detecting a first crossing point of dead zone crossing information by comparing the output voltage and the at least one reference voltage, and generating an operation signal at the first crossing point. Generating, in response to the operation signal, detecting a second intersection point of the dead zone crossing information by comparing the output voltage and the at least one reference voltage, and generating a rising pulse at the second intersection point. And generating a delay signal by digitally delaying the operation signal through delay cells and capacitor arrays, and determining slope information of the output voltage based on the delay signal and the rising pulse.

The digital LDO regulator and its operation method according to the embodiment of the present application can reduce a loss due to initialization of the control voltage by reducing the switching operation of the control voltage through the adaptive SAR algorithm.

1 is a block diagram of a digital LDO regulator according to an embodiment of the present application.
2A to 2D are exemplary embodiments for explaining transition information (Transient Statue) for an output voltage.
3 is an embodiment according to the operation of the state signal generator of FIG. 1.
4 is an embodiment according to the operation of the digital logic unit of FIG. 1.
5 is a block diagram of a digital LDO regulator according to another embodiment of the present application.
6 is an embodiment of the digital LDO regulator of FIG. 5.
7 is a block diagram of a digital LDO regulator according to another embodiment of the present application.
8 is an embodiment of the detection unit of FIG. 1.
9 is an operation process of a digital LDO regulator according to an embodiment of the present application.
10 is an operation process of the digital LDO regulator of FIG. 5.
11 is an operation process according to an embodiment of the detection unit of FIG. 1.

Specific structural or functional descriptions of the embodiments according to the concept of the present application disclosed in the present specification are exemplified only for the purpose of describing the embodiments according to the concept of the present application, and the embodiments according to the concept of the present application are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present application can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail in the present specification. However, this is not intended to limit the embodiments according to the concept of the present application to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present application.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present application, the first component may be named as the second component, and similarly The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it is directly connected to or may be connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

Terms used in the present specification are used only to describe specific embodiments, and are not intended to limit the present application. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate the presence of implemented features, numbers, steps, actions, components, parts, or a combination thereof, but one or more other features or numbers It is to be understood that it does not preclude the possibility of the presence or addition of, steps, actions, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in the present specification. Does not.

Hereinafter, the present application will be described in detail by describing a preferred embodiment of the present application with reference to the accompanying drawings.

1 is a block diagram of a digital LDO regulator 10 according to an exemplary embodiment of the present application, and FIGS. 2A to 2D are exemplary embodiments for explaining transition information (Transient Statue) for an output voltage V _O , 3 is an embodiment according to the operation of the state signal generator 120 of FIG. 1, and FIG. 4 is an embodiment according to the operation of the digital logic unit 130 of FIG. 1.

1 to 4, the digital LDO regulator 10 may include a main controller 100 and a power array 200.

First, the main controller 100 may apply a control voltage V _C to the power array 200. Here, the power array 200 may output an output voltage V _O based on the control voltage V _C applied from the main controller 100.

In the power array 200 according to the embodiment, a plurality of power transistors 210_1 to 210_N, 220_1 to 220_N, 230_1 to 230_N that receive the control voltage V _C to the drain side and output the output voltage V _O to the source side. ) Can be included.

More specifically, the plurality of power transistors 210_1 to 210_N, 220_1 to 220_N, and 230_1 to 230_N are first power transistor units 210_1 to 210_N that operate according to preset most significant bits of the control voltage V _C , to the predetermined least significant bit of the second power transistor unit (220_1 ~ 220_N) and the least significant bit and middle bit in a field between the most significant bit of the control voltage (V _C) that operates according to the control voltage (V _C) It may include third power transistor units 230_1 to 230_N operating accordingly. In this case, each of the power transistors 210_1 to 210_N, 220_1 to 220_N, and 230_1 to 230_N may be a PMOS transistor.

For example, the first power transistor units 210_1 to 210_N are 8-BIT Binary MSB, the second power transistor units 220_1 to 220_N are 4-Bit Unary LSBs, and the third power transistor units 230_1 to 230_N May be 3-Bit Binary Middle.

Hereinafter, in the present application, the control voltage V _C will be described by referring to a control code having a plurality of bits. Here, the control code of the control voltage V _C corresponds to the highest control code VG for changing the most significant bits corresponding to the first power transistor units 210_1 to 210_N and the second power transistor units 220_1 to 220_N. It may include a lowest order control code VL for changing the least significant bits and a middle control code VM for changing middle bits corresponding to the third power transistor units 230_1 to 230_N. At this time, the operation of changing one bit in any one of the highest control code (VG), the lowest control code (VL), and the middle control code (VM) may mean switching the control voltage (V _C ) once. have. Hereinafter, in the present application, for clarity, an operation example of changing the highest control code VG of the control voltage V _C will be described.

For example, when the highest control code VG is '1010110' and the target control voltage V _TC is '1110111', the operation of changing one bit of the control code is performed by the first power transistor units 210_1 to 210_N. It may mean switching for 2 times. Hereinafter, for convenience of description, a control code VG<7:0> such as '1010110' is described as the highest control code VG of the control voltage V _C.

The main controller 100 according to the embodiment may include a detection unit 110, a status signal generation unit 120, and a digital logic unit 130.

First, the detector 110 can detect the output voltage (V _O) and the transition information (Transient Statue) for the output voltage (V _O) by comparing at least one reference voltage (VREFH1, VREFL1, VREFH2, VREFL2) . Here, the transition information for the output voltage V _O may include dead-zone crossing information and slope information.

More specifically, the dead zone crossing information may correspond to a time when the output voltage V _O and at least one reference voltage VREFH1, VREFL1, VREFH2, and VREFL2 cross each other. Here, the dead-zone may mean voltage sections formed by at least one or more reference voltages VREFH1, VREFL1, VREFH2, and VREFL2.

For example, as shown in FIG. 2A, the dead zone is equal to a first dead zone formed by a first pair of reference voltages VREFH1 and VREFL1 among at least one reference voltage VREFH1, VREFL1, VREFH2, and VREFL2. As shown in 2b, a second dead zone formed by a second pair of reference voltages VREFH2 and VREFL2 among at least one reference voltage VREFH1, VREFL1, VREFH2, and VREFL2 may be included. Here, the second dead zone may be formed in a wider area than the first dead zone.

A second cross-point addition, the dead zone crossing information to the output voltage (V _O) and the first dead zone is the first intersection point (T1) and the output voltage (V _O) and the second dead zone crossing each other and cross each other ( T2) may be included. For example, as shown in FIGS. 2C and 2D, when the output voltage decreases, the dead zone crossing information is the first dead zone reference voltage (eg, VREFL1) and the output voltage V _O. A second intersection point T2 at which the first intersection point T1 and the reference voltage (eg, VREFL2) of the second dead zone and the output voltage V _O cross may be included.

In addition, the slope information of the output voltage V _O may correspond to any one of a heavy transition (HT) state and a mild transition (MT) state determined according to the dead zone crossing information. . For example, as shown in Figure 2c, when the slope information of the output voltage (V _O ) is less than or equal to a preset slope, it corresponds to the mild transition (MT) state, and as shown in Figure 2d, the output When the slope information of the voltage V _O is greater than a preset slope, it may correspond to the heavy transition HT state.

Next, the state signal generation unit 120 may be a finite state machine (FSM) that outputs one of COARSE, FINE, and MIDDLE based on the transition information and the control voltage V _C. .

More specifically, the state signal generator 120 may output a COARSE state signal at a first intersection point T1 of transition information detected by the detector 110.

In addition, when the control voltage (V _C ) is adjusted through the digital logic unit 130 to be described later according to the COARSE state signal, the state signal generation unit 120 transitions (TRAN) the COARSE state signal to the MIDDLE state signal to MIDDLE. Status signals can be output.

In addition, when the control voltage (V _C ) is adjusted through the digital logic unit 130 to be described later according to the MIDDLE state signal, the state signal generator 120 converts the MIDDLE state signal to the FINE state signal to generate the FINE state signal. Can be printed.

According to an embodiment, the state signal generator 120 may transition (TRAN) the FINE state signal to the COARSE state signal based on the dead zone crossing information. As shown in FIG. 3, the status signal generation unit 120 generates a FINE status signal at a first intersection point T1 of the dead zone crossing information based on the dead zone crossing information detected through the detection unit 110. Transition (TRAN) to a COARSE state signal may be output to the digital logic unit 130.

According to another embodiment, the state signal generation unit 120 transitions the FINE state signal to the MIDDLE state signal based on the number of times counted through the counter 140 shown in FIG. 7 (TRAN. )can do. More specifically, when the counter 140 shown in FIG. 7 continuously counts the up signal (UP) or the down signal (DN) more than a preset number of times, the status signal generator 120 transmits the FINE status signal to the MIDDLE state. Transition (TRAN) to a signal may be output to the digital logic unit 130. For example, when any one of the up signal (UP) or the down signal (DN) is continuously counted 8 or more times, the status signal generation unit 120 generates a FINE status signal as shown in FIG. Transition (TRAN) to the MIDDLE state signal may be output to the digital logic unit 130. Hereinafter, in FIG. 7, the counter 140 will be described in more detail.

Next, the digital logic unit 130 may adjust the control voltage V _C to the target control voltage V _TC . More specifically, the digital logic unit 130 receives any one status signal through the status signal generation unit 120, and sets the control voltage V _C to the target control voltage through an algorithm corresponding to any one status signal. It can be adjusted with (V _TC ).

According to an embodiment, the digital logic unit 130 uses an adaptive SAR-based Algorithm (ASA) to adjust the control voltage V _C in response to the COARSE status signal output through the status signal generation unit 120. Can be adjusted through. Here, the adaptive SAR algorithm (ASA) is an algorithm in which one of the MSB-FT algorithm (MSB First-Track Algorithm) and the Modified LSB-FT algorithm (LSB First-Track Algorithm) is selectively applied according to the transition information. Can be

As shown in FIG. 4, the digital logic unit 130 responds to the COARSE status signal output through the status signal generation unit 120, and the adaptive SAR-based algorithm corresponding to the COARSE status signal. ASA), and according to the transition information, the control voltage (V _C ) can be adjusted to the target control voltage (V _TC ) through one of the MSB-FT algorithm and the Modified LSB-FT algorithm. For example, the digital logic unit 130 includes a control code VC<10:3> corresponding to the highest control code VG, a control code VC<15:0> corresponding to the lowest control code VL, and a middle control code. Control code VC<2:3> corresponding to (VM) can be adjusted.

More specifically, when the transition information is in a heavy transition state, the digital logic unit 130 sequentially performs an initialization operation, a comparison operation, a setting operation and a completion operation for the control voltage V _C through the MSB-FT algorithm. It can be adjusted with the control voltage (V _TC ).

First, the initialization operation may be an operation of initializing the control voltage V _C with a preset control code according to whether the output voltage V _O and the target voltage V _T are large or small. For example, when the output voltage (V _O ) is greater than the target voltage (V _T ), the digital logic unit 130 initializes the control voltage (V _C ) to '10000000', which is a preset control code, and the output voltage ( When V _O ) is less than the target voltage V _T , the digital logic unit 130 may initialize the control voltage V _C to a preset control code '011111111'.

Then, the comparison operation may be an operation of changing or maintaining the most significant bit of the preset control code according to an up signal (UP) or a down signal (DN). For example, when the output voltage V _O is smaller than the target voltage V _T and the down signal DN is counted through the counter 140, the digital logic unit 130 sets '011111111' to the most significant bit. When 0'is changed to '1', the output voltage V _O is smaller than the target voltage V _T and the up signal UP is counted through the counter 140, 0'can be maintained as it is.

Then, the setting operation may be an operation of setting the lower bit after the most significant bit to 0 or 1 depending on whether the output voltage V _O and the target voltage V _T are large or small. For example, if the output voltage (V _O ) is '011111111' and the target voltage (V _T ) is '111000000', the digital logic unit 130 is the lower bit after the most significant bit of the output voltage (V _O ). 1'('0 1 1111111') can be set to '0'.

Thereafter, the completion operation may be an operation of performing a comparison operation and a setting operation from the next lower bit '1'('0 1 1111111') to the least significant bit.

In addition, when the transition information is in a mild transition state, the digital logic unit 130 sequentially performs an initialization operation, a setting operation, a comparison operation, and a completion operation of the control voltage V _C through the modified LSB-FT algorithm, thereby controlling the target. It can be adjusted by voltage (V _TC ). Here, it can be defined by classifying the initialization operation into a P1 phase, a setting operation and a comparison operation into a P2 phase, and a completion operation into a P3 phase.

First, the setup operation (P1 phase) is to detect the initialization code corresponding to the high order bits of the control voltage (V _C) that has an existing from, a predetermined look-up table when initializing the bits of the control voltage (V _C) control It may be an operation of initializing with a control code of voltage V _C.

Table 1 below is an example of a preset lookup table.

Of control voltage
Upper bits Initialization code Of control voltage
Upper bits Initialization code 0000 00001111 1000 10001111 0001 00011111 1001 10011111 0010 00111111 1010 10111111 0011 00111111 1011 10111111 0100 01111111 1100 11001111 0101 01111111 1101 11011111 0110 01111111 1110 11101111 0111 01111111 1111 11111111

As shown in Table 1, the digital logic unit 130 may include a preset lookup table having initialization codes corresponding to high-order bits from the most significant bit to the 4th high-order bit of the control voltage V _C. . That is, when using the Modified LSB-FT algorithm, the digital logic unit 130 detects the initialization code corresponding to the upper bits of the control voltage V _C from a preset look-up table, and the control code of the control voltage V _C Can be initialized with

At this time, Table 1 is an example when the output voltage (V _O ) is smaller than the target voltage (V _T ), and when the output voltage (V _O ) is greater than the target voltage (V _T ), the digital logic unit 130 The state of the upper bits of the control voltage (V _C ) is converted, the initialization code corresponding to the converted upper bits is detected from a preset look-up table, and the state of the detected initialization code is converted, and the control voltage (V _C ) It can be initialized with the control code of

For example, when the output voltage (V _O ) is greater than the target voltage (V _T ) and the upper bit of the control voltage (V _C ) is '1101', the digital logic unit 130 is the '1101' of the upper bit. Converts 0'to '1' and '1' to '0', detects the initialization code '001111111' corresponding to the converted high-order bit '0010', and in the detected initialization code '001111111', '0' By converting '1' to '1' and '1' to '0', 110000000' can be initialized with the control code of the control voltage (V _C ).

Next, the setting operation (P2 phase) may be an operation of sequentially setting the control code from the least significant bit to the most significant bit in 0 or 1 depending on whether the output voltage V _O and the target voltage V _T are large or small. .

For example, when the control code is '11011000' and the target voltage (V _T ) is '11100000', the digital logic unit 130 sets '0' to '1' from the least significant bit to the most significant bit of the control code '11011000'. When the control code is changed to '11011011' and the target voltage (V _T ) is '10000000', the setting operation is performed to sequentially change '1' to '0' from the least significant bit to the most significant bit. can do.

According to an embodiment, when the control code is set to one bit whose state is different from the remaining bits, the setting operation of the MODIFIED LSB-FT algorithm is completed, and the setting operation is performed on the lower bits after the other bit. -It can be completed by applying the setting operation of the MSB-FT algorithm, which is the completion operation of the FT algorithm.

Table 2 below is an embodiment for explaining the setting operation of the Modified LSB-FT algorithm.

Number of control code changes
(Counting number) First Embodiment of Modified LSB-FT Algorithm Second Embodiment of Modified LSB-FT Algorithm reset 11011111 00001111 0 11101111 00011111 One 11100111 00101111 2 11100011 00100111 3 11100001 00100011 4 11100000 00100001 5 11100001 00100000 6 00100000 7 8 9

As described in the first embodiment of Table 2, when the control code '11 0 11111' is set to one bit whose state is different from that of the remaining bits, the digital logic unit 130 The MSB-FT algorithm setting operation can be applied from 0 counting times for the lower bits '11111'. That is, when the digital logic unit 130 operates through the Modified LSB-FT algorithm, the setting operation of applying the setting operation of the MSB-FT algorithm is performed after completing the setting operation and comparison operation of the Modified LSB-FT algorithm. , It may mean that it is applied to the completion operation of the Modified LSB-FT algorithm.

Thereafter, the digital logic unit 130 adjusts the control code to the target control voltage (V _TC ) through the MSB-FT algorithm up to the number of counting 5 for the lower bits following the bit set through the setting operation of the MSB-FT algorithm. It may be an operation to do.

According to another embodiment, when the last bit of bits that can change within a preset transition boundary between the control code and the target control voltage (V _TC ) is set in the control code, the setting operation of the Modified LSB-FT algorithm After finishing, the MSB-FT algorithm setting operation, which is the completion operation of the Modified LSB-FT algorithm, can be applied to the lower bits following the last bit.

As described in the first embodiment of Table 2, in the setting operation, bits that can change within a preset transition boundary between the control code and the target control voltage (V _TC ), the last bit of '00 011111 ' When '00 0 11111' is set, the setting operation of the MSB-FT algorithm can be applied to the next lower bits '000 11111 ' of the last bit.

Next, the comparison operation may be an operation of comparing the control code and the target control voltage V _TC when the control code is set through the setting operation in turn for each bit.

For example, if the control code is '11011000' and the target control voltage (V _TC ) is '11100000', when the control code is changed to '11011001', '11011011', '11011111' through the setting operation, digital The logic unit 130 may compare with the target control voltage V _TC '11100000'.

Thereafter, the completion operation is the control code through the MSB-FT algorithm from the lower bit after the bit set through the setting operation to the least significant bit after the bit set through the setting operation when it is determined that the magnitude between the control code and the target control voltage (V _TC ) changes in the comparison operation. It may be an operation of adjusting to the target control voltage (V _TC ).

According to another embodiment, the digital logic unit 130 controls a target through a barrel shifter algorithm in response to a FINE state signal output through the state signal generation unit 120, and controls the control voltage V _C It can be adjusted by voltage (V _TC ).

According to another embodiment, the digital logic unit 130 applies the control voltage V _C to the LSB-FT algorithm (LSB First-Track Algorithm) in response to the MIDDLE status signal output through the status signal generation unit 120. It can be adjusted to the target control voltage (V _TC ) through. Accordingly, the digital logic unit 130 can smoothly convert the control voltage V _C adjusted between the COARSE state and the FINE state through the LSB-FT algorithm (LSB First-Track Algorithm), and DC generated by the dead zone. It can reduce the problem of accuracy.

The digital LDO regulator 10 according to the exemplary embodiment of the present application may detect transition information by comparing the output voltage V _O with at least one reference voltage VREFH1, VREFL1, VREFH2, VREFL2 through the detection unit 110. have. In this case, the digital LDO regulator 10 may output a COARSE state signal based on the transition information and the control voltage through the state signal generator 120. Then, the digital LDO regulator 10 can adjust the control voltage (V _C ) to the target control voltage (V _TC ) through the adaptive SAR algorithm (ASA) corresponding to the COARSE state signal through the digital logic unit 130. have. Accordingly, the digital LDO regulator 10 can further reduce initialization loss and a switching operation of the control voltage V _C generated through the conventional SAR algorithm.

5 is a block diagram of a digital LDO regulator 11 according to another embodiment of the present application, and FIG. 6 is an embodiment of the digital LDO regulator 11 of FIG. 5.

5 and 6, the digital LDO regulator 11 may include a main controller 100, a power array 200, a clock generator 400, and a dynamic comparator 400. Here, since the main controller 100 and the power array 200 have the same functions and configurations as described in FIG. 1, duplicate descriptions are omitted.

First, the dynamic comparator 300 may receive an output voltage V _O through the power array 200 and compare the output voltage V _O with a target voltage V _T. Then, the dynamic comparator 300 may generate an up signal UP or a down signal DN according to a result of comparison between the output voltage V _O and the target voltage V _T. Then, the dynamic comparator 300 may output an up signal UP or a down signal DN to the clock generator 400 and the main controller 100.

Next, the clock generator 400 may generate a clock and provide it to the main controller 100 and the dynamic comparator 400. That is, since the clock generator 400 provides the clock to the dynamic comparator 300, the dynamic comparator 300 responds to the clock, and the output voltage V _O and the target voltage output through the power array 200 ( V _T ) may be periodically compared to output an up signal UP or a down signal DN to the main controller 100 and the clock generator 400. In addition, since the clock generator 400 provides the clock to the main controller 100, the main controller 100 responds to the clock, and the up signal UP for the output voltage V _O from the dynamic comparator 300 Alternatively, the down signal DN may be transmitted, and an output voltage V _O may be output through the power array 200.

7 is a block diagram of a digital LDO regulator 12 according to another embodiment of the present application.

1 to 7, the digital LDO regulator 12 may include a main controller 100, a power array 200, a clock generator 400, and a dynamic comparator 400. Here, since the power array 200, the clock generator 400, and the dynamic comparator 400 have the same functions and configurations as described in FIG. 5, a duplicate description will be omitted.

First, the main controller 100 may further include a counter 140.

Here, the counter 140 may count an up signal UP or a down signal DN output through the dynamic comparator 400.

According to the embodiment, when the digital logic unit 130 adjusts the control voltage V _C through any one of the LSB-FT algorithm and the MSB-FT algorithm, the counter 140 is the digital logic unit 130 After the initialization operation, the number of bit changes can be counted. That is, in the present application, the count operation may mean the number of adjustment operations of the control voltage V _C.

At this time, when the FINE status signal is output to the digital logic unit 130, and either of the up signal (UP) or the down signal (DN) output through the dynamic comparator 400 is continuously counted more than a preset number of times, The state signal generator 120 may convert the FINE state signal to a MIDDLE state signal and output the MIDDLE state signal to the digital logic unit 130.

8 is an embodiment of the detection unit 110 of FIG. 1.

Referring to FIG. 8, the detection unit 110 may include a first detection unit 111 and a second detection unit 112, a delay unit 113 and a determination unit 114.

First, the first detection unit 111 may include a pair of static comparators 111_1 and 111_2, a pair of flip-flops 111_3 and 111_4, and a first OR gate 111_5.

More specifically, the pair of static comparators 111_1 and 111_2 compares the first pair of reference voltages VREFH1 and VREFL1 with the output voltage V _O , and outputs an output signal corresponding to the comparison result as a pair of flip-flops 111_3 , 111_4). Here, the output signal corresponding to the comparison result may be the first crossing point T1 of the dead zone crossing information for the output voltage V _O. That is, the pair of static comparators 111_1 and 111_2 compares the output voltage V _O and the first dead zone formed by the first pair of reference voltages VREFH1 and VREFL1, and the dead zone for the output voltage V _O It may be a static comparator that detects a first intersection point T1 of zone crossing information.

At this time, the pair of flip-flops 111_3 and 111_4 receives a preset voltage as an input signal and receives the output signal output through the pair of static comparators 111_1 and 111_2 as a trigger signal, and the output value is first ORed. It can be transmitted to the gate 111_5.

Then, the first OR gate 111_5 is at the first crossing point T1 of the deadzone crossing information for the output voltage V _O detected through any one of the pair of static comparators 111_1 and 111_2. Based on this, the operation signal VA may be output. Here, the operation signal VA may be a signal for operating the second detection unit 112, the delay unit 113, and the determination unit 114. That is, the first detection unit 111 may generate the operation signal VA at the first intersection point T1 of the dead zone crossing information.

That is, when the output voltage V _O is out of the first dead zone formed through the first pair of reference voltages VREFH1 and VREFL1, the first detection unit 111 operates through a pair of static comparators 111_1 and 111_2. The signal VA can be output.

Next, the second detection unit 112 may include a pair of dynamic comparators 112_1 and 112_2 and a second OR gate 112_3.

First, the pair of dynamic comparators 112_1 and 112_2 compares the second pair of reference voltages VREFH2 and VREFL2 with the output voltage V _O in response to the operation signal VA, and an output signal corresponding to the comparison result (D2) may be output to the second OR gate 112_3.

Here, the output signal D2 corresponding to the comparison result may be a second intersection point T2 of dead zone crossing information with respect to the output voltage V _O. That is, the pair of dynamic comparators 112_1 and 112_2 compares the output voltage V _O with the first pair of reference voltages VREFH1 and VREFL1, and the second crossing of the dead zone crossing information for the output voltage V _O The time point T2 can be detected. Accordingly, the pair of dynamic comparators 112_1 and 112_2 compares the output voltage V _O with the second pair of reference voltages VREFH2 and VREFL2, and the second crossing of the dead zone crossing information for the output voltage V _O By replacing a pair of static comparators that detect the time point T2, power consumption can be reduced.

More specifically, the pair of dynamic comparators 112_1 and 112_2 is based on the clock signal CLK according to the difference between the output voltage V _O and the reference voltage of any one of the first pair of reference voltages VREFH1 and VREFL1. As a result, it may be a dynamic comparator in which the delay of the output signal D2 is different. For example, when the difference between the output voltage V _O and the reference voltage of any one of the first pair of reference voltages VREFH1 and VREFL1 is large, the delay of the output signal D2 becomes short and the output voltage V _O ) And the first pair of reference voltages VREFH1 and VREFL1, if the difference between one of the reference voltages is small, the delay of the output signal D2 may increase. That is, the pair of dynamic comparators 112_1 and 112_2 receives the operation signal VA as the clock signal CLK, compares the output voltage V _O with the first pair of reference voltages VREFH1 and VREFL1, and compares According to the difference, the second crossing point T2 of the dead zone crossing information for the output voltage V _{O at} which the delay of the output signal D2 is different based on the operation signal VA may be detected.

Then, the second OR gate 112_3 is a second intersection point T2 of dead zone crossing information for the output voltage V _O detected through any one of the pair of dynamic comparators 112_1 and 112_2 On the basis of, it is possible to generate and output the rising pulse VD2. Here, the rising pulse VD2 may be a signal delayed for a predetermined time from the operation signal VA. That is, the second detection unit 112 may generate the rising pulse VD2 at the second intersection point T2 of the dead zone crossing information.

Meanwhile, as shown in FIG. 1, when the FINE status signal is output to the digital logic unit 130 through the status signal generation unit 120 and the operation signal VA is generated through the first detection unit 111 , The state signal generator 120 may transmit the COARSE state signal to the digital logic unit 130 by transitioning the FINE state signal to the COARSE state signal at the first crossing point T1 of the dead zone crossing information.

Referring back to FIG. 8, the delay unit 113 may include a plurality of delay cells 113_11 to 113_1N and a capacitor array 113_2.

First, the plurality of delay cells 113_11 to 113_1N digitally delay the operation signal VA output through the first detection unit 111 to output the delay signal VD1 for the operation signal VA. have. In this case, the capacitor array 113_2 is located between the plurality of delay cells 113_11 to 113_1N, and the degree of delay of the delay signal VD1 with respect to the operation signal VA may be adjusted.

That is, the delay unit 113 digitally delays the operation signal VA output through the first detection unit 111 through the plurality of delay cells 113_11 to 113_1N and the capacitor array 113_2 to provide a delay signal VD1. ) Can be created.

Thereafter, the determination unit 114 includes a D flip-flop 114_1, is electrically connected to the second detection unit 112 and the delay unit 113, and receives the delay signal VD1 and the rising pulse VD2. I can. At this time, the D flip-flop 114_1 receives the delay signal VD1 as an input signal, receives the rising pulse VD2 as a trigger signal, and receives the output signal 1 or the output signal corresponding to the slope information for the output voltage V _O. 0) can be output.

In this way, the determination unit 114 may determine slope information for the output voltage V _O based on the delay signal VD1 and the rising pulse VD2. For example, when the output signal output through the D flip-flop 114_1 is 0, the determination unit 114 may determine the slope information of the output voltage V _O as a heavy transition state. In addition, when the output signal output through the flip-flop 114_1 is 1, the determination unit 114 may determine the slope information of the output voltage V _O as a mild transition state.

That is, the detection unit 110 detects the first crossing point T1 through the first detection unit 111 and the second crossing point T2 through the second detection unit 112 to obtain dead zone crossing information. Can be detected. In addition, the detection unit 110 may output an output signal corresponding to the slope information of the output voltage V _O as 1 or 0 through the determination unit 114. Thus, detector 110 output voltage (V _O) and at least one reference voltage (VREFH1, VREFL1, VREFH2, VREFL2) and to the output voltage (V _O), the dead zone crossing information and the output voltage (V _O for comparison Transition information including slope information for) may be detected.

9 is an operation process of the digital LDO regulator 10 according to an embodiment of the present application.

Referring to FIGS. 1 to 9, first, in step S110, the power array 200 may output an output voltage V _O based on a control voltage V _C applied from the main controller.

In this case, in step S120, the detection unit 110 may detect transition information by comparing the output voltage V _O with at least one reference voltage VREFH1, VREFL1, VREFH2, and VREFL2.

Then, in step S130, the state signal generator 120 may output one of COARSE, FINE, and MIDDLE based on the transition information and the control voltage V _C.

Thereafter, in step S140, the digital logic unit 130 adjusts the control voltage V _C to the target control voltage V _TC through an algorithm corresponding to one state signal, and outputs it to the power array 200. have.

10 is an operation process of the digital LDO regulator 11 of FIG. 5.

Referring to FIGS. 1 to 10, first, in step S210, the clock generator 400 may generate a clock and provide it to the main controller 100 and the dynamic comparator 300.

In this case, in step S220, the main controller 100 may receive a clock and apply a preset control voltage V _C to the power array 200.

Then, in step S230, the power array 200 in response to the control voltage (V _C ) applied from the main controller 100, the output voltage (V _O ) and the detection unit 110 of the main controller 100 It can be output to the comparator 300.

Then, in step S240, the dynamic comparator 300 is provided with a clock and compares the output voltage (V _O ) and the target output voltage (VT) to obtain either an up signal (UP) or a down signal (DN). It may be output to the clock generator 400 and the main controller 100. In this case, the clock generator 400 may adjust the phase of the clock according to any one signal.

At this time, in step S250, the detection unit 110 responds to any one of the up signal UP or the down signal DN, the output voltage V _O and at least one reference voltage VREFH1, VREFL1, VREFH2, VREFL2) can be compared and transition information can be detected.

Then, in step S260, the state signal generator 120 may output one of COARSE, FINE, and MIDDLE based on the transition information and the control voltage V _C.

Then, in step S270, when receiving the CCOARSE state signal through the state signal generator 120, the digital logic unit 130 may select an adaptive SAR algorithm (ASA) corresponding to the CCOARSE state signal.

At this time, in step S280, the digital logic unit 130 determines whether the transition information output through the detection unit 11 is a heavy transition state or a mild transition state, and according to the transition information, the MSB-FT algorithm and the MODIFIED LSB- The control voltage (V _C ) can be adjusted to the target control voltage (V _TC ) through any one of the FT algorithms.

According to an embodiment, when it is determined that the transition information is in the heavy transition state, the digital logic unit 130 sequentially performs an initialization operation, a comparison operation, a setting operation and a completion operation of the MSB-FT algorithm with respect to the control voltage V _C. Can be adjusted to the target control voltage (V _TC ).

According to another embodiment, when the transition information is determined to be in the mild transition state, the digital logic unit 130 performs an initialization operation, a setting operation, a comparison operation, and a completion operation of the MODIFIED LSB-FT algorithm with respect to the control voltage V _C. It can be performed sequentially, and can be adjusted to the target control voltage (V _TC ).

Thereafter, in step S290, the power array 200 may output a regulated output voltage V _O based on the control voltage V _C adjusted through the digital logic unit 130.

11 is an operation process according to the embodiment of the detection unit 110 of FIG. 5.

1 to 11, first, in step S310, the first detection unit 111 detects the first intersection point T of the dead zone crossing information, and the operation signal VA at the first intersection point T. ) Can be created.

Then, in step S320, in response to the operation signal, the second detection unit 112 detects the second intersection point T2 of the dead zone crossing information, and generates a rising pulse VD2 at the second intersection point T2. Can be generated.

In this case, in step S330, the delay unit 113 may digitally delay the operation signal through the delay cells 113_11 to 113_1N and the capacitor array 113_2 to generate a delay signal VD1.

Thereafter, in step S340, the determination unit 114 may determine slope information of the output voltage V _O based on the delay signal VD1 and the rising pulse VD2. Here, the slope information for the output voltage V _O may correspond to either a mild transition state or a heavy transition state.

Although the present application has been described with reference to an exemplary embodiment illustrated in the drawings, this is only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other exemplary embodiments are possible therefrom. Therefore, the true technical protection scope of the present application should be determined by the technical idea of the attached registration claims.

10, 11, 12: digital LDO regulator
100: main controller
110: detection unit
120: status signal generator
130: digital logic unit
140: counter
200: power array
300: dynamic comparator
400: clock generator

Claims (20)

Main controller; And
And a power array that outputs an output voltage based on a control voltage applied from the main controller,
The main controller may include: a detector configured to compare the output voltage with at least one reference voltage to detect transition information for the output voltage;
A status signal generator for outputting one of COARSE, FINE, and MIDDLE based on the transition information and the control voltage; And
In response to the COARSE state signal, comprising a digital logic unit for adjusting the control voltage through an adaptive SAR algorithm,
The adaptive SAR algorithm is a digital LDO regulator to which one of an MSB-FT algorithm and a MODIFIED LSB-FT algorithm is selectively applied according to the transition information. The method of claim 1,
The digital logic unit, in response to the FINE state signal, a digital LDO regulator to adjust the control voltage through a barrel shifter algorithm. The method of claim 1,
The digital logic unit is a digital LDO regulator that adjusts the control voltage through an LSB-FT algorithm in response to the MIDDLE state signal. The method of claim 1,
The transition information includes dead zone crossing information and slope information for the output voltage,
The dead zone crossing information corresponds to time information at which the output voltage and the at least one reference voltage cross each other,
The slope information is a digital LDO regulator corresponding to any one of a heavy transition state and a mild transition state determined according to the dead zone crossing information. The method of claim 1,
When the transition information is in a heavy transition state, the digital logic unit sequentially performs an initialization operation, a comparison operation, a setting operation and a completion operation of the MSB-FT algorithm with respect to the control voltage,
When the transition information is in a mild transition state, the digital LDO regulator sequentially performs an initialization operation, a setting operation, a comparison operation, and a completion operation of the MODIFIED LSB-FT algorithm with the control voltage. The method of claim 5,
The digital logic unit, based on the transition information, detects a preset code corresponding to upper bits of the control voltage from a preset lookup table and performs the initialization operation. The method of claim 5,
The digital logic unit finishes the setting operation of the MODIFIED LSB-FT algorithm when a bit having a different state from the remaining bits of the control voltage is set during the setting operation of the MODIFIED LSB-FT algorithm,
A digital LDO regulator performing a setting operation of the MSB-FT algorithm, which is a completion operation of the MODIFIED LSB-FT algorithm, for lower bits after the other bit. The method of claim 5,
When the last bit of bits that can change within a preset transition boundary between the control voltage and the target control voltage is set in the control voltage, the digital logic unit finishes the setting operation of the MODIFIED LSB-FT algorithm, and the last bit A digital LDO regulator that performs the setting operation of the MSB-FT algorithm for the next lower bits of. The method of claim 6,
A clock generator for generating a clock; And
Further comprising a dynamic comparator for receiving the clock, comparing the output voltage and the target output voltage to output an up signal or a down signal,
The main controller further includes a counter receiving the clock and counting the up signal or the down signal,
The counter is a digital LDO regulator that counts the number of bit changes to the control voltage after the initialization operation. The method of claim 9,
The status signal generation unit, when the FINE status signal is output, and any one of the up signal or the down signal is continuously counted more than a preset number of times,
A digital LDO regulator that transitions the FINE state signal to the MIDDLE state signal and outputs it to the digital logic unit. The method of claim 4,
The detection unit may include: a first detection unit detecting a first intersection point of the dead zone crossing information and generating an operation signal at the first intersection point;
A second detection unit detecting a second intersection point of the dead zone crossing information in response to the operation signal and generating a rising pulse at the second intersection point;
A delay unit for generating a delay signal by digitally delaying the operation signal through delay cells and capacitor arrays; And
A digital LDO regulator including a determination unit determining slope information of the output voltage based on the delay signal and the rising pulse. The method of claim 11,
When the FINE state signal is output, the state signal generator converts the FINE state signal to the COARSE state signal at the first crossing point and outputs the transition to the COARSE state signal to the digital LDO regulator. The method of claim 11,
The first detection unit, a digital LDO regulator including a pair of static comparators for comparing the at least one reference voltage and the output voltage. The method of claim 11,
The second detection unit, in response to the operation signal, a digital LDO regulator including a pair of dynamic comparators for comparing the output voltage and the at least one reference voltage. The method of claim 11,
The determination unit is a digital LDO regulator including a D flip-flop receiving the delay signal as an input signal and the rising pulse as a trigger signal. As a method of operating a digital LDO regulator including a power array and a main controller,
Outputting, by the power array, an output voltage based on a control voltage applied from the main controller;
Detecting, by the main controller, transition information by comparing the output voltage with at least one reference voltage;
Outputting, by the main controller, a status signal of one of COARSE, MIDDLE, and FINE status signals based on the transition information and a control voltage; And
And the main controller adjusting the control voltage to a target control voltage through an algorithm corresponding to the one state signal. The method of claim 16,
The adjusting may include: when the main controller receives the COARSE state signal, selecting an adaptive SAR algorithm for the control voltage; And
And adjusting, by the main controller, the control voltage through one of an MSB-FT algorithm and a MODIFIED LSB-FT algorithm according to the transition information. The method of claim 16,
The adjusting comprises, when the main controller receives the FINE state signal, adjusting the control voltage through a barrel shifter algorithm. The method of claim 16,
The adjusting includes, when the main controller receives the MIDDLE status signal, adjusting the control voltage through an LSB-FT algorithm. The method of claim 16,
The detecting of the transition information may include detecting a first intersection point of dead zone crossing information by comparing the output voltage and the at least one reference voltage, and generating an operation signal at the first intersection point;
Detecting a second crossing point of the dead zone crossing information by comparing the output voltage and the at least one reference voltage in response to the operation signal, and generating a rising pulse at the second crossing point;
Generating a delay signal by digitally delaying the operation signal through delay cells and capacitor arrays; And
And determining slope information of the output voltage based on the delay signal and the rising pulse.

Images