KR102538241B1 - Hybrid Low-Dropout Regulator - Google Patents

Abstract

The present invention provides an analog low dropout voltage regulator that supplies an output voltage obtained by adjusting an input voltage to a load, and the output voltage is set based on a switch voltage of the analog low dropout voltage regulator and a feedback voltage corresponding to the output voltage. A hybrid low dropout voltage regulator including a digital low dropout voltage regulator for supplying a digital current to the load to fall within a reference voltage range.

Description

Hybrid Low-Dropout Voltage Regulator

The present invention relates to a hybrid low dropout voltage regulator, and more particularly, to a hybrid low dropout voltage regulator combining an analog low dropout voltage regulator and a digital low dropout voltage regulator.

Recently, with the trend of diversification and miniaturization of devices, efforts to integrate various circuits into a single chip (System-On-Chip) are increasing. For example, various circuits such as analog, digital, and RF are being gathered into one chip.

In this way, as various circuits are integrated into one chip, an efficient and stable power supply voltage management system is required.

The LDO regulator (LOW DROP-OUT REGULATOR) is one of the essential elements in the power supply voltage management system and is used to supply stable power supply voltage to these circuits. To this end, LDO regulators are used together with switching regulators. LDO regulators are mainly used to supply power supply voltages for circuits such as ADCs and VCOs that are sensitive to supply voltages, as they require little external circuitry, are simple, and do not have self-generated ripple.

On the other hand, the analog LDO regulator cannot lower the power supply voltage due to the use of an amplifier, and has difficulty in setting a large bandwidth for high-speed operation. In contrast, digital LDO regulators do not use an amplifier, so the power supply voltage can be greatly reduced, and they have a bandwidth close to infinity, so they are easy to perform high-speed operation.

Digital LDO regulators can achieve very low dropout voltages because the pass transistor operates in OFF and linear (resistive) mode.

However, digital LDO regulators can often have low power supply rejection (PSR) and large output ripple.

Recently, a method of improving load response characteristics and power efficiency by mixing an analog LDO regulator and a digital LDO has been studied.

It is an object of the present invention to provide a hybrid low dropout voltage regulator in which an analog low dropout voltage regulator and a digital low dropout voltage regulator are mixed.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

A hybrid low dropout voltage regulator according to the present invention includes an analog low dropout voltage regulator supplying an output voltage obtained by adjusting an input voltage to a load, a switch voltage of the analog low dropout voltage regulator, and a feedback voltage corresponding to the output voltage. It may include a digital low dropout voltage regulator for supplying a digital current to the load so that the output voltage falls within a set reference voltage range based on .

The analog low dropout voltage regulator may include a pass transistor that adjusts the input voltage to the output voltage and an error amplifier that supplies the switch voltage obtained by comparing the output voltage and a reference voltage to the pass transistor.

The digital low dropout voltage regulator includes a plurality of small pass transistors supplying the digital current to the load and a digital controller controlling the plurality of small pass transistors based on the switch voltage, the output voltage, and the reference voltage range. can include

The digital controller may include a clock generator configured to generate first and second clock signals and first and second error signals according to whether the output voltage falls within the reference voltage range; A reset counter generating first and second reset signals based on 2 error signals, an ADC (Analog-Digital ADC) outputting an error code based on the switch voltage, the lower limit voltage of the reference voltage range, and the first and second clock signals. Converter) and the error code, the first and second clock signals, and the first and second reset signals to generate a switch signal corresponding to the error code and supply it to the plurality of small pass transistors. ) may be included.

The clock generator may generate the first clock signal and the first error signal when the output voltage falls within the reference voltage range and the second clock signal and the second error signal when the output voltage does not fall within the reference voltage range. there is.

The reset counter generates the first reset signal to inactivate the plurality of small pass transistors when the first clock signal and the first error signal are input, and the second clock signal and the second error signal When is input, the second reset signal may be generated so that the plurality of small pass transistors are activated.

The ADC outputs an inactive error code when the first clock signal is input, and generates an active error code for controlling the digital current based on the switch voltage and the lower limit voltage when the second clock signal is input. can be printed out.

The FSM deactivates the plurality of small pass transistors when the first clock signal and the inactive error code are input, and corresponds to the active error code when the second clock signal and the active error code are input. The switch signal may be generated to activate the plurality of small pass transistors.

The hybrid low dropout voltage regulator according to the present invention combines an analog low dropout voltage regulator and a digital low dropout voltage regulator to improve high PSR and load response characteristics for high current, low quiescent current and high efficiency. There are advantages to having.

The hybrid low-dropout voltage regulator according to the present invention has the advantages of strict regulation and wide load current range of the analog control method and the advantage of efficiently utilizing transistors in the fast transient speed region of the digital control method.

The hybrid low dropout voltage regulator according to the present invention has the advantage of using a clock generator to detect a change in output voltage due to lack of current supplied to a load and to control a plurality of small pass transistors using a clock signal. there is.

On the other hand, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range apparent to those skilled in the art from the contents to be described below.

1 is a circuit diagram showing the circuit configuration of a hybrid low dropout voltage regulator according to the present invention.
2 is a circuit diagram illustrating the digital low dropout voltage regulator shown in FIG. 1;
FIG. 3 is a circuit diagram showing a detailed configuration of the clock generator shown in FIG. 2 .
FIG. 4 is a timing diagram illustrating the error signal shown in FIG. 2 .
FIG. 5 is a timing diagram schematically illustrating signals generated by the digital low dropout voltage regulator shown in FIG. 1 .

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals have been used for like elements throughout the description of each figure.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. The terms and/or include any combination of a plurality of related recited items or any of a plurality of related recited items.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, they should not be interpreted in an ideal or excessively formal meaning. don't Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing the circuit configuration of a hybrid low dropout voltage regulator according to the present invention, FIG. 2 is a circuit diagram showing the digital low dropout voltage regulator shown in FIG. 1, and FIG. 3 is a detailed configuration of the clock generator shown in FIG. 4 is a timing diagram showing the error signal shown in FIG. 2 and FIG. 5 is a timing diagram briefly showing signals generated by the digital low dropout voltage regulator shown in FIG.

1 to 5, the hybrid low dropout voltage regulator 100 includes an analog low dropout voltage regulator (hereinafter referred to as a “first LDO” 110) and a digital low dropout voltage regulator (hereinafter referred to as a “second LDO”). 2 LDO", 120).

The first LDO 110 may include a pass transistor PT and an error amplifier EA.

The pass transistor PT may receive the switch voltage Vg for outputting the output voltage Vo by adjusting the input voltage Vdd.

That is, the voltage level of the output voltage Vo may correspond to the magnitude of the switch voltage Vg.

The pass transistor PT may be implemented as a p-type transistor such as a p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET), but is not limited thereto.

The error amplifier (EA) may receive a reference voltage (Vm) and an output voltage (Vo) through an inverting terminal (-) and a non-inverting terminal (+), respectively, and compare the reference voltage (Vm) and the output voltage (Vo). there is.

The error amplifier EA may supply the switch voltage Vg to the pass transistor PT according to the comparison result, and the switch voltage Vg may control the switching operation of the pass transistor PT.

The switch voltage Vg may include information about a change in the output voltage Vo. That is, the switch voltage Vg changes according to the change of the output voltage Vo, and the error amplifier EA generates the switch voltage Vg according to the change of the output voltage Vo.

For example, when the output voltage Vo is less than the reference voltage Vm, the switch voltage Vg of the error amplifier EA may control the pass transistor PT so that the voltage level of the output voltage Vo increases. .

When the output voltage Vo is greater than the reference voltage Vm, the switch voltage Vg of the error amplifier EA may control the pass transistor PT so that the voltage level of the output voltage Vo decreases.

Accordingly, the pass transistor PT may change the voltage level of the output voltage Vo to stabilize the output voltage Vo in response to the switch voltage Vg.

The second LDO 120 may include a plurality of small pass transistors (pt) and a digital controller (D.C).

The plurality of small pass transistors pt may perform a switching operation according to a switch signal supplied from the digital controller D.C.

That is, the plurality of small pass transistors pt may compensate for undershoot and overshoot of the output voltage Vo.

A plurality of small pass transistors pt may be connected in parallel with each other, and at least one of them may perform a switching operation by the switch signal, but is not limited thereto.

Referring to FIG. 2 , the digital controller (D.C) may include a clock generator 122, a reset counter 124, an Analog-Digital Converter (ADC) 126, and a Finite State Machine (FSM) 128.

First, the clock generator 122 may generate first and second clock signals CLK and first and second error signals EN according to whether the output voltage Vo falls within the reference voltage range.

That is, the clock generator 122 outputs the first clock signal and the first error signal when the output voltage Vo falls within the reference voltage range and the second clock signal and the second error signal when the output voltage Vo does not fall within the reference voltage range. signal can be generated.

Here, the clock generator 122 includes a ring oscillator that compares the lower limit voltage Vl of the reference voltage range and the output voltage Vo, and the upper limit voltage Vh of the reference voltage range and the output voltage Vo, as shown in FIG. It may include a ring oscillator that compares.

The first and second error signals EN can be briefly shown in FIG. 4 .

That is, the first and second error signals EN may be output in different binary codes depending on whether the output voltage Vo belongs to the reference voltage range, but is not limited thereto.

The reset counter 124 may generate first and second reset signals RST based on the first and second clock signals and the first and second error signals.

That is, when the first clock signal and the first error signal are input, the reset counter 124 generates a first reset signal to inactivate a plurality of small pass transistors pt, and generates a second clock signal and the first error signal. When the second error signal is input, the second reset signal may be generated so that the plurality of small pass transistors pt are activated.

The ADC 126 may output an error code based on the switch voltage, the lower limit voltage of the reference voltage range, and the first and second clock signals.

That is, the ADC 126 outputs an inactive error code when the first clock signal is input, and controls the digital current based on the switch voltage and the lower limit voltage when the second clock signal is input. Error codes can be output.

The FSM 128 may generate a switch signal corresponding to the error code based on the error code, the first and second clock signals, and the first and second reset signals, and supply the generated switch signal to a plurality of small pass transistors (pt). .

That is, the FSM 128 deactivates the plurality of small pass transistors pt when the first clock signal and the inactive error code are input, and when the second clock signal and the active error code are input, The switch signal corresponding to the active error code may be generated and the switch signal may be output so that the plurality of small pass transistors pt are activated.

Features, structures, effects, etc. described in the embodiments above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified with respect to other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to these combinations and variations should be construed as being included in the scope of the present invention.

In addition, although the above has been described with reference to the embodiments, these are only examples and do not limit the present invention, and those skilled in the art to which the present invention belongs can exemplify the above to the extent that does not deviate from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications that have not been made are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention as defined in the appended claims.

Claims (8)

an analog low-dropout voltage regulator that supplies an output voltage regulated by an input voltage to a load; and
A digital low dropout voltage regulator for supplying a digital current to the load so that the output voltage falls within a set reference voltage range based on a switch voltage of the analog low dropout voltage regulator and a feedback voltage corresponding to the output voltage; ,
The digital low dropout voltage regulator,
a plurality of small pass transistors supplying the digital current to the load; and
A digital controller controlling the plurality of small pass transistors based on the switch voltage, the output voltage, and the reference voltage range;
The digital controller,
a clock generator configured to generate first and second clock signals and first and second error signals according to whether the output voltage falls within the reference voltage range;
a reset counter generating first and second reset signals based on the first and second clock signals and the first and second error signals;
an ADC (Analog-Digital Converter) outputting an error code based on the switch voltage, the lower limit voltage of the reference voltage range, and the first and second clock signals; and
A finite state machine (FSM) generating a switch signal corresponding to the error code based on the error code, the first and second clock signals, and the first and second reset signals and supplying the switch signal to the plurality of small pass transistors doing,
Hybrid low-dropout voltage regulator. According to claim 1,
The analog low dropout voltage regulator,
a pass transistor for adjusting the input voltage to the output voltage; and
And an error amplifier supplying the switch voltage obtained by comparing the output voltage and the reference voltage to the pass transistor.
Hybrid low-dropout voltage regulator. delete delete According to claim 1,
The clock generator,
generating the first clock signal and the first error signal and the second clock signal and the second error signal when the output voltage does not fall within the reference voltage range;
Hybrid low-dropout voltage regulator. According to claim 1,
The reset counter is
generating the first reset signal to inactivate the plurality of small pass transistors when the first clock signal and the first error signal are input;
generating the second reset signal so that the plurality of small pass transistors are activated when the second clock signal and the second error signal are input;
Hybrid low-dropout voltage regulator. According to claim 1,
The ADC,
Outputting an inactive error code when the first clock signal is input, and outputting an active error code for controlling the digital current based on the switch voltage and the lower limit voltage when the second clock signal is input.
Hybrid low-dropout voltage regulator. According to claim 7,
The FSM is
inactivating the plurality of small pass transistors when the first clock signal and the inactivation error code are input;
generating the switch signal corresponding to the active error code when the second clock signal and the active error code are input, and outputting the switch signal to activate the plurality of small pass transistors;
Hybrid low-dropout voltage regulator.

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