KR102609484B1 - Hybrid ldo regulator using operational trans-conductance amplifier - Google Patents

Abstract

The LDO regulator, which converts the power supply voltage and provides it as an output voltage according to an embodiment of the present invention, detects an offset by comparing the first and second reference voltages and the output voltage in synchronization with a clock signal, and outputs an offset detection signal. a dynamic comparator, a calibration circuit that generates an offset control signal for compensating for the offset in response to the offset detection signal, a first operational transconductance amplifier that generates a first gate voltage in accordance with the offset control signal, and the offset control a second operational transconductance amplifier that generates a second gate voltage according to a signal, a first pass transistor that delivers the power supply voltage to an output terminal according to the first gate voltage, and a first pass transistor that delivers the power supply voltage according to the second gate voltage a second pass transistor, a first loop switch connecting the second pass transistor and the output terminal in response to a first enable signal, and comparing the output voltage with a third reference voltage, and the second gate voltage It includes a digital control unit that detects the level and generates the first enable signal.

Description

Hybrid LDO regulator using operational trans-conductance amplifier {HYBRID LDO REGULATOR USING OPERATIONAL TRANS-CONDUCTANCE AMPLIFIER}

The present invention relates to semiconductor devices, and more particularly to a hybrid LDO regulator using three operational trans-conductance amplifiers (OTAs).

Typically, integrated circuits are designed to operate at a specific range of power supply voltages. However, in the environment in which the actual circuit operates, various variables exist, such as a voltage higher than the power supply voltage set at the time of design being supplied or noise flowing into the power supply voltage due to external factors. To solve this problem, a voltage regulator is used, which supplies a constant power voltage to the integrated circuit. Low-Dropout (LDO) regulators, a representative linear regulator, lose energy equal to the voltage drop, so they are mainly used when the difference between the input voltage and output voltage is not large.

The LDO regulator consists of an analog error amplifier, pass transistor, and feedback network. The error amplifier detects the error between the output voltage (Vout) and the reference voltage (V _REF ) and controls the pass transistor to reduce the error between the two voltages according to the negative feedback structure. Error amplifier-based analog LDOs have a relatively high operating voltage range and have the disadvantage of being difficult to apply to analog and digital circuits that operate at fast frequencies due to their limited operating bandwidth. In addition, as the current capacity increases, the size of the pass transistor that the error amplifier must control increases, and accordingly, there is a problem that the operating bandwidth or stability due to voice feedback is reduced. To solve this problem, technologies for digital LDOs implemented with comparators and shift registers are being actively proposed.

A typical analog LDO regulator tends not to lower the input voltage to ensure good performance because the performance of the error amplifier indicates the performance of the analog LDO regulator. In addition, when the input voltage is low, not only does the circuit of the analog LDO regulator have difficulty regulating to the desired voltage, but the power supply rejection ratio (PSRR) is low, making it difficult to eliminate the voltage ripple of the input power supply. Since the speed of the circuit and the gain of the amplifier have a trade-off relationship, as the voltage gain of the amplifier increases and the performance improves, the transient response speed becomes relatively low. In other words, the performance of the analog amplifier circuit is dependent on the input power, so there are many limitations to its use in low input voltage conditions.

(1) Korean Patent Publication 10-2020-0054008 (2020.05.19) (2) Korean Patent Publication 10-2021-0024863 (2021.03.08)

The purpose of the present invention is to solve the above-mentioned problems and to provide an LDO regulator that can provide fast transient response and high power supply ripple rejection performance even under low power supply voltage conditions.

The LDO regulator, which converts the power supply voltage and provides it as an output voltage according to an embodiment of the present invention, detects an offset by comparing the first and second reference voltages and the output voltage in synchronization with a clock signal, and provides an offset detection signal. A dynamic comparator that outputs, a calibration circuit that generates an offset control signal for compensating for the offset in response to the offset detection signal, a first operational trans-conductance amplifier that generates a first gate voltage in accordance with the offset control signal, and the offset A second operational trans-conductance amplifier that generates a second gate voltage according to the control signal, a first pass transistor that delivers the power supply voltage to an output terminal according to the first gate voltage, and a first pass transistor that delivers the power supply voltage to the output terminal according to the second gate voltage. a second pass transistor that transmits, a first loop switch that connects the second pass transistor and the output terminal in response to a first enable signal, and compares the output voltage with a third reference voltage, and the second gate voltage It includes a digital control unit that detects the level of and generates the first enable signal.

In this embodiment, the dynamic comparator includes a first dynamic comparator that generates a first offset detection signal that is activated when the level of the output voltage is higher than the first reference voltage, and the dynamic comparator generates a first offset detection signal that is activated when the level of the output voltage is higher than the first reference voltage. and a second dynamic comparator that generates a second offset detection signal that is activated when the second reference voltage is lower than the reference voltage.

In this embodiment, the calibration circuit includes a bidirectional shift register that generates a multi-bit offset control signal whose ratio of logic '1' and logic '0' is adjusted according to the first and second offset detection signals. .

In this embodiment, the offset control signal includes a first offset control signal provided to the first operational trans-conductance amplifier and a second offset control signal provided to the second operational trans-conductance amplifier, wherein the first offset control signal is provided to the first operational trans-conductance amplifier. The number of bits of the offset control signal and the second offset control signal are different.

In this embodiment, the first operational trans-conductance amplifier and each of the positive and negative input terminals of the first operational trans-conductance amplifier are connected in parallel and switched by the first offset control signal and the second offset control signal. Includes a plurality of input transistors.

In this embodiment, the channel size of the first pass transistor is smaller than the channel size of the second pass transistor.

In this embodiment, a third operational trans-conductance amplifier to generate a third gate voltage according to the offset control signal, a third pass transistor to deliver the power supply voltage according to the third gate voltage, and a second enable signal. In response, it further includes a second loop switch connecting the third pass transistor and the output terminal.

In this embodiment, the channel size of the third pass transistor is larger than the channel size of the second pass transistor.

In this embodiment, the digital control unit includes an output voltage comparator that compares the output voltage and the third reference voltage, a first comparator that compares the second gate voltage and the fourth reference voltage, and the third gate voltage. It includes a second comparator for comparison with a fourth reference voltage, and a mode controller for controlling the first loop switch and the second loop switch based on the output voltage comparator and the outputs of the first and second comparators.

According to an embodiment of the present invention, the mode controller turns on the second loop switch when the output voltage is lower than the third reference voltage.

According to the above-described embodiment of the present invention, an LDO regulator with fast transient response and high power ripple rejection performance even under low power supply voltage conditions is provided. In addition, it is possible to design a circuit with relatively high PSRR by using an analog LDO that can be regulated through negative feedback. In addition, by implementing a background calibration loop, offsets due to PVT fluctuations within the circuit can be independently detected and compensated, thereby minimizing the cost for offset compensation and improving integration.

1 is a circuit diagram showing the structure of a hybrid LDO regulator according to an embodiment of the present invention.
Figures 2 and 3 are circuit diagrams exemplarily showing the configuration of the dynamic comparators of Figure 1.
Figure 4 is a block diagram showing an exemplary configuration of a calibration circuit according to an embodiment of the present invention.
FIGS. 5A and 5B are diagrams exemplarily showing the configuration of a unit register that generates the offset control signals (Q ₁ to Q _k , Q _k+1 to Q _2k ) of FIG. 4 .
Figure 6 is a block diagram showing the configuration of each background calibration loop.
FIG. 7 is a circuit diagram exemplarily showing the structure of the third operational transconductance amplifier (OTA _L ) of FIG. 6.
FIG. 8 is a circuit diagram showing the input transistor of FIG. 7 in more detail.
Figure 9 is a diagram briefly showing a shift method of offset control signals (Q ₁ to Q _2k ) for controlling the input transistors of the operational transconductance amplifier (OTA) of the present invention.
Figure 10 is a graph showing the effect of the background calibration loop of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

1 is a circuit diagram showing the structure of a hybrid LDO regulator according to an embodiment of the present invention. Referring to FIG. 1, the hybrid LDO regulator 100 includes dynamic comparators 110 and 115, a calibration circuit 120, a small loop 130, a medium loop 140, a large loop 150, and an output voltage comparator 160. ), gate voltage comparators (170, 175), a mode controller (180), and a large loop switch (190) and medium loop switch (195).

Here, the dynamic comparators 110 and 115, the calibration circuit 120, and the background calibration loops 130, 140, and 150 constitute an analog loop. On the other hand, the output voltage comparator 160, gate voltage comparator 170, 175, mode controller 180, large loop switch 190, and medium loop switch 195 constitute a digital loop.

The dynamic comparators 110 and 115 are synchronous comparators that constitute the input terminal of the calibration circuit 120. The dynamic comparators 110 and 115 are synchronized with the clock signal CLK and compare the preset reference voltage V _REF with the output voltage Vout to generate offset detection signals U and D corresponding to the error values. For this purpose, the dynamic comparators 110 and 115 must include two synchronous comparators. The dynamic comparators 110 and 115 may set the size of the transistors at the input terminal to be different in order to provide an intentional offset. By setting the sizes of the input transistors of the dynamic comparators 110 and 115, it is possible to provide an intentional offset using only the reference voltage (V _REF ) without applying a separate voltage for offset from the outside.

The first dynamic comparator 110 receives the reference voltage (V _REF ) through the negative input terminal (-) and receives the output voltage (Vout) through the positive input terminal (+) to determine the down signal (D). do. On the other hand, the second dynamic comparator 115 receives the reference voltage (V _REF ) through the positive input terminal (+) and the output voltage (Vout) through the negative input terminal (-) to generate an up signal (U). Decide. The offset detection signals (U, D), which are composed of a pair of down and up signals, may be output in the form of a bit stream according to the cycle of the clock signal (CLK).

For example, when the output voltage (Vout) exceeds the reference voltage (V _REF ), the first dynamic comparator 110 determines that a positive offset occurs and sets the down signal (D) to logic '1' during the cycle. It can be output as '. On the other hand, when the output voltage (Vout) is lower than the reference voltage (V _REF ), the first dynamic comparator 110 determines that there is no positive offset and sets the down signal (D) to logic '0' during the cycle. Can be printed. When the output voltage (Vout) is lower than the reference voltage (V _REF ), the second dynamic comparator 115 determines that a negative offset occurs and outputs the up signal (U) as logic '1' during the cycle. there is. On the other hand, when the output voltage (Vout) is higher than the reference voltage (V _REF ), the second dynamic comparator 115 may output the up signal (U) as logic '0' during the corresponding cycle.

The calibration circuit 120 receives offset detection signals (U, D) output from the dynamic comparators (110, 115) in synchronization with the clock signal (CLK). And the calibration circuit 120 generates offset control signals (Q _S , Q _M , Q _L ) for adjusting the offset of the output voltage according to the offset detection signals (U, D). Each of the offset control signals (Q _S , Q _M , Q _L ) controls the voltage at the differential input terminal of the operational transconductance amplifiers (OTA _S , OTA _M , OTA _L ) of the background calibration loop (130, 140, 150). do.

The background calibration loops 130, 140, and 150 include a small loop 130, a medium loop 140, and a large loop 150, respectively, including operational trans-conductance amplifiers (OTA _S , OTA _M , and OTA _L ). Includes. Although an embodiment in which the background calibration loops 130, 140, and 150 are composed of three loops is described, it will be well understood that the number of loops may be two or four or more.

The small loop 130 can transfer the smallest amount of charge to the output terminal in response to the offset control signal (Q _S ). The small loop 130 includes a first operational trans-conductance amplifier (OTA _S ) and a small pass transistor (M _S ). The first operational trans-conductance amplifier (OTA _S ) controls the number of input transistors that are turned on or off according to the offset control signal (Q _S ). The gate voltage (V _{G_S} ) level of the small pass transistor (M _S ) is adjusted according to the number of input transistors that are turned on or off. The small pass transistor (M _S ) transfers the power supply voltage (V _DD ) to the output terminal according to the gate voltage (V _{G_S} ) provided by the first operational trans-conductance amplifier (OTA _S ). Since the channel size of the small pass transistor ( _MS ) is the smallest, the small loop 130 is most affected by offset. Therefore, the offset adjustment ability can be improved by providing the largest number of bits of the offset control signal (Q _S ). The small pass transistor (M _S ) is a structure in which one (for example, 1x) or two or more PMOS transistors sharing a gate voltage (V _{G_S} ) are connected in parallel between the power supply voltage (V _DD ) and the output voltage (Vout). can be formed.

The medium loop 140 can transfer medium level charges to the output terminal in response to the offset control signal (Q _M ). The medium loop 140 includes a second operational trans-conductance amplifier (OTA _M ) and a medium pass transistor (M _M ). The second operational trans-conductance amplifier (OTA _M ) controls the number of input transistors that are turned on or off according to the offset control signal (Q _M ). The second operational trans-conductance amplifier (OTA _M ) adjusts the gate voltage (V _{G_M} ) of the medium pass transistor (M _M ) according to the number of input transistors that are turned on or turned off. The medium pass transistor (M _M ) transfers the power supply voltage (V _DD ) to the output terminal according to the gate voltage (V _{G_M} ) provided by the second operational trans-conductance amplifier (OTA _M ). The channel size of the medium pass transistor (M _M ) is larger than that of the small pass transistor (M _S ) and smaller than that of the large pass transistor (M _L ). Accordingly, since the medium loop 140 has less influence on the offset than the small loop 130, the number of bits of the offset control signal (Q _M ) may be provided less than the number of bits of the offset control signal (Q _S ). The medium pass transistor (M _M ) may be formed in a structure in which a plurality of PMOS transistors (e.g., 8x) sharing the gate voltage (V _{G_S} ) are connected in parallel between the power supply voltage (V _DD ) and the output voltage (Vout). You can.

The large loop 150 may transfer the maximum amount of charges among the background calibration loops 130, 140, and 150 to the output terminal in response to the offset control signal (Q _L ). The large loop 150 includes a third operational trans-conductance amplifier (OTA _L ) and a large pass transistor ( _ML ). The third operational trans-conductance amplifier (OTA _L ) controls the number of input transistors that are turned on or off according to the offset control signal (Q _L ). The third operational trans-conductance amplifier (OTA _L ) adjusts the level of the gate voltage (V _{G_L} ) according to the number of input transistors that are turned on or turned off. The channel size of the large pass transistor (M _L ) is larger than that of the medium pass transistor (M _M ). Therefore, since the large loop 150 has less influence on the offset than the medium loop 140, the number of bits of the offset control signal (Q _L ) is less than the number of bits of the offset control signal (Q _M ) of the medium loop 140. can be provided. The large pass transistor ( _ML ) may be formed in a structure in which a plurality of PMOS transistors (for example, 16x) sharing the gate voltage (V _{G_S} ) are connected in parallel between the power supply voltage (V _DD ) and the output voltage (Vout). You can.

The output voltage comparator 160 compares the output voltage (Vout) and the first reference voltage (V _{REF_L} ) and provides the result to the mode controller 180. That is, the output voltage comparator 160 feeds back the level of the output voltage (Vout) and detects whether the level of the output voltage (Vout) drops below the first reference voltage (V _{REF_L} ). The gate voltage comparators 170 and 175 compare the gate voltages (V _{G_M} , V _{G_L} ) of the medium pass transistor (M _M ) and the large pass transistor (M _L ) with the second reference voltage (V _{REF_H} ), respectively, and use a mode controller ( 180).

The mode controller 180 monitors the levels of the gate voltage (V _{G_M} , V _{G_L} ) and the output voltage (Vout) and the large loop switch 190 and medium loop to activate the medium loop 140 and large loop 150. Controls the switch 195. When the output voltage (Vout) is lower than the first reference voltage (V _{REF_L} ), the mode controller 180 generates a large loop enable signal (EN _L ) to turn on the large loop switch (190, _SL ). On the other hand, the small loop 130 is always in an activated state. Additionally, the mode controller 180 may control the large loop switch 190 and the medium loop switch 195 by monitoring the levels of the gate voltages (V _{G_M} , V _{G_L} ).

The hybrid LDO regulator 100 of the present invention described above may include a plurality of analog calibration loops and a digital controller with different offset adjustment capabilities. The digital controller can selectively activate/deactivate a plurality of analog calibration loops depending on the level of the output voltage (Vout). The speed of transient response can be increased through multiple analog calibration loops, and circuit stability can be improved by using an operational trans-conductance amplifier.

Figures 2 and 3 are circuit diagrams exemplarily showing the configuration of the dynamic comparators of Figure 1. 2 and 3, the dynamic comparator 110 generates an offset detection signal (U) by comparing the input signals (V _REF , Vout), and the dynamic comparator 115 compares the input signals (V _REF , Vout). An offset detection signal (D) can be generated by comparing Vout).

The dynamic comparator 110 of FIG. 2 is activated in synchronization with the clock signal CLK and can output a comparison result between the output voltage Vout and the reference voltage V _REF . The dynamic comparator 110 initializes and charges the transistors constituting the comparator with the power supply voltage (V _DD ) in the low level section of the clock signal (CLK). In the high level section of the clock signal CLK, an up signal U can be generated by comparing the output voltage Vout and the reference voltage V _REF .

A reference voltage (V _REF ) can be provided to the gate of the NMOS transistor (NM3), and an output voltage (Vout) can be provided to the gate of the NMOS transistor (NM4). In particular, when adjusting the size of the input transistor to set the offset, the effect of adding the offset (ΔV) voltage to the reference voltage (V _REF ) may be provided. Then, when the output voltage (Vout) is higher than the offset-added reference voltage (V _REF +ΔV), the up signal (U) formed at the output node is formed at a high level or logic '1'. The existence of this offset (ΔV) arises from the level difference between the output voltage (Vout) and the reference voltage (V _REF ), and offsets due to process variation or temperature are also detected by the dynamic comparator 110 and an up signal ( It can be reflected by U).

The dynamic comparator 115 of FIG. 3 is activated in synchronization with the clock signal CLK and may output a down signal D according to the comparison result. The output voltage (Vout) can be provided to the gate of the NMOS transistor (NM3'), and the reference voltage (V _REF ) can be provided to the gate of the NMOS transistor (NM4'). When the output voltage (Vout) is lower than the reference voltage (V _REF ), the down signal (D) formed at the output node is formed at a high level or logic '1'. The unique offset of the device can also be detected as the level difference between the output voltage (Vout) and the reference voltage (V _REF ) and reflected by the down signal (D). The effect of the detected offset can be compensated for by the operation of the calibration circuit 120 and the background calibration loops 130, 140, and 150.

Figure 4 is a block diagram showing an exemplary configuration of a calibration circuit according to an embodiment of the present invention. Referring to FIG. 4, the calibration circuit 120 may be implemented as a bi-directional shift register for generating offset control signals (Q _S , Q _M , Q _L ).

The bidirectional shift register constituting the calibration circuit 120 can switch the shift direction of the logical sequences stored in the register according to the offset detection signals (U, D). For example, when the offset detection signals (U, D) and the current output voltage (Vout) are higher than the upper limit reference voltage (V _REF +ΔV), offset control signals (Q ₁ ) to lower the level of the output voltage (Vout) ~Q _k , Q _k+1 ~Q _2k ) will be generated.

Each unit register that makes up the bidirectional shift register may be composed of a D-flip-flop (D-FF) and a multiplexer (MUX). The number of input transistors of the operational trans-conductance amplifier (OTA) that is turned on is determined according to the shift direction of the bidirectional shift register.

FIGS. 5A and 5B are diagrams exemplarily showing the configuration of a unit register that generates the offset control signals (Q ₁ to Q _k , Q _k+1 to Q _2k ) of FIG. 4 . Referring to FIGS. 5A and 5B, the unit register that generates the offset control signals (Q ₁ to Q _k ) is a multiplexer (MUX) and the D-flip-flop (D-FF) shifts the direction according to the selection signal (SEL). This can be decided. And inverters may be added to the input and output terminals of the unit register that generates offset control signals (Q _k+1 to Q _2k ).

Figure 6 is a block diagram showing the configuration of each background calibration loop. Referring to FIG. 6, the background calibration loop includes a small loop 130, a medium loop 140, and a large loop 150.

The small loop 130 can transfer the smallest amount of charge to the output terminal in response to the offset control signal (Q _S ). The offset control signal (Q _S ) may be a plurality of logic bits generated by a bidirectional shift register. The small loop 130 includes a first operational trans-conductance amplifier (OTA _S ) and a small pass transistor (M _S ). The first operational trans-conductance amplifier (OTA _S ) controls the number of input transistors that are turned on or off according to the offset control signal (Q _S ). For example, turn-on/turn-off of 40 input transistors is determined by the offset control signal (Q _S ). The level of the gate voltage (V _{G_S} ) is adjusted according to the number of input transistors that are turned on or off.

The small pass transistor (M _S ) switches the power supply voltage (V _DD ) according to the gate voltage (V _{G_S} ) provided by the first operational trans-conductance amplifier (OTA _S ). Since the channel size of the small pass transistor ( _MS ) is the smallest, the small loop 130 is most affected by the offset caused by the difference in size of the input transistors of the dynamic comparators 110 and 115. In other words, even with a small offset change, the influence on the output of the small pass transistor ( _MS ) is bound to increase because the channel size is small. Accordingly, the small loop 130 has the largest number of bits of the offset control signal (Q _S ) to compensate for this offset. The small pass transistor (M _S ) may be composed of, for example, one PMOS transistor controlled by the gate voltage (V _{G_S} ). In addition, there is no switch controlled by the mode controller 180 between the small pass transistor ( _MS ) and the output voltage (Vout). Accordingly, the offset adjustment operation by the small loop 130 will always remain activated.

The medium loop 140 includes a second operational transconductance amplifier (OTA _M ) and a medium pass transistor (M _M ) that generate a gate voltage (V _{G_M} ) in response to the offset control signal (Q _M ). The second operational trans-conductance amplifier (OTA _M ) controls the number of input transistors that are turned on or off according to the offset control signal (Q _M ). The level of the gate voltage (V _{G_M} ) is adjusted according to the number of input transistors that are turned on or off. The medium pass transistor (M _M ) switches the power supply voltage (V _DD ) according to the gate voltage (V _{G_M} ) provided by the second operational trans-conductance amplifier (OTA _M ).

The channel size of the medium pass transistor (M _M ) is larger than that of the small pass transistor (M _S ) and smaller than that of the large pass transistor (M _L ). Therefore, since the medium loop 140 has less influence on the offset than the small loop 130, the number of bits of the offset control signal (Q _M ) is less than the number of bits of the offset control signal (Q _S ) of the small loop 130. can be provided. The medium pass transistor (M _M ) may be formed in a structure in which a plurality of PMOS transistors (e.g., 8x) sharing the gate voltage (V _{G_S} ) are connected in parallel between the power supply voltage (V _DD ) and the output voltage (Vout). You can. In addition, there is a medium loop switch 195 controlled by the mode controller 180 between the medium pass transistor ( _MM ) and the output voltage (Vout). Accordingly, offset adjustment by the medium loop 140 may be activated or deactivated depending on the level change of the output voltage (Vout).

The large loop 150 may transfer the maximum charges among the background calibration loops 130, 140, and 150 to the output terminal in response to the offset control signal (Q _L ). The large loop 150 includes a third operational trans-conductance amplifier (OTA _L ) and a large pass transistor ( _ML ). The third operational trans-conductance amplifier (OTA _L ) controls the number of input transistors that are turned on or off according to the offset control signal (Q _L ). The level of the gate voltage (V _{G_L} ) is adjusted according to the number of input transistors that are turned on or off.

The large pass transistor ( _ML ) switches the power supply voltage (V _DD ) according to the gate voltage (V _{G_L} ) provided by the third operational trans-conductance amplifier (OTA _L ). The channel size of the large pass transistor (M _L ) is larger than that of the medium pass transistor (M _M ). Therefore, since the large loop 150 has less influence on the offset than the medium loop 140, the number of bits of the offset control signal (Q _L ) is less than the number of bits of the offset control signal (Q _M ) of the medium loop 140. can be provided. The large pass transistor ( _ML ) may be formed in a structure in which a plurality of PMOS transistors (for example, 16x) sharing the gate voltage (V _{G_S} ) are connected in parallel between the power supply voltage (V _DD ) and the output voltage (Vout). You can. There is a large loop switch 190 controlled by the mode controller 180 between the large pass transistor ( _ML ) and the output voltage (Vout). Accordingly, offset adjustment by the large loop 150 may be activated or deactivated depending on the level change of the output voltage (Vout). That is, when the level of the output voltage Vout rapidly decreases due to the offset, the large loop switch 190 will be turned on and offset adjustment by the large loop 150 will be activated.

FIG. 7 is a circuit diagram exemplarily showing the structure of the third operational transconductance amplifier (OTA _L ) of FIG. 6. Referring to FIG. 7 , the third operational trans-conductance amplifier (OTA _L ) includes input transistors 155 controlled by an offset control signal (Q _L ). The structures of the first and second operational transconductance amplifiers OTA _S and OTA _M are also substantially similar to the third operational transconductance amplifier OTA _L.

The third operational trans-conductance amplifier (OTA _L ) includes input transistors (155, N11, N12) whose gates are connected to the differential input terminals (V _INN , V _INP ). The voltage difference between the differential input terminals (V _INN , V _INP ) is provided as the gate voltage (V _{G_S} ), which is the output of the third operational trans-conductance amplifier (OTA _L ).

FIG. 8 is a circuit diagram showing the input transistor of FIG. 7 in more detail. Referring to FIG. 8, offset control signals (Q ₁ to Q _k ) provided to the negative input terminal (V _INN ) and offset control signals (Q _k+1 to Q _2k ) provided to the positive input terminal (V _INP ). ) is provided to each gate of the input transistor 155.

The input transistor N11 constituting the negative input terminal V _INN may be configured to have a plurality of NMOS transistors connected in parallel. Offset control signals (Q ₁ to Q _k ) are provided to the gates of each of the plurality of NMOS transistors. Each of the plurality of NMOS transistors is turned on or turned off depending on the level of the offset control signals (Q ₁ to Q _k ).

The input transistor N12 constituting the positive input terminal V _INP may be configured to have a plurality of NMOS transistors connected in parallel. Offset control signals (Q _k+1 to Q _2k ) are provided to the gates of each of the plurality of NMOS transistors. Each of the plurality of NMOS transistors is turned on or turned off depending on the level of the offset control signals (Q _k+1 to Q _2k ). Accordingly, the level of the gate voltage (V _{G_S} ), which is the output of the third operational trans-conductance amplifier (OTA _L ), can be adjusted according to the shift state of the offset control signals (Q ₁ to Q _2k ).

Figure 9 is a diagram briefly showing a shift method of offset control signals (Q ₁ to Q _2k ) for controlling the input transistors of the operational transconductance amplifier (OTA) of the present invention. Referring to FIG. 9, the level difference between the negative input voltage (V _INN ) and the positive input voltage (V _INP ) is adjusted by the offset control signals (Q ₁ to Q _2k ) generated by the calibration circuit 120. You can.

Offset control to provide a negative input voltage (V _INN ) under initial conditions Number of bits (logic '0') of the signals (Q ₁ ~ Q _k ) and offset control to provide a positive input voltage (V _INP ) The number of bits (logic '1') of the signals (Q _k+1 to Q _2k ) may be set to be the same.

However, if the level of the negative input terminal voltage (V _INN ) needs to be increased (if V _INN < V _INP ), the shift direction of the bidirectional shift register will be controlled to the right so that the number of bits of logic '0' increases. On the other hand, if the level of the positive input voltage (V _INP ) needs to be increased (if V _INN > V _INP ), the bidirectional shift register will be shifted to the left to increase the number of bits of logic '1'.

Figure 10 is a graph showing the effect of the background calibration loop of the present invention. Referring to FIG. 10, when the level of the output voltage (Vout) is outside the allowable reference voltage range (V _REF ±ΔV), the output voltage (Vout) may be stabilized by an offset compensation operation by a background calibration loop.

The graph (C1) shows the offset compensation operation when the output voltage (Vout) exceeds the upper limit reference voltage (V _REF +ΔV). From time T0, the level of the output voltage (Vout) is detected by the dynamic comparator 110 as exceeding the upper limit reference voltage (V _REF +ΔV), and the calibration circuit 120 and the background calibration loops 130, 140, and 150 Compensation by the people begins. Then, the output voltage (Vout) is stabilized at a level lower than the upper limit reference voltage (V _REF +ΔV). The graph (C2) shows the offset compensation operation when the output voltage (Vout) is lower than the lower limit reference voltage (V _REF -ΔV). Likewise, the level of the output voltage (Vout) is detected to be lower than the lower limit reference voltage (V _REF -ΔV) by the dynamic comparator 115, and the calibration circuit 120 and the background calibration loops 130, 140, and 150 Compensation begins. Then, the output voltage (Vout) can be stabilized at a level higher than the lower limit reference voltage (V _REF -ΔV).

The above-described details are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply changed or easily changed in design. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described later.

100: Hybrid LDO regulator
110, 115: dynamic comparator
120: Calibration circuit
130: Small loop
140: medium loop
150: Large Loop
160: output voltage comparator
170, 175: Gate voltage comparator
180: mode controller
190: Large loop switch
195: Medium loop switch

Claims (11)

For an LDO regulator that converts the supply voltage and provides an output voltage:
a dynamic comparator that compares first and second reference voltages and the output voltage in synchronization with a clock signal to detect an offset and output an offset detection signal;
a calibration circuit that generates offset control signals to compensate for the offset in response to the offset detection signal;
a first operational trans-conductance amplifier that generates a first gate voltage according to a first offset control signal among the offset control signals;
a second operational trans-conductance amplifier that generates a second gate voltage according to a second offset control signal among the offset control signals;
a first pass transistor transmitting the power voltage to an output terminal according to the first gate voltage;
a second pass transistor transmitting the power voltage according to the second gate voltage;
a first loop switch connecting the second pass transistor and the output terminal in response to a first enable signal; and
An LDO regulator comprising a digital control unit that compares the output voltage and a third reference voltage, detects the level of the second gate voltage, and generates the first enable signal. According to claim 1,
The dynamic comparator:
a first dynamic comparator that generates a first offset detection signal that is activated when the level of the output voltage is higher than the first reference voltage; and
An LDO regulator comprising a second dynamic comparator that generates a second offset detection signal that is activated when the level of the output voltage is lower than the second reference voltage. According to claim 2,
The calibration circuit includes a bidirectional shift register that generates the plural-bit offset control signals whose ratio of logic '1' and logic '0' are adjusted according to the first and second offset detection signals. According to claim 3,
The offset control signals include the first offset control signal provided to the first operational trans-conductance amplifier and the second offset control signal provided to the second operational trans-conductance amplifier, wherein the first offset control signal An LDO regulator, wherein the number of bits of the second offset control signal is different. According to claim 4,
The first operational trans-conductance amplifier and each of the positive and negative input terminals of the first operational trans-conductance amplifier include a plurality of input transistors connected in parallel that are switched by the first offset control signal and the second offset control signal. Includes LDO regulator. According to claim 1,
An LDO regulator wherein the channel size of the first pass transistor is smaller than the channel size of the second pass transistor. According to claim 6,
An LDO regulator wherein the first pass transistor includes one PMOS transistor, and the second pass transistor includes a plurality of PMOS transistors sharing the second gate voltage. According to claim 1,
a third operational trans-conductance amplifier that generates a third gate voltage according to a third offset control signal among the offset control signals;
a third pass transistor transmitting the power voltage according to the third gate voltage; and
The LDO regulator further includes a second loop switch connecting the third pass transistor and the output terminal in response to a second enable signal. According to claim 8,
An LDO regulator, characterized in that the channel size of the third pass transistor is larger than the channel size of the second pass transistor. According to claim 8,
The digital control unit:
an output voltage comparator that compares the output voltage and the third reference voltage;
a first comparator that compares the second gate voltage and a fourth reference voltage;
a second comparator comparing the third gate voltage with the fourth reference voltage; and
An LDO regulator including a mode controller that controls the first loop switch and the second loop switch based on the output voltage comparator and the outputs of the first and second comparators. According to claim 10,
The mode controller is an LDO regulator that turns on the second loop switch when the output voltage is lower than the third reference voltage.

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