KR102133758B1 - 레지스터 파일 회로 및 최소 동작 공급 전압을 개선하기 위한 방법 - Google Patents
레지스터 파일 회로 및 최소 동작 공급 전압을 개선하기 위한 방법 Download PDFInfo
- Publication number
- KR102133758B1 KR102133758B1 KR1020177007915A KR20177007915A KR102133758B1 KR 102133758 B1 KR102133758 B1 KR 102133758B1 KR 1020177007915 A KR1020177007915 A KR 1020177007915A KR 20177007915 A KR20177007915 A KR 20177007915A KR 102133758 B1 KR102133758 B1 KR 102133758B1
- Authority
- KR
- South Korea
- Prior art keywords
- nfet
- header
- gate
- pfet
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/007—Register arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Power Engineering (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/499,052 | 2014-09-26 | ||
| US14/499,052 US9251875B1 (en) | 2014-09-26 | 2014-09-26 | Register file circuit and method for improving the minimum operating supply voltage |
| PCT/US2015/043602 WO2016048455A1 (en) | 2014-09-26 | 2015-08-04 | Register file circuit and method for improving the minimum operating supply voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20170063609A KR20170063609A (ko) | 2017-06-08 |
| KR102133758B1 true KR102133758B1 (ko) | 2020-07-14 |
Family
ID=53836860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020177007915A Expired - Fee Related KR102133758B1 (ko) | 2014-09-26 | 2015-08-04 | 레지스터 파일 회로 및 최소 동작 공급 전압을 개선하기 위한 방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9251875B1 (https=) |
| EP (1) | EP3198608B1 (https=) |
| JP (1) | JP6668337B2 (https=) |
| KR (1) | KR102133758B1 (https=) |
| CN (1) | CN106716541B (https=) |
| WO (1) | WO2016048455A1 (https=) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5317900B2 (ja) | 2009-09-14 | 2013-10-16 | ルネサスエレクトロニクス株式会社 | 半導体集積回路およびその動作方法 |
| US10163524B2 (en) | 2016-06-22 | 2018-12-25 | Darryl G. Walker | Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor |
| US9940999B2 (en) | 2016-06-22 | 2018-04-10 | Darryl G. Walker | Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits |
| US11417370B2 (en) * | 2020-08-12 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device |
| RU2771447C1 (ru) * | 2021-08-03 | 2022-05-04 | Владимир Владимирович Шубин | Элемент входного регистра |
| US11955171B2 (en) | 2021-09-15 | 2024-04-09 | Mavagail Technology, LLC | Integrated circuit device including an SRAM portion having end power select circuits |
| US12512151B1 (en) * | 2024-01-17 | 2025-12-30 | Synopsys, Inc. | Memory with hybrid write assist scheme |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002042476A (ja) * | 2000-07-25 | 2002-02-08 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| US20070206404A1 (en) * | 2006-03-01 | 2007-09-06 | Yoshinobu Yamagami | Semiconductor memory device |
| US20130343135A1 (en) | 2012-06-22 | 2013-12-26 | Samsung Electronics Co., Ltd | Semiconductor memory devices |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6771095B1 (en) * | 2002-11-22 | 2004-08-03 | Analog Devices, Inc. | Level translating digital switch |
| JP4917767B2 (ja) * | 2005-07-01 | 2012-04-18 | パナソニック株式会社 | 半導体記憶装置 |
| US20070047364A1 (en) * | 2005-08-31 | 2007-03-01 | International Business Machines Corporation | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
| US7313032B2 (en) * | 2005-11-29 | 2007-12-25 | International Business Machines Corporation | SRAM voltage control for improved operational margins |
| US20070242498A1 (en) * | 2006-04-13 | 2007-10-18 | Anantha Chandrakasan | Sub-threshold static random access memory |
| KR100780750B1 (ko) * | 2006-05-11 | 2007-11-30 | 한국과학기술원 | 표준 셀과 파워 게이팅 셀을 이용한 파워 네트워크 및 이를가지는 반도체 장치 |
| US7542329B2 (en) * | 2006-07-19 | 2009-06-02 | International Business Machines Corporation | Virtual power rails for integrated circuits |
| US7692130B2 (en) * | 2006-11-01 | 2010-04-06 | International Business Machines Corporation | CMOS imaging sensor having a third FET device with a gate terminal coupled to a second diffusion region of a first FET device and a first terminal coupled to a row select signal |
| US7414878B1 (en) * | 2007-05-04 | 2008-08-19 | International Business Machines Corporation | Method for implementing domino SRAM leakage current reduction |
| JP2009076164A (ja) * | 2007-09-21 | 2009-04-09 | Fujitsu Microelectronics Ltd | 半導体記憶装置 |
| US7551508B2 (en) * | 2007-11-16 | 2009-06-23 | International Business Machines Corporation | Energy efficient storage device using per-element selectable power supply voltages |
| US8099688B2 (en) * | 2007-11-19 | 2012-01-17 | International Business Machines Corporation | Circuit design |
| JP5200506B2 (ja) * | 2007-11-28 | 2013-06-05 | 富士通セミコンダクター株式会社 | メモリ装置 |
| US8111579B2 (en) | 2008-11-10 | 2012-02-07 | Intel Corporation | Circuits and methods for reducing minimum supply for register file cells |
| US8094505B2 (en) | 2009-10-09 | 2012-01-10 | Intel Corporation | Method and system to lower the minimum operating voltage of a memory array |
| TWI419162B (zh) * | 2009-11-03 | 2013-12-11 | Univ Hsiuping Sci & Tech | 具放電路徑之單埠靜態隨機存取記憶體 |
| US8400819B2 (en) * | 2010-02-26 | 2013-03-19 | Freescale Semiconductor, Inc. | Integrated circuit having variable memory array power supply voltage |
| US8320203B2 (en) | 2010-03-26 | 2012-11-27 | Intel Corporation | Method and system to lower the minimum operating voltage of register files |
| US8493124B2 (en) | 2010-07-26 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low minimum power supply voltage level shifter |
| US9093125B2 (en) | 2012-01-23 | 2015-07-28 | Qualcomm Incorporated | Low voltage write speed bitcell |
| US9111600B2 (en) * | 2012-03-30 | 2015-08-18 | Intel Corporation | Memory cell with improved write margin |
| US8823454B2 (en) * | 2012-03-30 | 2014-09-02 | Freescale Semiconductor, Inc. | Fully complementary self-biased differential receiver with startup circuit |
| US9153304B2 (en) | 2012-06-28 | 2015-10-06 | Jaydeep P. Kulkarni | Apparatus for reducing write minimum supply voltage for memory |
| US20140112429A1 (en) * | 2012-10-23 | 2014-04-24 | Apple Inc. | Low Voltage Register File Cell Structure |
| US9224453B2 (en) * | 2013-03-13 | 2015-12-29 | Qualcomm Incorporated | Write-assisted memory with enhanced speed |
| US9135987B2 (en) * | 2013-07-01 | 2015-09-15 | Internatinal Business Machines Corporation | FinFET-based boosting supply voltage circuit and method |
-
2014
- 2014-09-26 US US14/499,052 patent/US9251875B1/en active Active
-
2015
- 2015-08-04 WO PCT/US2015/043602 patent/WO2016048455A1/en not_active Ceased
- 2015-08-04 JP JP2017515931A patent/JP6668337B2/ja active Active
- 2015-08-04 CN CN201580047910.8A patent/CN106716541B/zh active Active
- 2015-08-04 EP EP15750549.6A patent/EP3198608B1/en active Active
- 2015-08-04 KR KR1020177007915A patent/KR102133758B1/ko not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002042476A (ja) * | 2000-07-25 | 2002-02-08 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| US20070206404A1 (en) * | 2006-03-01 | 2007-09-06 | Yoshinobu Yamagami | Semiconductor memory device |
| US20130343135A1 (en) | 2012-06-22 | 2013-12-26 | Samsung Electronics Co., Ltd | Semiconductor memory devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106716541B (zh) | 2021-06-04 |
| EP3198608B1 (en) | 2019-11-06 |
| JP6668337B2 (ja) | 2020-03-18 |
| CN106716541A (zh) | 2017-05-24 |
| JP2017529644A (ja) | 2017-10-05 |
| WO2016048455A1 (en) | 2016-03-31 |
| EP3198608A1 (en) | 2017-08-02 |
| US9251875B1 (en) | 2016-02-02 |
| KR20170063609A (ko) | 2017-06-08 |
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St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
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