KR102131319B1 - Light emitting device and lightihng device having the same - Google Patents

Abstract

The light emitting device according to the embodiment includes a first semiconductor layer including a plurality of first feet concave from the upper surface; An active layer having a plurality of well layers and a plurality of barrier layers on the first semiconductor layer; And a second semiconductor layer on the active layer, the barrier layer and the barrier layer are alternately stacked, and the plurality of well layers includes a plurality of holes in an area corresponding to the plurality of first feet, and Some regions of the barrier layer are disposed in the plurality of holes.

Description

Light-emitting element and lighting device having same{LIGHT EMITTING DEVICE AND LIGHTIHNG DEVICE HAVING THE SAME}

The embodiment relates to a light emitting device and a lighting device having the same.

Group III-V nitride semiconductors are spotlighted as core materials for light-emitting devices such as light-emitting diodes (LEDs) or laser diodes (LDs) due to their physical and chemical properties. Group III-V nitride semiconductors are usually made of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1).

A light emitting diode (LED) is a type of semiconductor device used as a light source or a signal by converting electricity into infrared rays or light using characteristics of a compound semiconductor.

LEDs or LDs using these nitride semiconductor materials are frequently used in light-emitting elements for obtaining light, and are used as light sources for various products such as keypad light-emitting units of mobile phones, display devices, electronic displays, and lighting devices.

The embodiment provides a light emitting device in which holes are arranged in a region corresponding to a pit among regions of the well layer of the active layer.

The embodiment provides a light emitting device having a non-emission region corresponding to the pits and holes of the active layer and a non-emission region corresponding to the well layer.

An embodiment provides a light emitting device having an active layer providing a pit region of a barrier layer corresponding to a convex portion of a substrate and a hole of a well layer corresponding to the pit.

The embodiment provides a light emitting device having an active layer and a lighting device having the same.

The light emitting device according to the embodiment includes a first semiconductor layer including a plurality of first feet concave from the upper surface; An active layer having a plurality of well layers and a plurality of barrier layers on the first semiconductor layer; And a second semiconductor layer on the active layer, the barrier layer and the barrier layer are alternately stacked, and the plurality of well layers includes a plurality of holes in an area corresponding to the plurality of first feet, and Some regions of the barrier layer are disposed in the plurality of holes.

Embodiments can reduce defects in the active layer.

The embodiment can improve the efficiency of the light emitting region by distinguishing the light emitting region and the non-light emitting region of the active layer.

The embodiment may reduce the non-emission area around the pit in the active layer.

The embodiment may enhance resistance to elecrosatic discharge (ESD) in the light emitting device.

The embodiment may provide pits of uniform size to the active layer.

An embodiment may provide a light emitting device with improved reliability of an active layer and a lighting device having the same.

1 is a side cross-sectional view of a light emitting device according to a first embodiment.
2 is an enlarged view showing an active layer of the light emitting device of FIG. 1.
FIG. 3 is a view showing another example of the active layer of FIG. 2.
4 is a view showing another example of the active layer of FIG. 2.
5 is a side cross-sectional view showing a light emitting device according to a second embodiment.
6 is a side sectional view showing a light emitting device according to a third embodiment.
7 is a chip structure in which electrodes are disposed on the light emitting device of FIG. 1.
8 is another chip structure in which electrodes are disposed on the light emitting device of FIG. 1.
9 is a side cross-sectional view of a light emitting device package having the light emitting device of FIG. 7.
10 is a view showing a display device having a light emitting device or a light emitting device package according to an embodiment.
11 is a view showing another example of a display device having a light emitting device or a light emitting device package according to an embodiment.
12 is a view showing a lighting device having a light emitting device or a light emitting device package according to an embodiment.

In the description of the embodiment, each layer (film), region, pattern or structure is formed "on/on" or "under" of the substrate, each layer (film), region, pad or pattern. In the case described as being, "on/up" and "under" include both "directly" or "indirectly" formed through another layer. In addition, the criteria for the top/top or bottom of each layer will be described based on the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity. Also, the size of each component does not entirely reflect the actual size.

Hereinafter, with reference to the accompanying drawings will be described.

1 is a perspective view showing a light emitting device according to a first embodiment, and FIG. 2 is a partially enlarged view of an active layer of the light emitting device of FIG. 1.

1 and 2, the light emitting device includes a substrate 111, a buffer layer 113 disposed on the substrate 111, a first semiconductor layer 115 disposed on the buffer layer 113, and the agent A plurality of pits 71 in the first semiconductor layer 115, the active layer 116 disposed on the first semiconductor layer 115, the second semiconductor layer 117 disposed on the active layer 116, and the And a third semiconductor layer 119 disposed on the second semiconductor layer 117.

The substrate 111 is a growth substrate for semiconductor single crystal, such as nitride single crystal growth, sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge, Ga ₂ O ₃ At least one of them can be used. The substrate 111 may be a transmissive, insulating or conductive substrate. The sapphire is a crystal having hexagonal room beam (Hexa-Rhombo R3c) symmetry, and the lattice constants in the c-axis and a-axis directions are 13.001Å and 4.758Å, and C(0001), A(1120), and R(1102) ). In this case, the C-plane is relatively easy to grow a nitride thin film and is stable at high temperatures, and thus is mainly used as a substrate for growing a nitride semiconductor.

The thickness of the substrate 111 includes a range of 120㎛ to 500㎛, the refractive index may be formed of a material of 2.4 or less, for example, 2 or less.

The length of adjacent sides of the substrate 111 may be the same or different from each other, and the length of at least one side may be 0.3 mm×0.3 mm or more, or may be provided in a size having a large area, for example, an area of 1 mm×1 mm or more. . When viewed from above, the substrate 111 may be formed in a polygonal shape such as a square or hexagon, but is not limited thereto.

The buffer layer 113 is formed on the substrate 111 and may be formed of one layer or a plurality of layers by selectively using a group II to VI compound semiconductor. The buffer layer 113 is, for example, a semiconductor layer using a group III-V compound semiconductor, for example, Al _x In _y Ga _(1-xy) N composition formula (0≤x≤1, 0≤y≤1, 0≤x+ It may be formed of a compound semiconductor having a y≤1), typically, may include at least one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN. The buffer layer 113 is mainly grown through the growth surface (0001) of the substrate 111, and when a potential is generated by a lattice constant, the potential is mostly propagated in the growth direction.

An undoped semiconductor layer may be further formed between the buffer layer 113 and the first semiconductor layer 115, and the undoped semiconductor layer has lower conductivity than the n-type semiconductor layer. It can be formed of a low conductive layer. Dislocations may be generated in at least one of the buffer layer 113 and the undoped semiconductor layer.

The first semiconductor layer 115 is formed on the buffer layer 113, and a first conductive dopant may be added. The first conductive dopant may be an N-type dopant, and includes Si, Ge, Sn, Se, and Te. The first semiconductor layer 115 may be formed of any one of group III-V compound semiconductors, such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. The first semiconductor layer 115, for example, In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) to form a semiconductor having a composition formula Can.

The first semiconductor layer 115 includes a plurality of pits 71 recessed recessed from the top surface of the first semiconductor layer 115. Each pit 71 has a side cross-section formed in a V shape, and a planar shape may be formed in a hexagonal shape, for example, a hexagonal pillar shape. That is, each of the pits 71 becomes larger as the thickness of the first semiconductor layer 115 increases, and the inclined surface may have a range of 35 degrees to 60 degrees. One or a plurality of electric potentials propagated may be connected to each pit 71.

When the first semiconductor layer 115 grows in a range of 500 degrees to 1000 degrees, pits 71 having a V shape may be formed. As another example, the V-shaped pits may be formed when the first semiconductor layer 115 is formed to a predetermined thickness and then grown using a mask pattern. As shown in FIG. 2, the depth D2 of the pit 71 may be formed in a range of 2 nm to 100 nm, for example, 15 nm to 100 nm, but is not limited thereto.

The thickness of the first semiconductor layer 115 may be formed thicker than the depth D2 of the pit 71, for example, 50 nm or more, or may be formed to a thickness of 2 to 50 times the depth D2. have. The first semiconductor layer 115 may be defined as a pit control layer or a defect control layer, but is not limited thereto.

A cladding layer may be formed between the first semiconductor layer 115 and the active layer 116. The first clad layer may be formed of a GaN-based semiconductor, and the band gap may be formed wider than the band gap of the active layer 116. The cladding layer serves to constrain the carrier, and may include an N-type dopant.

A super lattice structure in which different semiconductor layers are alternately stacked may be formed between the first semiconductor layer 115 and the active layer 116, and such a superlattice structure may reduce lattice defects. Each layer of the super lattice structure may be stacked to a thickness of several A or more.

The active layer 116 is formed on the first semiconductor layer 115, and optionally includes a single quantum well, multiple quantum well (MQW), quantum wire structure or quantum dot structure, and a barrier The cycle of the layer 61 and the well layer 63 is included. The well layer 61 includes a composition formula of In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and the barrier layer 63 is In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) may include a composition formula. The period of the well layer/barrier layer 61/63 is 1, for example, using a stacked structure of InGaN/GaN, GaN/AlGaN, InGaN/AlGaN, InAlGaN/AlGaN, InGaN/InGaN, InGaN/InAlGaN, GaN/InAlGaN. It may be formed in a period longer than, for example, 3 periods or longer, such as 3 to 5 periods. The barrier layer 63 may be formed of a semiconductor material having a band gap wider than that of the well layer 61.

Looking at the growth method of the active layer 116, the barrier layer 63 is grown in a horizontal growth mode, and the well layer 61 can be grown in a vertical growth mode. The horizontal growth mode is a structure that grows more in the horizontal direction than the vertical growth mode, and the vertical growth mode is a structure that grows more in the vertical direction than the horizontal growth mode. For example, the horizontal growth mode can be grown by lowering the growth pressure in the chamber, increasing the temperature, or decreasing the growth rate, and the vertical growth mode increases the growth pressure in the chamber, lowers the growth temperature, or increases the growth rate. It can be grown in a way. The growth pressure in the vertical growth mode is to grow at a growth rate of Rg 0.1Å/min or more at 400 mbar or more, and the growth temperature at this time may be 900 degrees or less.

The well layer 61 may be formed in a thickness of 1.5 to 5 nm, for example, 2 nm to 4 nm. The barrier layer 63 may be formed thicker than the thickness of the well layer 61, and may be formed within a range of 3 to 30 nm, for example, within a range of 3 to 5 nm.

A barrier layer closest to the first semiconductor layer 115 among the barrier layers 63 is defined as a first barrier layer B1, and a barrier layer closest to the second semiconductor layer 117 is a third barrier layer It is defined as (B3), and the second well layer W2 and the second barrier layer B2 are disposed between the first and third barrier layers B1 and B3.

In addition, a well layer closest to the first semiconductor layer 115 among the well layers 61 is defined as a first well layer W1, and another well layer W2 is disposed on the first well layer W1. Can. At least one well layer 61 (W1, W2) may be disposed between the barrier layers 63 (B1, B2, B3). A third barrier layer B3 may be disposed on the top layer of the active layer 116.

The first barrier layer B1 may be contacted on the first semiconductor layer 115 or the first well layer W1 may be contacted, but is not limited thereto. For example, in the case of materials different from those of the first semiconductor layer 115 and the barrier layer 63, another barrier layer may be further formed under the first well layer W1.

The first well layer W1 is formed on the first semiconductor layer 115 and may be formed with a plurality of holes 61A corresponding to each of the pits 71. The first well layer W1 is formed on a flat surface of the first semiconductor layer 115, and the width of the hole 61A corresponding to the pit 71 in the region of the first well layer W1 ( D1) may be equal to or wider than the upper width of the pit 71. Each hole 61A overlaps with the area of the pit 71 in a vertical direction. The shape of the hole 61A includes a polygonal shape, for example, a hexagonal shape, when viewed from above. Since the first well layer W1 is grown in a vertical growth mode, it grows while suppressing indium (In) from flowing into the pit 71, so that the first well layer ( The material of W1) hardly grows and can be formed into a hole 61A. Here, as the indium of the well layer 61 increases to the inside of the pit 71, a leakage current may be caused, and the embodiment may reduce a leakage current problem and reduce a non-emission area and a light emission area. Can be clearly distinguished.

The side wall of the hole 61A may be formed as a vertical surface, and may be connected to an inclined surface of the pit 71.

A first barrier layer B1 is formed on the first well layer W1, and the first barrier layer B1 is formed above the first well layer W1 and inside the hole 61A. Some of the regions 64 formed in the hole 61A of the first barrier layer B1 may contact the feet 71 of the first semiconductor layer 115 and side surfaces of the hole 61A. The partial region 64 protrudes in the direction of the low point 74 of the pit 71 and forms a pit corresponding to the pit 71. The thickness of the first barrier layer B1 may be different from the thickness T1 of the region disposed on the first well layer and the thickness T2 of the partial region 64, for example, of the partial region 64. The thickness T2 may be formed thinner.

A second well layer W2 is disposed on the first barrier layer B1, and the second well layer W2 includes a plurality of holes corresponding to the pit 71 of the first barrier layer B1 ( 61A). The plurality of holes 61A may have the same width as the width D1 of the pit 71 or may have a wider width. That is, the second well layer W2 is disposed in an area excluding the hole 61A among the areas between the first barrier layer B1 and the second barrier layer B2.

A second barrier layer B2 is disposed on the second well layer W2, and a partial region 64 of the second barrier layer B2 passes through the hole 61A to form the first barrier layer B1. It can be formed on the feet (71). Growing in the cycle of the well layer/barrier layer 61/63, the third barrier layer B3 may be disposed as the last layer.

Since each region 64 of the barrier layer 63 is disposed in each hole 61A of the well layer 61, some regions 64 of adjacent barrier layers W1, W2, and W3 are disposed and contact each other. Can be. A potential 65 may be connected to the bottom of the pits 71 in the active layer 116. Since the well layer 61 of the active layer 116 is disposed with a plurality of holes 61A, it can be divided into a light emitting region in which the well layer 61 is disposed and a non-light region in which the well layer 61 is not disposed. The non-emission region corresponds to the region of the pit 71. Accordingly, the defect area caused by the pit 71 is minimized, and leakage current is prevented from flowing around the defect area to enhance ESD resistance and improve the reliability of the active layer.

A second semiconductor layer 117 is formed on the active layer 116. The second semiconductor layer 117 may be formed of any of semiconductors doped with a second conductive dopant, such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. The second semiconductor layer 117 is p having a semiconductor having a composition formula of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example. It may be formed of a semiconductor layer, the second conductive dopant is a p-type dopant, may include Mg, Zn, Ca, Sr, Ba.

The second semiconductor layer 117 may be formed of an electron blocking layer, for example, P-AlGaN or P-InAlGaN. The second semiconductor layer 117 may suppress propagation of the pits 71. When the pits are exposed on the surface of the semiconductor device, ESD may be affected. Thus, it can be formed in a horizontal growth mode to remove pits. A portion of the pit 71 may be propagated to the second semiconductor layer 117, but is not limited thereto.

The second semiconductor layer 117 may include a superlattice structure, and the superlattice structure may include an InGaN/GaN superlattice structure or an AlGaN/GaN superlattice structure. The superlattice structure of the second semiconductor layer 117 may abnormally diffuse the current included in the voltage to protect the active layer 116.

The third semiconductor layer 119 may be formed with a semiconductor different from the second semiconductor layer 117 on the second semiconductor layer 117 and includes a second conductive dopant. The third semiconductor layer 119 may be formed of any one of compound semiconductors such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. The third semiconductor layer 119 is p having a semiconductor having a composition formula of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example. Type semiconductor layer, for example, P-GaN or P-InGaN. The second conductive dopant is a p-type dopant, and may include Mg, Zn, Ca, Sr, and Ba. The third semiconductor layer 119 may be formed to block the pits so that the pits are not exposed.

In addition, the first semiconductor layer 115 may be a p-type semiconductor layer, and the second and third semiconductor layers 117 and 119 may be implemented as n-type semiconductor layers. A semiconductor layer having a polarity opposite to that of the second conductivity type may be formed on the third semiconductor layer 119.

The light emitting device may be defined as a stacked structure of the n-type semiconductor layer 115, the active layer 116 and the p-type semiconductor layers 117 and 119 as a light emitting structure, wherein the light emitting structure is an np junction structure, a pn junction structure, and an npn junction It can be implemented as either a structure or a pnp junction structure. Here, p is a p-type semiconductor layer, n is an n-type semiconductor layer, and-includes a structure in which the p-type semiconductor layer and the n-type semiconductor layer are in direct or indirect contact. Hereinafter, for convenience of description, the uppermost layer of the light emitting structure will be described as the third semiconductor layer 119, that is, the second conductive semiconductor layer.

3 is another example of the active layer of FIG. 2. In describing FIG. 3, the same parts as in FIG. 2 will be referred to the description of FIG. 2.

Referring to FIG. 3, the active layer is disposed on the first semiconductor layer 115 and includes a plurality of well layers 61 having holes 61B and a plurality of barrier layers 63 having pits 71.

Each well layer 61 may have a side surface of the hole 61B formed as an inclined surface, and the inclined surface may extend from the inclined surface of the pit 71. The inclined side surface of the hole 61B may be formed at an angle ranging from 35 degrees to 60 degrees, but is not limited thereto.

The upper width D1 of the pit 71 in the first semiconductor layer 115 may be smaller than the upper width D3 of the hole 61B, but is not limited thereto.

4 is another example of the active layer of FIG. 2. In describing FIG. 4, the same portion as in FIG. 2 will be referred to the description of FIG. 2.

Referring to FIG. 4, the active layer 116 is disposed over the first semiconductor layer 115, and includes a plurality of well layers 61 having holes 61A and a plurality of barrier layers 63 having pits 71. Includes.

Each well layer 61 has a hole 61A, and the plurality of barrier layers 63 may be formed of the same material. Accordingly, some regions 64 of the plurality of barrier layers 63 may be formed of the same material on the pit 71, so that a boundary surface between adjacent barrier layers may not be formed. Some regions of the active layer 116 corresponding to the pits 71 in the vertical direction, that is, regions overlapping with the pits 71 in the vertical direction, are made of a material of the barrier layer 63, for example, GaN, InGaN or AlGaN semiconductor. It can be formed without borders.

5 is a side cross-sectional view of a light emitting device according to a second embodiment. In describing FIG. 5, the same portion as in FIG. 1 will be referred to the description of FIG. 1.

Referring to FIG. 5, a fourth semiconductor layer 114 is disposed between the first semiconductor layer 115 and the active layer 116A, and a second semiconductor layer 117 is disposed on the active layer 116A.

The first semiconductor layer 115 includes a plurality of pits 72,73 having different depths, and the plurality of pits 72,72,73 have a first foot having a first depth D4 ( 72) and a second foot 73 having a second depth D5 smaller than the first foot 72. The first depth D4 has a depth of 15 nm or more from the top surface of the first semiconductor layer 115, and may be formed in a range of 15 nm to 100 nm, for example, and has the same depth within the first depth D4 range. Or may have a different depth. The second depth D5 has a depth of less than 15 nm from the top surface of the first semiconductor layer 115, and may be formed, for example, from 2 nm to less than 15 nm, and also within the second depth D4 range. Or may be of different depths.

The second feet 73 are in contact with or connected to the first feet 72, and a portion of one or a plurality of second feet 73 may be overlapped within an area of the first feet 72. . When the second feet 73 and the first feet 72 are merged, the width D6 of the merged pits may be formed larger than the width of the first feet 72 (D1 in FIG. 2 ). . Also, a plurality of troughs 75 and 76 may be disposed within the merged pit spaced apart from each other. The first feet 72 and the second feet 73 may have an inclined surface and an inclined surface connected to each other, or an inclined surface and an edge to each other. In addition, a portion where the first feet 72 and the second feet 73 are connected may be located at a lower position than the upper surface of the first semiconductor layer 115, for example, the first and second feet 72, 73) may be positioned higher than the locations of the bottom points 75 and 76, and lower than the top surface of the first semiconductor layer 115. These merged pits are a collection of two or more pits, which, when viewed from above, appear as long-length defects.

Also, in the first semiconductor layer 115, first feet 72 having a first depth D4 may be provided in the form of a merged pit, and the merged pit has a boundary portion between two bottoms. It may be disposed lower than the upper surface of the semiconductor layer 115, but is not limited thereto.

The fourth semiconductor layer 114 includes a plurality of semiconductor layers, for example, a first nitride layer 41 and a second nitride layer 42 on the first semiconductor layer 115. The first nitride layer 41 and the second nitride layer 42 may be repeatedly stacked with two layers having one cycle, for example, may be formed in 2 to 5 cycles. The first nitride layer 41 may be contacted on the first semiconductor layer 115 or the second nitride layer 42 may be contacted.

The first nitride layer 41 may be formed of a nitride semiconductor having aluminum (Al), for example, an AlGaN-based semiconductor such as AlGaN or InAlGaN. The composition ratio of aluminum in the first nitride layer 41 may range from 5% to 20%. In the case of the InAlGaN, the aluminum composition ratio is in the range of 5% to 20%, and the composition ratio of the indium (In) may be less than the composition ratio of the aluminum, for example, 5% or less. The first nitride layer 41 includes a first conductive dopant, for example, an N-type dopant. The first nitride layer 41 may have a thickness in the range of 0.5 nm to 5 nm, for example, 0.5 nm to 2 nm, and a thickness smaller than the first depth D4 of the first foot 72, for example, 1/ It may be formed to a thickness of 3 times or less.

The second nitride layer 42 may be formed of a nitride semiconductor different from the first nitride layer 41. The second nitride layer 42 may be formed of InGaN or GaN, and in the case of InGaN, the composition ratio of indium (In) may be 7% or less.

The second nitride layer 42 may be formed in a thickness in the range of 0.5 nm to 5 nm, for example, 0.5 nm to 2 nm, and a thickness smaller than the first depth D4 of the first foot 72, for example, 1/ It may be formed to a thickness of 3 times or less. The second nitride layer 42 may be formed to have the same thickness or a thinner thickness than the first nitride layer 41.

When the first nitride layer 41 is grown on the first semiconductor layer 115, it is formed on the first and second feet 72, 73, and at this time, a portion of the second feet 73 is filled. Will grow. That is, as the first nitride layer 41 grows by filling the depths, that is, the smaller pits, the second feet 73 may gradually become smaller pits.

Since the second nitride layer 42 is grown in a mode in which vertical growth is promoted, the pits 72 and 73 existing in the second nitride layer 42 are maintained.

By repeatedly growing the first nitride layer 41 and the second nitride layer 42, the relatively small sized pits, for example, the second feet 73, by the plurality of first nitride layers 41 Can be filled and removed, and the first feet 72 remain. The cycles of the first and second nitride layers 41 and 42 may be stacked in 2 to 5 cycles, and any one of the first and second nitride layers 41 and 42 may be further formed. It is not limited.

By removing the second feet 73 in the fourth semiconductor layer 114, only pits of uniform size can be provided. In addition, by removing the second feet 73 connected to the first feet 72, the merged feet can be provided as individual feet, thereby reducing the area of the merged feet, such as a valley. Accordingly, the first feet 72 or pits having a uniform size may be exposed on the surface of the fourth semiconductor layer 114. The uniformly sized pits include pits having a depth of 15 nm or more, and the removed pits include pits having a depth of less than 15 nm.

The pit density of the entire upper surface of the fourth semiconductor layer 114 is smaller than the pit density of the entire upper surface of the fourth semiconductor layer 114.

The active layer 116 is disposed on the fourth semiconductor layer 114, and the active layer 116 has pits 71 having a size corresponding to the first feet 71, and the plurality of barrier layers 63 ), and holes 61A are disposed in the plurality of well layers 61 in regions corresponding to the first feet 72. Accordingly, the light emitting area and the non-light emitting area can be clearly divided and provided by the pits 71 of uniform size. In addition, by blocking the propagation of the small size of the pits to the active layer 116, it is possible to reduce the non-emission area.

6 is a side sectional view showing a light emitting device according to a third embodiment. In describing the third embodiment, for the same parts as the first embodiment, the description of the first embodiment will be referred to.

Referring to FIG. 6, the light emitting device includes a substrate 111 having a plurality of convex portions 112, a buffer layer 113, a first semiconductor layer 115, an active layer 116, and a second semiconductor over the active layer 116 It includes a layered structure of the layer 117 and the third semiconductor layer 119.

The substrate 111 may use a light-transmissive, insulating or conductive substrate, for example, sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge, Ga ₂ O ₃ At least one can be used. The thickness of the substrate 111 includes a range of 120㎛ to 500㎛, the refractive index may be formed of a material of 2.4 or less, for example, 2 or less. The C surface of the sapphire substrate is relatively easy to grow the nitride film, and is mainly used as a substrate for nitride growth because it is stable at high temperatures.

The substrate 111 includes a plurality of convex portions 112. The plurality of convex portions 112 protrude from the substrate 111 in the direction of the active layer 116, and the shape may be a hemispherical shape, a convex dome-shaped lens shape, or a convex lens shape in a three-dimensional shape. Other shapes of the convex portion 112 may include a polygonal shape that is a three-dimensional structure, but is not limited thereto.

The plurality of convex portions 112 are disposed spaced apart from each other, and viewed from above, may be arranged in a lattice shape or a matrix shape or a stripe shape. The intervals between the plurality of convex portions 112 may be formed at regular intervals, irregular intervals, or random intervals, but are not limited thereto. The plurality of convex portions 112 may convert a critical angle of incident light to improve light extraction efficiency.

The ratio of the width at the bottom of the convex portion 112 and the spacing between the convex portions may be about 1:1 to 4:2, and the width of the convex portion 112 includes a range of 3 μm±0.5 μm. And, the spacing between the convex portions, for example, includes a range of 2㎛ ± 0.5㎛, the height of each convex portion may be formed in a range of 0.8㎛ ~ 2.5㎛.

The buffer layer 113 is disposed on a flat upper surface of the substrate 111 and may contact the curved surface of the convex portion 112. A part of the buffer layer 113 is not illustrated, but may also be disposed on the apex of the convex portion 112, but is not limited thereto.

A first semiconductor layer 115 is formed on the buffer layer 113, and the first semiconductor layer 115 is combined on the convex portion 112. At this time, a potential 65 may be formed in a region overlapping with the convex portion 112, propagated in the upper surface direction of the first semiconductor layer 115, and each potential 65 is connected to the pit 71. . Dislocations 65 disposed on the convex portion 112 may be merged with dislocations (not shown) generated in a region other than the convex portion 112, but are not limited thereto.

The plurality of pits 71 disposed on the first semiconductor layer 115 corresponds to the convex portion 112. The active layer 116 includes a well layer 61 having a plurality of holes 61A and a barrier layer 63 having a pit 71 in an area corresponding to the plurality of holes 61A, and It can be divided into a non-emission region.

7 is a structure in which electrodes are disposed on the light emitting device of FIG. 1.

Referring to FIG. 7, the light emitting device 101 is disposed on the substrate 111, the first semiconductor layer 115, the active layer 116, the second and third semiconductor layers 117 and 119, and the third semiconductor layer 119. It includes a current diffusion layer 151, a first electrode 153 disposed on the first semiconductor layer 115, and a second electrode 155 on the current diffusion layer 151.

The current spreading layer 151 covers 70% or more of the entire upper surface of the third semiconductor layer 119, and is supplied by diffusing the current. The current diffusion layer 151 may include metal or transparent metal. The current diffusion layer 151 is, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAO), indium gallium zinc oxide (IGZO), indium indium (GTO) It is selected from gallium tin oxide (AZO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), ZnO, IrOx, RuOx, and NiO, and may be formed as at least one layer. The current diffusion layer 151 may be formed of a reflective electrode layer, and the material may be selectively formed of Al, Ag, Pd, Rh, Pt, Ir, and alloys of two or more of them.

The second electrode 155 may be formed on the third semiconductor layer 119 and/or the current diffusion layer 151, and may include an electrode pad. The second electrode 155 may further have a current diffusion pattern of an arm structure or a finger structure. The second electrode 155 is a metal having characteristics of an ohmic contact, an adhesive layer, and a bonding layer, and may be non-transmissive, but is not limited thereto.

The second electrode 155 may be formed of 40% or less, for example, 20% or less of the upper surface area of the third semiconductor layer 119, but is not limited thereto.

The first electrode 153 is disposed on the first semiconductor layer 115. The first electrode 153 and the second electrode 155 are Ti, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, Ni, Si, Ge, Ag, and Au, and It can be selected from alternative alloys.

An insulating layer (not shown) may be further formed on the surface of the semiconductor layers 113-121, and the insulating layer may prevent shorts between layers between semiconductor layers and prevent moisture penetration.

8 is a view showing another electrode arrangement example of the light emitting device of FIG. 1. Descriptions of some components of FIG. 8 will be referred to the descriptions of FIGS. 1 and 7.

Referring to FIG. 8, the light emitting device 102 includes a first electrode 181 on the first semiconductor layer 115 and a second electrode 170 on the bottom.

The substrate 111 and the buffer layer 113 of FIG. 1 can be removed by physical or/and chemical methods. The first semiconductor layer 115 includes a conductive semiconductor layer, for example, an n-type semiconductor layer. The removal method of the substrate 111 may be removed by a physical method (for example, laser lift off) or/and a chemical method (wet etching, etc.), and other buffer layers may also be removed to expose the first semiconductor layer 115. give. Isolation etching is performed through a direction in which the substrate 111 is removed to form a first electrode 181 on the first semiconductor layer 115. The first electrode 181 may be disposed in different regions, and may be formed with an arm pattern or a bridge pattern, but is not limited thereto. Some regions of the first electrode 181 may be used as pads to which wires (not shown) are bonded.

A second electrode 170 is disposed under the third semiconductor layer 119. The second electrode 170 may include a plurality of conductive layers, for example, a contact layer 165, a reflective layer 167, a bonding layer 169, and a conductive support member 173.

The contact layer 165 is a permeable conductive material or a metal material, for example, a low conductivity material such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, or a metal of Ni or Ag. A reflective layer 167 is formed under the contact layer 165, and the reflective layer 167 is composed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, and combinations thereof. It may be formed of a structure comprising at least one layer of a material selected from the group. A portion of the reflective layer 167 may be contacted under the third semiconductor layer 119, and may be ohmic contacted with a metal or ohmic contact with a low-conductivity material such as ITO, but is not limited thereto.

A bonding layer 169 is formed under the reflective layer 167, and the bonding layer 169 can be used as a barrier metal or a bonding metal, and the material thereof is, for example, Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, and Ta and optional alloys.

A conductive support member 173 is formed under the bonding layer 169, and the conductive support member 173 may be a metal or carrier substrate, for example, copper (Cu-copper), gold (Au-gold), nickel (Ni-nickel), molybdenum (Mo), copper-tungsten (Cu-W), carrier wafers (eg, Si, Ge, GaAs, ZnO, SiC, etc.) may be formed of a conductive material. The conductive support member 173 may be implemented as a conductive sheet as another example.

A light extraction structure 59 such as roughness may be formed on the top surface of the first semiconductor layer 115. An insulating layer (not shown) may be formed on the surface of the semiconductor layers 113-121, and the insulating layer may be further formed on the light extraction structure 59.

A current blocking layer 161 is disposed in a region between the second electrode 170 and the third semiconductor layer 119 that corresponds to the first electrode 181, and the second electrode 170 and A protective layer 163 may be disposed on an outer circumference of the region between the third semiconductor layers 119. The current blocking layer 161 and the protective layer 163 may be formed of an insulating material or a transparent conductive material, but are not limited thereto. The current blocking layer 161 and the protective layer 163 may be formed of the same material or different materials, but are not limited thereto.

<Light emitting device package>

9 is a view showing a light emitting device package having the light emitting device of FIG. 7.

Referring to FIG. 9, the light emitting device package 200 includes a body 221, a first lead electrode 211 and a second lead electrode 213 having at least a portion disposed on the body 221, and the body ( The light emitting element 241 electrically connected to the first lead electrode 211 and the second lead electrode 213 on the 221, and a molding member covering the light emitting element 241 on the body 221 (231).

The body 221 may be formed of a silicon material, a synthetic resin material, or a metal material. When viewed from above, the body 221 may be formed with a cavity 225 inside and a surface inclined with respect to the bottom of the cavity around the cavity 225.

The first lead electrode 211 and the second lead electrode 213 are electrically separated from each other, and may be formed to penetrate inside the body 221. That is, a portion of the first lead electrode 211 and the second lead electrode 213 may be disposed inside the cavity 225 and the other portion may be disposed outside the body 221.

The first lead electrode 211 and the second lead electrode 213 supply power to the light emitting element 241 and reflect light generated from the light emitting element 241 to increase light efficiency. The heat generated by the light emitting element 241 may function to be discharged to the outside. The first and second lead electrodes 211 and 213 may be formed of a metal material and are separated by a gap portion 223.

The light emitting device 241 may be installed on the body 221 or on the first lead electrode 211 or/and the second lead electrode 213.

The light emitting device 221 may be connected to the first lead electrode 211 by a first wire 242 and may be connected to the second lead electrode 213 by a second wire 243, but is not limited thereto.

The molding member 231 may surround the light emitting element 241 to protect the light emitting element 241. In addition, a phosphor is included in the molding member 231, and the wavelength of light emitted from the light emitting element 241 may be changed by the phosphor.

<Lighting system>

The light emitting device or the light emitting device package according to the embodiment may be applied to a lighting system. The lighting system includes a structure in which a plurality of light emitting elements or a light emitting element package is arrayed, and includes the display device shown in FIGS. 10 and 11, the lighting device shown in FIG. 12, a lighting lamp, a traffic light, a vehicle headlight, and a display board Etc. may be included.

10 is an exploded perspective view of a display device according to an exemplary embodiment.

Referring to FIG. 10, the display device 1000 includes a light guide plate 1041, a light emitting module 1031 providing light to the light guide plate 1041, a reflective member 1022 under the light guide plate 1041, and the A bottom cover 1011 for storing the optical sheet 1051 on the light guide plate 1041, the display panel 1061 on the optical sheet 1051, the light guide plate 1041, the light emitting module 1031, and the reflective member 1022. ) May be included, but is not limited thereto.

The bottom cover 1011, the reflective sheet 1022, the light guide plate 1041, and the optical sheet 1051 may be defined as a light unit 1050.

The light guide plate 1041 serves to diffuse the light provided from the light emitting module 1031 and to make a surface light source. The light guide plate 1041 is made of a transparent material, for example, acrylic resin series such as PMMA (polymethyl metaacrylate), PET (polyethylene terephthlate), PC (poly carbonate), COC (cycloolefin copolymer) and PEN (polyethylene naphthalate) It may include one of the resin.

The light emitting module 1031 is disposed on at least one side of the light guide plate 1041 to provide light to at least one side of the light guide plate 1041, and ultimately acts as a light source of the display device.

The light emitting module 1031 includes at least one, and may directly or indirectly provide light from one side of the light guide plate 1041. The light emitting module 1031 includes a board 1033 and a light emitting device package 200 according to the embodiment disclosed above, and the light emitting device package 200 may be arranged on the board 1033 at predetermined intervals. have. The board may be a printed circuit board, but is not limited thereto. In addition, the board 1033 may include a metal core PCB (MCPCB, metal core PCB), a flexible PCB (FPCB, flexible PCB), and the like, but is not limited thereto. When the light emitting device package 200 is mounted on a side surface of the bottom cover 1011 or a heat radiation plate, the board 1033 may be removed. A portion of the heat dissipation plate may contact the top surface of the bottom cover 1011. Therefore, heat generated in the light emitting device package 200 may be discharged to the bottom cover 1011 via the heat dissipation plate.

The plurality of light emitting device packages 200 may be mounted on the board 1033 so that an emission surface from which light is emitted is spaced apart from the light guide plate 1041 by a predetermined distance, but is not limited thereto. The light emitting device package 200 may directly or indirectly provide light to a light incident portion, which is one side of the light guide plate 1041, but is not limited thereto.

The reflective member 1022 may be disposed under the light guide plate 1041. The reflection member 1022 reflects light incident on the lower surface of the light guide plate 1041 and supplies the light to the display panel 1061, thereby improving the brightness of the display panel 1061. The reflective member 1022 may be formed of, for example, PET, PC, or PVC resin, but is not limited thereto. The reflective member 1022 may be an upper surface of the bottom cover 1011, but is not limited thereto.

The bottom cover 1011 may accommodate the light guide plate 1041, the light emitting module 1031, and the reflective member 1022. To this end, the bottom cover 1011 may be provided with an accommodating portion 1012 having a box shape with an open top surface, but is not limited thereto. The bottom cover 1011 may be combined with a top cover (not shown), but is not limited thereto.

The bottom cover 1011 may be formed of a metal material or a resin material, and may be manufactured using a process such as press molding or extrusion molding. In addition, the bottom cover 1011 may include a metal or non-metal material having good thermal conductivity, but is not limited thereto.

The display panel 1061 is, for example, an LCD panel, and includes first and second substrates of transparent materials facing each other, and a liquid crystal layer interposed between the first and second substrates. A polarizing plate may be attached to at least one surface of the display panel 1061, and is not limited to the attachment structure of the polarizing plate. The display panel 1061 transmits or blocks light provided from the light emitting module 1031 to display information. The display device 1000 may be applied to various types of portable terminals, notebook computer monitors, laptop computer monitors, and video display devices such as televisions.

The optical sheet 1051 is disposed between the display panel 1061 and the light guide plate 1041 and includes at least one light-transmitting sheet. The optical sheet 1051 may include at least one of a sheet such as, for example, a diffusion sheet, a horizontal/vertical prism sheet, and a brightness enhanced sheet. The diffusion sheet diffuses incident light, and the horizontal or/and vertical prism sheet condenses the incident light to the display panel 1061, and the luminance enhancement sheet reuses the lost light to improve luminance. Let me do it. In addition, a protective sheet may be disposed on the display panel 1061, but is not limited thereto.

An optical member on the light path of the light emitting module 1031 may include the light guide plate 1041 and the optical sheet 1051, but is not limited thereto.

11 is a view showing a display device having a light emitting device package according to an embodiment.

Referring to FIG. 11, the display device 1100 includes a bottom cover 1152, a board 1120 in which the light emitting device package 200 disclosed above is arrayed, an optical member 1154, and a display panel 1155. .

The board 1120 and the light emitting device package 200 may be defined as a light emitting module 1060. The bottom cover 1152, at least one light emitting module 1060, and the optical member 1154 may be defined as a light unit 1150.

The bottom cover 1152 may include a storage unit 1153, which is not limited thereto.

The optical member 1154 may include at least one of a lens, a light guide plate, a diffusion sheet, a horizontal and vertical prism sheet, and a brightness enhancement sheet. The light guide plate may be made of PC material or poly methy methacrylate (PMMA) material, and the light guide plate may be removed. The diffusion sheet diffuses incident light, and the horizontal and vertical prism sheets converge the incident light to the display panel 1155, and the luminance enhancement sheet reuses the lost light to improve luminance. .

The optical member 1154 is disposed on the light emitting module 1060, and performs light or surface diffusion of light emitted from the light emitting module 1060, or diffusion or condensing.

A plurality of boards 1120 may be disposed in the bottom cover 1152, and a light emitting device package 200 or a light emitting device (ie, LED chip) of an embodiment may be arranged on the plurality of boards 1120. .

12 is a view showing a lighting device having a light emitting device package according to an embodiment.

Referring to FIG. 12, the lighting device according to the embodiment may include a cover 2100, a light source module 2200, a radiator 2400, a power supply unit 2600, an inner case 2700, and a socket 2800. Can be. In addition, the lighting device according to the embodiment may further include any one or more of the member 2300 and the holder 2500. The light source module 2200 may include a light emitting device according to an embodiment.

For example, the cover 2100 may have a shape of a bulb or a hemisphere, a hollow portion, and a portion of the cover 2100. The cover 2100 may be optically coupled to the light source module 2200. For example, the cover 2100 may diffuse, scatter, or excite light provided from the light source module 2200. The cover 2100 may be a kind of optical member. The cover 2100 may be combined with the heat radiator 2400. The cover 2100 may have a coupling portion coupled to the heat radiator 2400.

A milky white coating may be coated on the inner surface of the cover 2100. The milky white paint may include a diffusion material that diffuses light. The surface roughness of the inner surface of the cover 2100 may be greater than the surface roughness of the outer surface of the cover 2100. This is for light from the light source module 2200 to be sufficiently scattered and diffused to be emitted to the outside.

The material of the cover 2100 may be glass, plastic, polypropylene (PP), polyethylene (PE), polycarbonate (PC), or the like. Here, polycarbonate has excellent light resistance, heat resistance, and strength. The cover 2100 may be transparent so that the light source module 2200 is visible from the outside, and may be opaque. The cover 2100 may be formed through blow molding.

The light source module 2200 may be disposed on one surface of the heat radiator 2400. Thus, heat from the light source module 2200 is conducted to the heat sink 2400. The light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250.

The member 2300 is disposed on the upper surface of the radiator 2400, and has a plurality of light source parts 2210 and guide grooves 2310 into which the connector 2250 is inserted. The guide groove 2310 corresponds to the substrate and connector 2250 of the light source unit 2210.

The surface of the member 2300 may be coated or coated with a light reflective material. For example, the surface of the member 2300 may be coated or coated with a white paint. The member 2300 reflects light that is reflected on the inner surface of the cover 2100 and returns to the direction of the light source module 2200 in the direction of the cover 2100 again. Therefore, it is possible to improve the light efficiency of the lighting device according to the embodiment.

The member 2300 may be made of, for example, an insulating material. The connection plate 2230 of the light source module 2200 may include an electrically conductive material. Therefore, electrical contact may be made between the heat sink 2400 and the connection plate 2230. The member 2300 may be formed of an insulating material to block electrical shorts between the connection plate 2230 and the heat radiator 2400. The radiator 2400 radiates heat by receiving heat from the light source module 2200 and heat from the power supply unit 2600.

The holder 2500 closes the storage groove 2719 of the insulating portion 2710 of the inner case 2700. Therefore, the power supply unit 2600 accommodated in the insulation portion 2710 of the inner case 2700 is sealed. The holder 2500 has a guide protrusion 2510. The guide protrusion 2510 may include a hole through which the protrusion 2610 of the power supply unit 2600 passes.

The power supply unit 2600 processes or converts an electrical signal provided from the outside and provides it to the light source module 2200. The power supply unit 2600 is accommodated in a storage groove 2719 of the inner case 2700 and is sealed inside the inner case 2700 by the holder 2500.

The power supply unit 2600 may include a protrusion 2610, a guide 2630, a base 2650, and a protrusion 2670.

The guide portion 2630 has a shape protruding from the side of the base 2650 to the outside. The guide part 2630 may be inserted into the holder 2500. A plurality of parts may be disposed on one surface of the base 2650. The plurality of components include, for example, a DC converter for converting AC power provided from an external power source into DC power, a driving chip controlling driving of the light source module 2200, and ESD for protecting the light source module 2200. (ElectroStatic discharge) may include a protection element, but is not limited thereto.

The protrusion 2670 has a shape protruding from the other side of the base 2650 to the outside. The protrusion 2670 is inserted into the connection portion 2750 of the inner case 2700 and receives an electrical signal from the outside. For example, the protrusion 2670 may be provided equal to or smaller than the width of the connecting portion 2750 of the inner case 2700. Each end of the "+ wire" and the "- wire" may be electrically connected to the protrusion 2670, and the other end of the "+ wire" and the "- wire" may be electrically connected to the socket 2800.

The inner case 2700 may include a molding unit together with the power supply unit 2600 therein. The molding portion is a portion in which the molding liquid is hardened, so that the power supply unit 2600 can be fixed inside the inner case 2700.

The features, structures, and effects described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, and the like exemplified in each embodiment may be combined or modified for other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiments have been mainly described above, these are merely examples and do not limit the present invention, and those skilled in the art to which the present invention pertains are exemplified above without departing from the essential characteristics of this embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be implemented by modification. And differences related to these modifications and applications should be construed as being included in the scope of the invention defined in the appended claims.

65: dislocation 41,42: nitride layer
61: well layer 63: barrier layer
61A, 61B: Hall 71, 72, 73: feet
101, 102: light emitting element 111: substrate
112: convex portion 114: fourth semiconductor layer
115: first semiconductor layer 116: active layer
119: 3rd semiconductor layer

Claims (15)

A first semiconductor layer comprising a plurality of first feet concave from the top surface;
An active layer having a plurality of well layers and a plurality of barrier layers on the first semiconductor layer; And
A second semiconductor layer on the active layer,
The well layer and the barrier layer are alternately stacked,
The plurality of well layers includes a plurality of holes in an area corresponding to the plurality of first feet, and
A portion of the barrier layer is a light emitting device that is disposed in the plurality of holes. According to claim 1,
A light emitting device in which some regions of adjacent barrier layers are disposed in the hole of the well layer and are in contact with each other. According to claim 2,
A first barrier layer closest to the first semiconductor layer among the plurality of barrier layers,
A portion of the first barrier layer formed in the hole contacts the plurality of first feet and the side surfaces of the hole. According to claim 1,
The hole is a light emitting device that overlaps with the area of the first foot in the vertical direction. According to claim 3,
The sidewall of the hole is a light emitting device that contacts a portion of the barrier layer. The method of claim 5,
The sidewall of the hole includes a vertical surface or a sloped surface. delete delete delete delete delete delete delete delete delete

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