KR102096152B1 - Recessed Channel Type Transistor having Improved Current-leakage Characteristics - Google Patents

Abstract

A gate 8 in which a predetermined portion is buried in a state in which a gate insulating layer 7 is interposed in the silicon body 2 between the drain region and the source region and the silicon body 2 between the drain region and the source region. Regarding a transistor having a non-planar channel including a, the drain region and the source region are portions of the silicon body 2 doped with a doping material, and the silicon body 2 is filled with an insulator 10. , Based on the height direction (Y-axis direction) of the silicon body 2, the upper surface of the insulator 10 is higher than the lower surface of the gate insulating film 7 embedded in the silicon body 2 At the same time, it is characterized by having a non-planar channel, characterized in that located in the drain region or the source region.

Description

Recessed Channel Type Transistor having Improved Current-leakage Characteristics}

The present invention relates to a semiconductor device, and more particularly, compared to a transistor having a non-planar channel such as a conventional recessed channel array transistor (RCA) and a saddle fin transistor (saddle finFET), GIDL (Gate Induced Drain Leakage) ) Is a transistor having a non-planar channel with improved leakage current characteristics.

Recently, the gate size of a device for DRAM cell transistor technology has been actively studied in a region of 100 nm or less. The biggest technical problem in reducing the gate size is the generation of a leakage current known as the so-called short channel effect.

The short channel effect is drained by the drain voltage even when the transistor is off when the length of the gate is shortened due to the tendency of semiconductor miniaturization, that is, the distance between the source and the drain (see FIGS. 1 (a) and 1 (b)). As a phenomenon in which current flows, it is a problem that inevitably occurs as the size of the transistor decreases.

Furthermore, as the gate size decreases due to the characteristics of DRAM cell transistors, the gate insulating film thickness cannot be reduced and the source / drain doping depth cannot be made shallow compared to conventional logic MOSFETs. Have Therefore, in the case of a conventional MOSFET device having a flat channel, a short channel effect is a major obstacle in miniaturization of the device.

One of the methods for solving this problem is a semiconductor device called a Recessed Channel Array Transistor (RCT) that recesses a gate to make a non-planar channel as shown in FIG. 2. RCAT (Recessed Channel Array Transistor) can improve the short channel effect because the channel is longer than the conventional flat channel MOSFET. However, due to the structural difference from the MOSFET having a conventional flat channel, the change in threshold voltage due to the substrate bias is very large compared to the conventional flat channel structure, and as the channel becomes unflattened, the channel width becomes narrower and the current decreases. There is a disadvantage in that the driving ability is greatly reduced.

The semiconductor device proposed to overcome all of the shortcomings of the RCAT's low current driving capability and the MOSFET having a flat channel has a non-planar channel by immersing the gate as shown in FIG. 3, while the gate surrounds the channel region. It is a semiconductor device called a transistor (saddle FinFET, application number: 10-2004-0104560) having a saddle structure in the form of a gate. Hereinafter, a transistor having a saddle structure will be referred to as a saddle FinFET for convenience of description.

2 (b) is a perspective view of a Recessed Channel Array Transistor (RCA), and FIG. 2 (a) is a plan view of a Recessed Channel Array Transistor (RCA). FIG. 2 (c) is a cross-sectional view taken along the plane A-A 'in FIG. 2 (a), and FIG. 2 (d) is a cross-sectional view taken along B-B' in FIG. 2 (a). Figure 3 (b) is a perspective view of the saddle FinFET, Figure 3 (a) is a plan view of the saddle FinFET. FIG. 2 (c) is a cross-sectional view taken along the plane A-A 'in FIG. 2 (a), and FIG. 2 (d) is a cross-sectional view taken along B-B' in FIG. 2 (a).

In a typical MOSFET having a flat channel, the gate electrode is different from that located on the top of the silicon body (see FIG. 1), but in the recessed channel array transistor (RCA) and saddle FinFET, the bottom of the gate electrode 18 is wall-type. type) The silicon body 12 is buried with the gate insulating film 17 therebetween, and portions of the silicon body 12 located on both sides of the gate electrode 18 are doped to form the source / drain regions 19 do. In the transistor having the non-planar channel as described above, since the channel between the source region and the drain region becomes longer, a short channel effect can be reduced.

However, even in a transistor having a non-planar channel, the leakage current problem in the off state due to GIDL (Gate Induced Drain Leakage) has not been solved. GIDL is a phenomenon in which electrons are tunneled from the balance band (Ev) to the conduction band (Ec) due to the steep energy band difference between the drain and the gate, resulting in leakage current. The voltage applied to the drain region 19 and the gate electrode 18 is mainly applied to the gate insulating layer 17 and the drain region in the vicinity thereof. As the drain voltage increases, the voltage in these two regions becomes larger and the voltage of the energy band increases. The slope becomes larger. Since the leakage current problem caused by GIDL occurs due to the structural characteristics of the recessed gate, it also occurs in the RCAT (Recessed Channel Array Transistor), but the saddle FinFET increases the source / drain region and gate overlap due to the influence of the triple gate. The leakage current by GIDL is further increased.

In addition to the basic saddle FinFET of the type shown in FIG. 3, a MOS device having an improved saddle structure by controlling the source / drain region of the saddle FinFET and the overlap region of the gate (application number: 1020050082864) has been developed. However, even though MOSFETs having various types of non-planar channels have been developed, a solution that satisfactorily solves the leakage current problem caused by GIDL while maintaining current driving capability is still not provided.

The inventor of the present invention has developed and applied a technique of embedding an insulator in one of the drain or source regions in order to solve the above-mentioned problems (application number 10-2017-01210101, filed on September 20, 2017). Although the effect of reducing the leakage current was obtained through the above invention, the above invention was applied with a lightly doped drain (LDD) type process to keep the doping concentration of the overlapped region between the gate and drain (or source) regions low. As a target developed for transistors, the optimized insulator parameters (size and position) presented in the above invention are highly doped (HDD) whose doping concentration is maintained to an overlapped region between the gate and drain (or source) regions. It was confirmed that the optimal performance cannot be guaranteed in transistors with Drain-type processes.

For reference, LDD doping places a side wall around the gate to maintain a low doping concentration in some regions (regions where the gate and drain (or source) overlap) and to apply a high concentration of doping only near the rest of the contact region. HDD doping may be performed by doping the region where the gate and drain (or source) overlap directly without sidewalls.

Korean Patent Publication No. 10-2004-0092017 (2004.11.03.) United States Published Patent Publication US2017 / 0069764 (2017.03.09.)

The present invention is a non-planar type of a new structure capable of maintaining a proper current driving capability while solving the above-described technical problem of the conventional transistor having a non-planar channel, that is, a leakage current problem caused by GIDL when the transistor is off. It is an object to provide a transistor having a channel structure.

More specifically, in a transistor having a non-planar channel to which an HDD-type process is applied, an object of the present invention is to find a condition capable of minimizing leakage current.

The present invention is a gate in which at least a portion of a silicon body 2 in which a drain region and a source region are formed, and at least a part of which is buried in the silicon body 2 between the drain region and the source region, with a gate insulating film 7 interposed therebetween. Regarding a transistor having a non-planar channel including (8), the drain region and the source region are portions of the silicon body 2 doped with a doping material, and the silicon body 2 has an insulator 10 Is buried, based on the height direction (Y-axis direction) of the silicon body 2, the upper surface of the insulator 10 is higher than the lower surface of the gate insulating film 7 embedded in the silicon body 2 At the same time, it is characterized in that located in the drain region or the source region.

The drain region is formed by a Highly Dopped Drain (HDD) process, wherein the distance y in the height direction of the silicon body 2 between the upper surface of the insulator 10 and the lower surface of the gate insulating film 7 is the gate insulating film. (7) It is preferable that the α value divided by the depth D embedded in the silicon body 2 is 0.6 or more and 0.9 or less.

Furthermore, the shortest distance (x) in the horizontal direction (X-axis direction) between the insulator 10 and the gate insulating film 7 is the side of the silicon body 2 on the side where the insulator 10 is buried. The β value divided by the shortest distance (L) in the horizontal direction (X-axis direction) between the cross-section and the gate insulating film 7 is preferably 0.4 or less.

Here, the insulator may be a dielectric, preferably, may be composed of at least one material selected from SiO ₂ , Si3N ₄ , and HfO ₂ , ZrO ₂ . Alternatively, the insulator may be formed by a vacuum layer.

Furthermore, it is preferable that the insulator is formed in a hexahedral shape.

Among the transistors having a non-planar channel that can be applied according to the present invention, a voltage contour line between a drain and a gate generated when a drain voltage is applied can be changed by embedding an insulator in a portion of a drain region or a source region of a saddle FinFET. Was confirmed. According to the present invention, several transistors with the remaining non-planar channels also have the same type of voltage contour change.

In particular, it was confirmed through the present invention that the change in the voltage contour between the drain and the gate generated inside the saddle FinFET has an excellent effect on reducing leakage current by GIDL according to the parameters of the insulator found by the inventor (size of the insulator and buried position) Did.

1 shows a MOSFET according to the prior art.
Figure 2 shows a RCAT (Recessed Channel Array Transistor) according to the prior art.
Figure 3 shows a saddle FinFET according to the prior art.
Figure 4 shows a RCAT (Recessed Channel Array Transistor) according to the present invention.
5 shows a saddle FinFET according to the present invention.
6 shows a voltage distribution between a drain and a gate of a transistor having a non-planar channel to which an LDD process is applied.
7 shows a voltage distribution between a drain and a gate of a transistor having a non-planar channel to which an HDD process is applied.
8 is a conceptual diagram showing a doped region according to the LDD type and the HDD type.
9 is a graph showing the effect of a change in α, a parameter on the position of an insulator, on a leakage current in an LDD transistor.
10 is a graph showing the effect of a change in parameter α related to the position of an insulator on a driving current in an LDD transistor.
11 is a graph showing the effect of a change in β, a parameter on the position of an insulator, on a leakage current in an LDD transistor.
12 is a graph showing the effect of a change in β, a parameter on the position of an insulator, on a driving current in an LDD transistor.
13 is a graph showing the effect of a change in parameter α on the position of an insulator on a leakage current in an HDD transistor.
14 is a graph showing the effect of a change in β, a parameter on the position of an insulator, on a leakage current in an HDD transistor.
15 to 16 show the shape of a saddle FinFET according to various embodiments of the present invention.

Specific features and advantages of the present invention will become more apparent from the following description based on the accompanying drawings. Prior to this, if it is determined that a detailed description of known functions and configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, it should be noted that the detailed description is omitted.

4 and 5 respectively show the appearance of a Recessed Channel Array Transistor (RCA) and a saddle FinFET according to the present invention. Fig. 4 (b) is a perspective view of the RCAT according to the present invention, and Fig. 4 (a) is a plan view when the RACT according to the present invention is viewed from the top. FIG. 4 (c) is a cross-sectional view taken along A-A 'in FIG. 4 (a), and FIG. 4 (d) is a cross-sectional view taken along B-B' in FIG. 4 (a).

5 (b) is a perspective view of the saddle FinFET according to the present invention, and FIG. 5 (a) is a plan view of the saddle FinFET according to the present invention when viewed from the top. 5 (c) is a sectional view taken along A-A 'in FIG. 5 (a), and FIG. 5 (e) is a sectional view taken along B-B' in FIG. 5 (a). 5 (d) is a cross-sectional view taken along line C-C 'in FIG. 5 (a).

Between the RCAT (Recessed Channel Array Transistor) and the saddle FinFET applied according to the present invention, there is no difference in the improvement of the leakage current characteristic by GIDL as well as the change in other electrical characteristics. Explain.

There is no difference in the basic structure of the silicon body 2, the gate electrode 8 and the drain or source region 9 from the saddle FinFET according to the prior art. However, the present invention is different from the conventional saddle FinFET in that the insulator 10 is embedded in a predetermined depth of the drain region or the source region. 5 (b) and 5 (c), the insulator 10 is buried at a predetermined distance d1 from the top surface of the silicon body 2 in the drain region or the source region 9.

As the above insulator 10, various kinds of dielectric materials having a dielectric constant of 3 to 50 can be used, and SiO ₂ and Si ₃ N _4, which are most commonly used as insulators in semiconductor devices, are high, such as HfO ₂ and ZrO ₂ . -k materials can be used.

Furthermore, the leakage current reduction effect can be obtained not only by a general dielectric, but also by forming an air layer or a vacuum layer in the silicon body 2 that can exhibit properties such as dielectric.

The inventors of the present invention have found that it is possible to reduce the leakage current caused by GIDL (Gate Induced Drain Leakage) by appropriately adjusting the formation position of the insulator 10. GIDL is a phenomenon that occurs due to the tunneling of electrons between the drain and the gate to generate a leakage current. FIGS. 6 and 7 show voltage contour lines of the electric field formed in the drain region 9 when a voltage is applied to the drain.

For reference, the source / drain doping type of the transistor illustrated in FIG. 6 is a lightly doped drain (LDD) process in which a doping concentration of an overlapped region between a gate and a drain (or source) region is kept low. The doping form of the transistor shown in 7 is a high doped drain (HDD) process in which the doping concentration is maintained to an overlapped region between the gate and drain (or source) regions. As the doping material, Group 5 elements such as antimony (Sb), arsenic (As), and phosphorus (P), or Group 3 elements such as boron (B), gallium (Ga), and indium (In) may be used.

8 (a) is a drain and source doped form in the LDD type transistor (saddle FinFET), and FIG. 8 (b) is a schematic view showing a form in which the drain and source are doped in the HDD type transistor. Here, the dotted line indicates the insulator, and the position and size of the insulator are important parameters for obtaining the technical effect that the present invention seeks to be described in detail below.

6 (a) shows voltage contour lines in a conventional saddle FinFET in which the insulator 10 is not embedded in the silicon body 2, and FIGS. 6 (b) to 6 (f) are insulators of various sizes and locations ( 10) shows the voltage contour line in the saddle FinFET in the state where it is buried in the drain region, where the insulator is marked with a black dotted line. For reference, what is shown in FIG. 6 is that the LDD type process is applied.

7 (a) shows voltage contour lines in a conventional saddle finFET to which an HDD type process is applied, and FIGS. 7 (b) to 7 (d) show various types of insulators 10 (SiO2, Si3N4, HfO2) drained. It shows the voltage contour in the saddle FinFET in the region embedded state.

Here, the expression “drain region” refers to a region in which drain doping is performed, and does not mean that the insulator 10 is formed separately from the doped region, but means that the insulator 10 is located in the doped region. .

Even if the same voltage was applied to the drain, it was confirmed that the shape of the voltage contour line changed due to the presence of the insulator. That is, it can be seen that the spacing of the voltage contour lines is adjusted by the insulator 10 located in the drain region.

As the distance between the drain region and the gate is denser, the number of electrons tunneling from Ev to Ec, which is the cause of leakage current due to GIDL, increases. Between the drain region and the gate by appropriately adjusting the position of the insulator. It was confirmed through experiments that it was possible to change the shape of the voltage contour and reduce the amount of actual leakage current.

The inventor of the present invention confirmed the amount of leakage current by GIDL while varying the size and position of the insulator, and confirmed the parameters that most affect the leakage current reduction. Looking at Figures 4 (c) and 5 (c), it can be seen that various variables showing the size and position of the insulator are shown.

Here, the distance y in the Y-axis direction between the top of the insulator 10 and the bottom of the gate insulating film 7 and in the X-axis direction between one side of the insulator 10 and one side of the gate insulating film 7 Distance (x) was the most influential parameter for the reduction of leakage current.

The size (d2) in the height direction (Y-axis direction) of the insulator 10 is such that if the bottom of the insulator is only down below the bottom of the gate 8, the size (d2) greatly affects the GIDL improvement. It was confirmed that it was not insane.

For convenience of description, hereinafter, the distance D in the Y-axis direction between the lower ends of the gate insulating films 7 of the insulator 10 is the depth D in which the gate insulating films 7 are embedded in the silicon body 2. The dimensionless variable α obtained by dividing by is used, that is, the relative distance in the Y-axis direction. Furthermore, the indifference obtained by dividing the distance x in the X-axis direction between the insulator 10 and the gate 7 by the distance L from one side of the silicon body 2 to one side of the gate insulating film 7 Use the originalized variable β, the relative distance in the X-axis direction.

That is, α denotes the distance relationship between the insulator 10 and the gate 8 in the height direction (Y-axis direction), wherein 0 or less indicates that the top of the insulator 10 is lower than the shortest of the gate insulating film 7 That is, 1 means that the upper surface of the insulator 10 is in contact with the upper surface of the silicon body 2.

And when β is 0, it means that the insulator 10 is almost in contact with the gate insulating film 7, and when β is close to 1, it means that the thickness of the insulator 10 is thin and almost absent.

Hereinafter, “Pi-FinFET” used in the graphs of FIGS. 9 and 10 refers to a transistor according to the present invention, and an LDD type process is applied.

9 is a graph showing a change trend of the leakage current Ioff measured while changing the α value, and FIG. 10 is a graph showing a change trend of the drive current Ion measured while changing the α value.

The leakage current Ioff is a current flowing in the drain region by the voltage applied to the drain when the gate 8 is turned off, and the current must be 0 or kept at a very small value as much as possible for the transistor to operate normally. The asterisk in FIG. 7 is the value of the leakage current obtained in a conventional saddle FinFET without filling the insulator 10. And the rest of the graphs are the values of the leakage current obtained by changing the α value, and experiments were conducted on various βs.

As the α value increased, it was found that the leakage current Ioff tended to decrease as a whole, and the tendency was not significantly affected by the difference in the β value. And when the α value is 0.2 or more, it was confirmed that the amount of leakage current (Ioff) generated in the conventional saddle FinFET is certainly reduced. As α increases, the amount of leakage current (Ioff) decreases continuously, but when α becomes 1, the insulator 10 is exposed outside the silicon body 2 and the drain region itself disappears. Since carriers must be able to move to the drain region, it is preferable to set α to about 0.9 as an upper limit.

10 is a driving current (Ion) generated when the gate is on, which is a normal current for the transistor to operate, so it is not desirable to reduce the value by an insulator. In FIG. 10, an asterisk means a driving current (Ion) in a conventional saddle FinFET, and the trend of changing the driving current (Ion) while changing α was investigated. While the leakage current (Ioff) is sensitive to changes in the α value, the driving current (Ion) is not significantly affected by the presence or absence of the insulator or the α value, and is not significantly different from the driving current (Ion) in a conventional saddle finFET. You can see that it has a value.

Therefore, from the data of FIGS. 9 and 10, the presence of the insulator 10 does not significantly affect the driving current Ion, and greatly affects the reduction of the leakage current Ioff, thereby greatly improving the saddle FinFET performance. I was able to check the zoom.

FIG. 11 summarizes the amount of leak current Ioff irradiated while changing β. The larger the α value, the greater the leakage current (Ioff) reduction effect, whereas the β value was found to have a significant leakage current (Ioff) reduction effect in a specific range. A reduction effect could be obtained. More preferably, it can be seen that the leakage current (Ioff) reduction effect is maximized when it is 0.3 or more and 0.45 or less. For reference, the asterisk here indicates the value of the leakage current obtained in a conventional saddle FinFET without an insulator.

FIG. 12 summarizes the amount of driving current (Ion) irradiated while changing β, and shows a tendency that the smaller the value of β, the smaller the value of driving current (Ion). However, it was confirmed that in the region in which the reduction effect of the leakage current Ioff is remarkable, that is, the β value is 0.2 or more and 0.7 or less, the reduction width of the driving current Ion is not large enough to have a substantial effect on the driving of the saddle finFET. For reference, the asterisk here indicates the value of the driving current obtained in a conventional saddle FinFET without an insulator.

Therefore, from the graphs of FIGS. 11 and 12, when the β value is within a predetermined range, the presence of the insulator 10 does not significantly affect the driving current Ion, but greatly affects the reduction of the leakage current Ion. As a result, it was confirmed that it greatly helps to improve the performance of the saddle FinFET.

Hereinafter, “saddle FinFET” used in the graphs of FIGS. 13 and 14 refers to a transistor according to the present invention, and is applied to an HDD type process.

13 is a graph showing a variation trend of the leakage current Ioff measured while changing the α value, and FIG. 14 is a graph showing a variation trend of the leakage current Ioff measured while changing the β value.

Leakage current (Ioff) is a current generated when the gate (8) is turned off, and occurs mainly in the region where the gate and drain regions overlap. It is as described above that the current must be 0 or kept as small as possible for the transistor to operate normally.

 The asterisks in FIGS. 13 and 14 are the values of the leakage current obtained in the conventional saddle FinFET without embedding the insulator 10. And the rest of the graphs are the values of the leakage current obtained by changing the α value, and experiments were conducted on various βs.

Referring to FIG. 13, it was confirmed that the leakage current (Ioff) was significantly reduced as the α value was increased from the value of α being 0.4 or more, and the leakage was practically significant in the region where the α value was 0.6 or more and 0.9 or less. The amount of current (Ioff) reduction was obtained.

 And Figure 14 summarizes the amount of leakage current (Ioff) irradiated while changing the β value. In the range where the β value was 0.4 or less, a practically significant leakage current (Ioff) reduction effect was observed. As the β value decreased, it was confirmed that the leakage current reduction effect was consistent. The lower limit of the β value can converge to 0 (the state where the insulator is almost in contact with the gate), but is preferably 0.1 or more from a practical point of view (in terms of ease of manufacture).

In conclusion, it can be seen that in the HDD type saddle FinFET, the α value, which is a parameter representing the relative depth of the insulator, is 0.6 or more and 0.9 or less, and the β value is 0.4 or less, and the effect of reducing the leakage current (Ioff) is maximized.

15 and 16 illustrate further embodiments according to the present invention, and the technical idea according to the present invention, that is, an insulator may be embedded in a predetermined portion of a drain region or a source region in various conventional saddle FinFETs. It is showing. In the embodiments shown in FIGS. 15 to 16, even if there are some differences in the structure of the saddle FinFET, the parameters of the insulator described above can be applied as it is.

In each figure, (b) is a perspective view of the saddle FinFET, (a) is a plan view of the saddle FinFET from the top, (c) is a cross-section cut along A-A 'in (a), (d) Is a cross-section of C-C 'in (a), and (e) is a cross-section of B-B' in (a).

The saddle FinFET shown in FIGS. 15 and 16 has a structure in which the gate surrounds the channel in a triple layer, and in FIG. 15, the gate surrounds the channel in a triple layer only in the region where the channel under the gate is formed without forming the side gate. A saddle FinFET of the form is shown, and FIG. 16 shows a saddle FinFET of the form where the gate region near the channel maintains a triple gate and reduces regions overlapping the source and drain regions of the side gate region.

The structure of the remaining saddle FinFET except the insulator 10 is according to the prior art, so a detailed description thereof will be omitted.

1, 11: silicon substrate
2, 12: Wall-type silicone body
3: 1st insulating film
4: nitride film
5: 2nd insulating film (field insulating film or insulating insulating film)
6: Polysilicon
7, 17: gate insulating film
8, 18: gate electrode
9, 19: source / drain area
10: insulator
Xj: source / drain junction

Claims (8)

A gate 8 in which at least a portion of the silicon body 2 having a drain region and a source region is formed, and at least a part of the silicon body 2 is interposed between the drain region and the source region with a gate insulating film 7 interposed therebetween. As for a transistor having a non-planar channel comprising a,
The drain region and the source region are portions of the silicon body 2 doped with a doping material,
Insulator 10 is buried in the silicon body 2,
With respect to the height direction (Y-axis direction) of the silicon body 2, the upper surface of the insulator 10 is at a higher position than the lower surface of the gate insulating film 7 embedded in the silicon body 2 and at the same time , Located in the drain region or the source region,
The drain region is formed by a HDD (Highly Dopped Drain) process,
The depth (D) in which the gate insulating film 7 is buried in the silicon body 2 is the distance y in the height direction of the silicon body 2 between the upper surface of the insulator 10 and the lower surface of the gate insulating film 7. The α value divided by) is 0.6 or more and 0.9 or less.
delete delete The silicon body (2) of claim 1, wherein the shortest distance (x) between the insulator (10) and the gate insulating film (7) in the horizontal direction (X-axis direction) is buried. Transistor having a non-planar channel, characterized in that the β value divided by the shortest distance (L) in the horizontal direction (X-axis direction) between the side cross-section and the gate insulating film 7 is 0.4 or less.
The transistor according to claim 1 or 4, wherein the insulator is a dielectric.
The transistor according to claim 5, wherein the dielectric is made of at least one material selected from SiO ₂ , Si ₃ N ₄ , and HfO ₂ and ZrO ₂ .
The transistor according to claim 1 or 4, wherein the insulator is formed by a vacuum layer.
The transistor according to claim 1 or 4, wherein the insulator is formed in a hexahedral shape.

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