KR102059429B1 - Integrated circuit - Google Patents

Abstract

A circuit for measuring the temperature of an integrated circuit, the circuit comprising: a clock delay unit that receives a source clock, varies a nonlinear delay amount according to a change in temperature, and outputs the delay clock; A oscillation clock oscillating, having a oscillation delay in which oscillation delays fluctuate in a direction for compensating for nonlinearity of the clock delay portion in response to a change in temperature, and a temperature detection portion detecting a change in temperature according to a phase difference between the source clock and the oscillation clock It provides an integrated circuit having a.

Description

Integrated Circuits {INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques and, more particularly, to circuitry for measuring the temperature of integrated circuits.

Temperature sensing circuits, which sense temperature changes within integrated circuits, are now one of the most important circuits. Temperature sensing circuits play a very important role in circuits that protect circuits at high temperatures, circuits whose operating characteristics change at constant temperatures, and circuits such as thermometers. The operating speed, internal resistance, and the like of the integrated circuit change with temperature. In particular, as the degree of integration of integrated circuits increases, it is increasingly important to detect accurate temperature changes because the change in temperature has a greater effect on the process of integrated circuits.

1 is a temperature sensor of an integrated circuit corresponding to the prior art.

In the case of an on-chip thermal sensor of an integrated circuit according to the prior art, a band-gap reference method using a band-gap characteristic of a bipolar transistor has been used. Was the best performance and the most common method.

Specifically, referring to FIG. 1, different currents are applied to two bipolar transistors Q1 and Q2 that are diode-connected in the same diode form, wherein P is a ratio of the magnitudes of currents applied to Q1 and Q2. ), You can get VBE, which decreases in proportion to temperature, and ΔVBE, which increases in proportion to temperature. With this characteristic, the bipolar transistors Q1 and Q2 can generate a voltage proportional to temperature. Finally, by applying the VPTAT amplified ΔVBE and the reference voltage (VREF) to the analog-to-digital converter (ADC), it is possible to obtain a digital value (Dout) corresponding to the temperature, at this time, the value output from the digital converter (ADC) Since (DOUT) is linear with temperature, it can show high accuracy.

However, recently, in a situation where a plurality of temperature sensors are to be mounted on a semiconductor chip, a problem arises due to the large area of the temperature sensor using a bipolar transistor. In addition, most semiconductor processes are optimized for CMOS, which makes bipolar transistors (BJTs) in the same process, making them larger and more burdensome to use.

In addition, when the size of the transistor becomes smaller and accordingly, the driving voltage is also lowered, when the temperature is measured by using the voltage change, the voltage headroom that the voltage can change becomes small. There is a limit to the temperature fluctuation range, and also becomes vulnerable to noise. Because high-performance analog-to-digital converters (High-Performance ADCs) are required to increase the measurable temperature fluctuations, this also leads to an increase in area and design time.

Embodiments of the present invention provide an integrated circuit including a temperature measuring device capable of measuring temperature information with a linear characteristic while minimizing an occupying area.

An integrated circuit according to an exemplary embodiment of the present invention includes a clock delay unit which receives a source clock and changes it as a nonlinear delay amount according to a change in temperature and outputs it as a delay clock; A clock oscillation unit oscillating an oscillation clock having the same frequency in response to the delay clock, the oscillation delay of which fluctuates in a direction for compensating for nonlinearity of the clock delay unit according to a change in temperature; And a temperature detector configured to detect a change in temperature according to a phase difference between the source clock and the oscillation clock.

According to another embodiment of the present invention, an integrated circuit may include: a first clock delay unit receiving a source clock and constantly changing a constant delay amount as a first delay clock regardless of a change in temperature; A second clock delay unit which receives the source clock and changes it as a non-linear delay amount according to a change in temperature and outputs it as a second delay clock; A clock oscillator configured to oscillate an oscillation clock having the same frequency in response to the second delay clock, the oscillation delay of which fluctuates in a direction compensating for nonlinearity of the second clock delay unit in response to a change in temperature; And a temperature detector configured to detect a temperature change according to a phase difference between the first delay clock and the oscillation clock.

In accordance with still another aspect of the present invention, an integrated circuit includes a first clock delay unit receiving a source clock and outputting a constant delay amount as a first delay clock regardless of temperature fluctuations; A frequency divider for distributing a frequency of the source clock at a set ratio to generate a divided clock; A second clock delay unit which receives the distribution clock and changes the non-linear delay amount according to the temperature change and outputs the second delay clock as a second delay clock; A clock oscillator configured to oscillate an oscillation clock having the same frequency in response to the second delay clock, the oscillation delay of which fluctuates in a direction compensating for nonlinearity of the second clock delay unit in response to a change in temperature; And a temperature variation code generator configured to generate a temperature variation code by counting a phase variation width of the oscillation clock based on the first delay clock based on a change in temperature.

By measuring the temperature using a time-delay method in which a linear characteristic can be applied to a change in temperature, there is an effect of increasing the temperature measurement accuracy while minimizing the occupied area.

1 is a temperature sensor of an integrated circuit corresponding to the prior art.
2A to 2D are diagrams for explaining a time-delay type temperature measuring circuit.
3 is a view for explaining a temperature measuring circuit according to a first embodiment of the present invention.
4 is a view for explaining a temperature measuring circuit according to a second embodiment of the present invention.
5 is a diagram for explaining a temperature measuring circuit according to a third embodiment of the present invention.
6 is a timing diagram for explaining the operation of the temperature measuring circuit according to the third embodiment of the present invention disclosed in FIG.
FIG. 7 is a view for explaining a process of generating a linear operating characteristic according to temperature variation in the temperature measuring circuit according to the first to third embodiments of the present invention disclosed in FIGS. 3 to 5.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

2A to 2D are diagrams for explaining a time-delay type temperature measuring circuit.

First, the temperature measuring circuit shown in FIGS. 2A to 2D uses a phenomenon in which a delay of an inverter varies with temperature based on a CMOS. That is, the circuits that can measure the amount of delay according to the change in temperature based on time.

When the time-delay method is used for temperature measurement, there is no limit on the range that varies with temperature, unlike voltage, which is a suitable time-to-digital converter. , TDC), you can increase the range of measurable temperature fluctuations. It can also be implemented in a much smaller area than using a bipolar transistor (BJT), and the delay locked loop (DLL) or phase locked loop (PLL) already exists inside the integrated circuit when generating a reference clock for operation. ) Can be shared to reduce the footprint.

FIG. 2A is a temperature measurement circuit using a cyclic time-to-digital converter (Cyclic TDC) method, and a signal TDDL and a temperature fluctuation passing through a Temperature Dependent Delay Line whose delay is changed according to temperature fluctuation. Variation of the delay amount of the signal (TIDL) passing through the Independent Delay Line, which is not changed according to the delay, is converted into a final digital value by using a cyclic TDC and a counter. Done.

FIG. 2B is a temperature measuring circuit using a ring oscillator method and an output from a current-controlled ring oscillator controlled by a bias current generator-linear to temperature according to a temperature change By using the oscillation clock (OSC2) output from the current-controlled ring oscillator (Bias current generator-Independent of temperature) is controlled so that the oscillation clock (OSC1) does not fluctuate according to the temperature fluctuation It counts and converts them into digital values.

FIG. 2C is a temperature measurement circuit using a dual delay locked loop (Dual-DLL) method, and includes a delay dependent loop and a delay locked loop DLL in which a delay amount fluctuates with temperature variation. The phase difference of the delay line (Temperature Independent Delay Line) does not change according to the change of the circuit through the finite state machine (FSM) to convert the temperature value.

2A to 2C described above, the temperature measuring circuits described above commonly use a delay line (Temperature Dependent Delay Line) using an inverter whose delay amount varies according to temperature variation. By the way, the delay line (Temperature Dependent Delay Line) in which the delay amount fluctuates according to the temperature change using the inverter has a characteristic that the variation of the delay amount due to the temperature change is nonlinear due to the characteristics of the inverter itself. In other words, the delay amount does not change at a constant rate with respect to the change in temperature. As such, when the nonlinear characteristic of the temperature fluctuations is obtained, there is a problem that it is difficult to find the correct value even when the digital value is converted.

In addition, as many inverters as the number of inverters used in a delay line (Temperature Dependent Delay Line) using an inverter whose delay amount varies with temperature fluctuation should generally be used. That is, a large number of inverters are required in order to achieve a measurable level in which the variation in the delay amount varies with the temperature variation. However, an increase in the number of inverters means that power supply noise may occur, and an error occurs in the temperature measurement result due to the noise.

In order to solve this problem, as shown in FIG. 2D, a temperature measuring circuit having a linear characteristic with respect to temperature fluctuation is proposed using a successive Approximation Register (SAR) control logic. Specifically, by controlling the difference comparison register (SAR) by compensating for the delay amount (Adjustable Reference Delay Line (ARDL)) to the delay line (Temperature Dependent Delay Line) that the delay amount is non-linearly changed according to the temperature change Finally, the delay amount varies linearly with temperature fluctuations.

By using the control of the sequential comparison type register SAR as described in FIG. 2D, it is possible to prevent the delay amount from non-linearly fluctuating with the change in temperature. However, there are still many problems of power supply noise coming from the delay lines due to the large number of inverters, and since the area occupied by the SAR is relatively large, the bipolar transistor ( The advantage of not using BJT) is reduced.

In summary, since the temperature measuring circuit using the bipolar transistor (BJT) shown in the prior art of FIG. 1 occupies a very large area, in order to solve the area problem, as shown in FIGS. Although a temperature measurement circuit using a time-delay has been proposed through a delay-dependent delay line including an inverter in which the delay amount fluctuates, the characteristic that the variation in the delay amount is nonlinear with respect to temperature fluctuations is proposed. In addition, there is a problem that accuracy is lowered compared to a temperature measuring circuit using a bipolar transistor (BJT) due to power supply noise coming from a long delay line including a plurality of inverters. Therefore, as shown in FIG. 2D, a method of using the SAR control logic to have a linear variation in the delay amount according to the temperature change has been proposed. However, due to the SAR control logic, The problem is that the area is greatly increased, and the problem due to power supply noise has not been solved.

<First Embodiment>

3 is a view for explaining a temperature measuring circuit according to a first embodiment of the present invention.

Referring to FIG. 3, the temperature measuring circuit according to the first embodiment of the present invention includes a clock delay unit 300, a clock oscillator 320, and a temperature detector 340. Here, the clock oscillator 320 includes a ring oscillator 322 and a compensation adjuster 324.

Specifically, the clock delay unit 300 receives the source clock REF_CLK, changes the non-linear delay amount according to the change in temperature, and outputs the delayed clock DLY_CLK. That is, the clock delay unit 300 receives the source clock REF_CLK and delays it by a predetermined delay amount and outputs the delayed clock DLY_CLK. However, as the temperature fluctuations occur, the set delay amount fluctuates in a state having nonlinear characteristics.

In this case, the delay amount of the clock delay unit 300 having a non-linear characteristic according to the change in temperature means that the width of the delay amount of the clock delay unit 300 changes correspondingly when the temperature fluctuates in a relatively low section. When the temperature fluctuates in a relatively high section, it means that the widths of the delays of the clock delay unit 300 vary accordingly. For example, in the 0 degree to 20 degree range belonging to the section where the temperature is relatively low, the delay amount of the clock delay unit 300 fluctuates by 0.2 percent every time the temperature changes by 1 degree, but 21 degrees belonging to the section where the temperature is relatively high. In the 40 to 40 degrees section, the delay amount of the clock delay unit 300 varies by 0.15 percent every time the temperature changes by 1 degree.

In addition, the clock oscillator 320 oscillates the oscillation clock OSCLK having the same frequency in response to the delay clock DLY_CLK, but compensates for the non-linearity of the clock delay unit 300 according to a change in temperature. The oscillation delay amount fluctuates. In this case, the variation in the oscillation delay amount in the clock oscillator 320 means that the oscillation frequency of the oscillation clock OSCLK is changed.

Specifically, the ring oscillator 322 of the components of the clock oscillator 320 oscillates the oscillation clock (OSCLK) having a frequency difference within the set range and the frequency of the delay clock (DLY_CLK) in the first enable mode, In the second enable mode, the amount of oscillation delay varies in a direction in which the frequency of the oscillation clock OSCLK coincides with the frequency of the delay clock DLY_CLK.

In this case, the reason why the ring oscillator 322 operates differently in the first enable mode and the second enable mode is that the frequency of the oscillation clock OSCLK is determined based on the frequency of the delayed clock DLY_CLK in the clock oscillator 320. This is because injection locking is used as a control method.

Here, injection locking is a method of injecting a master oscillation clock output from a master oscillator into a slave oscillator, and a slave oscillation clock output from a slave oscillator is output from a master oscillator. Are synchronized to the master oscillation clock. For reference, in FIG. 3, since the configuration of the master oscillator is not included separately, the master oscillation clock may be a delay clock DLY_CLK, the slave oscillator may be a clock oscillator 320, and the slave oscillation clock may be an oscillation clock OSCLK. .

As such, the clock oscillator 320 using the injection locking method can reduce power consumption and is a very efficient circuit in terms of improving operating performance on jitter. However, in order for injection locking to occur, the frequency of the injected master oscillation clock, that is, the delay clock DLY_CLK and the slave oscillation clock, that is, the free running frequency of the oscillation clock OSCLK, must be included in the set frequency range. do. In this case, the free running frequency of the oscillation clock OSCLK refers to the frequency of the oscillation clock OSCLK when no control other than an enable operation is applied to the ring oscillator 322.

Accordingly, the ring oscillator 322 has a frequency range in which the frequency of the oscillation clock OSCLK is set in comparison with the frequency of the delay clock DLY_CLK in the first enable mode, which means when no control except for the enable operation is applied. Operate to belong to. For reference, since the frequency of the delay clock DLY_CLK is known in advance at the time of design, it is not difficult to set the free running frequency of the oscillation clock OSCLK. However, in view of the fact that the frequency of the delay clock DLY_CLK may vary, a method of using an additional control signal to adjust the free running frequency of the oscillation clock OSCLK may be required. That is, although not shown in the ring oscillator 322 disclosed in FIG. 3, an additional control signal may be applied to the ring oscillator 322 to adjust the free running frequency of the oscillation clock OSCLK. .

In addition, the second enable mode of the ring oscillator 322 is an enable operation to be distinguished from the above-described first enable mode, and is controlled by the compensation adjusting unit 324 during the injection locking operation. This refers to an operation in which the frequency of the oscillation clock OSCLK oscillated in the oscillator 322 is changed. In this case, since the injection locking operation adjusts the frequency of the oscillation clock OSCLK based on the frequency of the delay clock DLY_CLK, in the second enable mode, the ring oscillator 322 oscillates at the frequency of the delay clock DLY_CLK. The frequency of the oscillation clock OSCLK is adjusted in a direction to match the frequency of the OSCLK.

Although the control signal is not directly shown in FIG. 3, a control operation for disabling the operation of the ring oscillator 322 is also possible. That is, a disable control operation without oscillating the oscillation clock OSCLK may be performed regardless of the operation of the delay clock DLY_CLK and the compensation controller 324.

The compensator 324 among the components of the clock oscillator 320 of the clock oscillator 320 of the ring oscillator 322 responds to variations in the delayed clock DLY_CLK, the compensation control voltage INJECT_STR, and the temperature in the second enable mode. Adjust the amount of operating current. At this time, as described above, the compensation adjusting unit 324 changes the frequency of the oscillation clock OSCLK in the second enable mode of the ring oscillator 322, and the method includes the amount of operating current of the ring oscillator 322. It can be a way to control.

Specifically, when the elements for adjusting the operating current amount of the ring oscillator 322 are separated one by one from the compensation controller 324, the frequency of the delay clock DLY_CLK and the voltage level of the compensation control voltage INJECT_STR are fixed. However, there may be temperature fluctuations as a variable factor. For reference, the fixed element means an element that can no longer be changed after the operation of the clock oscillator 320 including the compensation adjusting unit 324 is started, and the variable element is the opposite of the fixed element. As a meaning, it means an element that may be changed after the operation of the clock oscillator 320 starts. That is, the value of the frequency of the delay clock DLY_CLK and the voltage level of the compensation control voltage INJECT_STR are not changed in the operation section of the clock oscillator 320 after the value is set before the operation. However, the temperature fluctuates in an unpredictable state in which the fluctuation of the clock oscillator 320 operates.

First, the operation of adjusting the amount of operating current of the ring oscillator 322 in response to the frequency of the delay clock DLY_CLK in the compensation controller 324, for example, the frequency of the delay clock DLY_CLK oscillates in the ring oscillator 322. When the oscillation clock OSCLK is higher than the frequency of the oscillation clock OSCLK, the oscillation delay amount of the ring oscillator 322 is reduced by reducing the amount of operating current of the ring oscillator 322, and thus the frequency of the oscillation clock OSCLK is increased, thereby delaying the clock. It is set to the frequency of (DLY_CLK). However, when the frequency of the delay clock DLY_CLK is lower than the frequency of the oscillation clock OSCLK oscillated by the ring oscillator 322, the oscillation delay amount of the ring oscillator 322 is increased by increasing the amount of operating current of the ring oscillator 322. As a result, the frequency of the oscillation clock OSCLK is slowed down to match the frequency of the delay clock DLY_CLK.

In addition, the ring oscillator of the compensation control unit 324 does not directly change the magnitude of the operation current amount of the compensation control unit 324 according to the voltage level of the compensation control voltage INJECT_STR, but according to the voltage level of the compensation control voltage INJECT_STR. The operating current amount adjustable width of 322 is determined. That is, in response to a change in the voltage level of the compensation control voltage INJECT_STR, a maximum value that can increase and a minimum value that can decrease the amount of operating current of the ring oscillator 322 in the compensation adjusting unit 324 may vary.

For example, as the voltage level of the compensation control voltage INJECT_STR is higher, the range of the maximum value that can increase and the minimum value that can decrease the amount of operating current of the ring oscillator 322 in the compensation control unit 324 can be widened. Of course, as the range of the maximum value that can increase and the minimum value that can decrease the operating current of the ring oscillator 322 in the compensation adjusting unit 324 is widened, the ring oscillator 322 is controlled by the control of the compensation adjusting unit 324. Since the amount of the operating current of Rc is relatively more fluctuated, the frequency locking accuracy between the frequency of the delayed clock DLY_CLK applied to the clock oscillator 320 and the oscillation clock OSCLK output from the clock oscillator 320 will decrease.

On the contrary, as the voltage level of the compensation control voltage INJECT_STR is lower, the range of the maximum value that can increase and the minimum value that can decrease the operating current amount of the ring oscillator 322 in the compensation control unit 324 can be narrowed. . Of course, as the range of the maximum value that can increase and decrease the minimum value that can decrease the operating current amount of the ring oscillator 322 in the compensation adjusting unit 324 becomes narrower, the ring oscillator 322 under the control of the compensation adjusting unit 324. Since the amount of the operating current of Rc varies relatively little by little, the frequency locking accuracy between the frequency of the delayed clock DLY_CLK applied to the clock oscillator 320 and the oscillation clock OSCLK output from the clock oscillator 320 will increase.

In order to explain an operation of adjusting the amount of operating current of the ring oscillator 322 in response to a temperature change in the compensation controller 324, the specific configuration of the compensation controller 324 will be described. A second NMOS transistor N2 is included. That is, the compensation adjusting unit 324 may include the first NMOS transistor N1 controlled on / off in response to the delay clock DLY_CLK between the ring oscillator 322 and the operation node MND, and the compensation control voltage INJECT_STR. The second NMOS transistor N2 adjusts the amount of current flowing between the operation node MND and the ground voltage VSS terminal in accordance with the level of VIII.

As such, the compensation adjusting unit 324 includes NMOS transistors N1 and N2 therein, and each of the NMOS transistors N1 and N2 is controlled by the delay clock DLY_CLK and the compensation control voltage INJECT_STR to ring. It can be seen that the operation of the compensation adjusting unit 324 described above is made according to how much the current of the oscillator 322 sinks. That is, the increase in the amount of current flowing between the drain and the source of the NMOS transistors N1 and N2 by the control of the delay clock DLY_CLK and the compensation control voltage INJECT_STR increases the ground voltage VSS at the ring oscillator 322. This means that the amount of current sinking into is increased, which means that the amount of operating current of the ring oscillator 322 is reduced. On the contrary, the decrease in the amount of current flowing between the drain and the source of the NMOS transistors N1 and N2 by the control by the delay clock DLY_CLK and the compensation control voltage INJECT_STR means that the ground voltage VSS terminal of the ring oscillator 322 is reduced. This means that the magnitude of the sinked current decreases, which means that the amount of operating current in the ring oscillator 322 increases.

On the other hand, the NMOS transistors N1 and N2, which are components of the compensation control unit 324, generally have a non-linear variation in resistance value with respect to temperature variations, regardless of the level of the voltage applied to the gate. The magnitude of the current flowing between them varies nonlinearly. That is, as the temperature increases, the resistance values of the NMOS transistors N1 and N2 increase nonlinearly regardless of the control by the delay clock DLY_CLK and the compensation control voltage INJECT_STR. The magnitude of the current flowing between the drain and the source of N2) decreases nonlinearly. On the contrary, as the temperature decreases, the resistance values of the NMOS transistors N1 and N2 decrease nonlinearly regardless of the control by the delay clock DLY_CLK and the compensation control voltage INJECT_STR, and thus the NMOS transistors N1, The magnitude of the current flowing between the drain and the source of N2) increases nonlinearly.

As described above, since the compensation adjusting unit 324 includes the NMOS transistors N1 and N2, the ring oscillator () may be changed according to a change in temperature regardless of the control by the delay clock DLY_CLK and the compensation control voltage INJECT_STR. The amount of current sinking in 322 is varied non-linearly, and thus the amount of operating current of the ring oscillator 322 is non-linearly varied.

In detail, the variation in the amount of current of the compensation controller 324 is relatively reduced in a section where the temperature is relatively low, and relatively large in the section where the temperature is high. For example, if the current amount of the compensation control unit 324 decreases by 0.1 percent every time the temperature is increased by 1 degree between 0 degrees and 20 degrees, which is a relatively low temperature section, the temperature is increased by 40 degrees at 21 degrees which is a relatively high temperature section. Between degrees, each time the temperature increases by 1 degree, the current amount of the compensation adjusting unit 324 decreases by 0.15 percent.

Accordingly, the variation of the operating current amount of the ring oscillator 322 increases relatively in a section where the temperature is relatively low, and increases relatively in a section where the temperature is high. For example, if the operating current of the ring oscillator 322 increases by 0.1 percent every time the temperature is increased by 1 degree between 0 degrees and 20 degrees, which is a relatively low temperature section, the operating temperature of the ring oscillator 322 increases by 0.1 percent. Between the figures, each time the temperature increases by 1 degree, the operating current amount of the ring oscillator 322 increases by 0.15 percent.

As described above, it can be seen that the amount of operating current of the ring oscillator 322 not only increases nonlinearly with increasing temperature, but also increases as the temperature increases. The oscillation delay amount also increases non-linearly with temperature fluctuations, and the non-linear increase direction increases as the temperature increases.

That is, the ring oscillator 322 increases in a nonlinear manner as the temperature increases, but compensates for the non-linear delay increase characteristic of the clock delay unit 300 having a characteristic of increasing slightly as the temperature increases. It can be seen that the oscillation delay amount of is determined.

Referring to FIG. 7, the operation of the temperature measuring circuit according to the first embodiment of the present invention disclosed in FIG. 3 is summarized as follows.

First, the delay of the clock delay unit 300 (TDDL) increases nonlinearly with increasing temperature, but increases at a relatively high rate in a section where the temperature is relatively low, and relatively low in a section where the temperature is relatively high. Increases in proportion.

In addition, the oscillation delay amount of the clock oscillator 320 (ILO) increases nonlinearly with increasing temperature, but increases at a relatively low rate in a section where the temperature is relatively low, and relatively high in a section where the temperature is relatively high. Increases in proportion.

Therefore, when the delay amount of the clock delay unit 300 and the delay amount of the clock oscillator 320 are combined (TDDL + ILO) through an injection locking operation, a delay applied to the finally outputted clock OSCLK. The amount becomes a state having a linear characteristic according to the change of temperature.

The temperature detector 340 detects a change in temperature in accordance with the phase difference between the source clock REF_CLK and the oscillation clock OSCLK.

That is, the source clock REF_CLK is a clock that has a constant phase at all times regardless of temperature fluctuations, and the oscillation clock OSCLK is a clock having a linear characteristic with respect to temperature fluctuations. It is easy to see how much variation has occurred.

For example, if the phase of the oscillation clock OSCLK is slightly delayed in comparison with the phase of the source clock REF_CLK, the temperature detector 340 may increase the temperature relatively little, and compare the phase of the oscillation clock with the phase of the source clock REF_CLK. If the phase of (OSCLK) is relatively delayed, it can be determined that the temperature has increased relatively.

In addition, if the temperature detector 340 knows the direction in which the phase difference between the source clock REF_CLK and the oscillation clock OSCLK occurs, the temperature increase / decrease may be determined.

Second Embodiment

4 is a view for explaining a temperature measuring circuit according to a second embodiment of the present invention.

Referring to FIG. 4, the temperature measuring circuit according to the second embodiment of the present invention includes a first clock delay unit 460, a second clock delay unit 400, a clock oscillator 420, and a temperature detector 440. ). Here, the clock oscillator 420 includes a ring oscillator 422 and a compensation adjuster 424. In addition, the first clock delay unit 460 includes a delay line 462 and a delay lock operation unit 464.

In detail, the first clock delay unit 460 receives the source clock REF_CLK and always changes it with a constant delay regardless of the temperature change, and outputs it as the first delay clock DLL_CLK. That is, the first clock delay unit 460 operates so that the source clock REF_CLK and the first delay clock DLL_CLK always have a constant delay amount regardless of temperature fluctuations.

In addition, the delay line 462 of the components of the first clock delay unit 460 adjusts the delay amount in response to the change in temperature and the delay control signal DLY_CON, and delays the source clock REF_CLK to delay the first clock. Output as a delay clock DLL_CLK.

Also, among the components of the first clock delay unit 460, the delay lock operation unit 464 compares the phases of the source clock REF_CLK and the first delay clock DLL_CLK for the delay lock operation. Accordingly, the value of the delay control signal DLY_CON is adjusted.

In this case, the delay amount of the delay line 462 may be adjusted according to the change in temperature, and at the same time, it may be adjusted according to the delay control signal DLY_CON. For example, when the delay amount of the delay line 462 increases or decreases as the initial set amount according to the increase in temperature, the delay lock operation unit 464 detects the delay amount and the value of the delay control signal DLY_CON is changed. The delay amount of the delay line 462 is returned to the initial set amount. Therefore, the source clock REF_CLK and the first delay clock DLL_CLK can always maintain a constant phase difference, which means that the delay amount of the delay line 462 is always kept constant.

The second clock delay unit 400 receives the source clock REF_CLK, changes the non-linear delay amount according to the change in temperature, and outputs the second clock delay as the second delay clock DLY_CLK. That is, the second clock delay unit 400 receives the source clock REF_CLK and delays it by a predetermined delay amount and outputs it as the second delay clock DLY_CLK. However, as the temperature fluctuations occur, the set delay amount fluctuates in a state having nonlinear characteristics.

In this case, the delay amount of the second clock delay unit 400 having a non-linear characteristic according to the change in temperature means that the delay amount of the second clock delay unit 400 corresponding to the change in the temperature range is relatively low. When the fluctuating width and the temperature fluctuate in a relatively high period, it means that the width in which the delay amount of the second clock delay unit 400 fluctuates correspondingly is different. For example, in the 0 degrees to 20 degrees section where the temperature is relatively low, the delay amount of the second clock delay unit 400 fluctuates by 0.2 percent every time the temperature fluctuates by 1 degree, but it belongs to the section where the temperature is relatively high. In the period of 21 degrees to 40 degrees, it means a case in which the delay amount of the second clock delay unit 400 fluctuates by 0.15 percent every time the temperature fluctuates by 1 degree.

In addition, the clock oscillator 420 oscillates the oscillation clock OSCLK having the same frequency in response to the second delay clock DLY_CLK, but the non-linearity of the second clock delay unit 400 is changed in response to a change in temperature. The oscillation delay amount fluctuates in a direction to compensate for the loss. In this case, the variation in the oscillation delay amount in the clock oscillator 420 means that the oscillation frequency of the oscillation clock OSCLK is changed.

In detail, among the components of the clock oscillator 420, the ring oscillator 422 oscillates the oscillation clock OSCLK having a frequency difference within a set range from a frequency of the second delayed clock DLY_CLK in the first enable mode. In the second enable mode, the amount of oscillation delay varies in a direction in which the frequency of the oscillation clock OSCLK matches the frequency of the second delay clock DLY_CLK.

In this case, the reason why the ring oscillator 422 operates differently in the first enable mode and the second enable mode is that the clock oscillator 420 of the oscillation clock OSCLK is based on the frequency of the second delayed clock DLY_CLK. This is because injection locking is used to adjust the frequency.

Here, injection locking is a method of injecting a master oscillation clock output from a master oscillator into a slave oscillator, and a slave oscillation clock output from a slave oscillator is output from a master oscillator. Are synchronized to the master oscillation clock. For reference, in FIG. 4, since the configuration of the master oscillator is not included, the master oscillation clock is the second delay clock DLY_CLK, the slave oscillator is the clock oscillator 420, and the slave oscillation clock is the oscillation clock OSCLK. Can be.

As such, the clock oscillator 420 using the injection locking method can reduce power consumption and is a very efficient circuit in terms of improved operation performance for jitter. However, in order for injection locking to occur, the frequency of the injected master oscillation clock, that is, the second delayed clock DLY_CLK and the slave oscillation clock, that is, the free running frequency of the oscillation clock OSCLK, are included in the set frequency range. Should be. In this case, the free running frequency of the oscillation clock OSCLK refers to the frequency of the oscillation clock OSCLK when no control other than an enable operation is applied to the ring oscillator 422.

Accordingly, the ring oscillator 422 sets the frequency of the oscillation clock OSCLK in comparison with the frequency of the second delayed clock DLY_CLK in the first enable mode, which means when no control is applied except for the enable operation. Operate to fall within the frequency range. For reference, since the frequency of the second delayed clock DLY_CLK is known in advance at the time of design, it is not difficult to set a free running frequency of the oscillation clock OSCLK. However, in view of the fact that the frequency of the second delayed clock DLY_CLK may vary, a method of using an additional control signal may be needed to adjust the free running frequency of the oscillation clock OSCLK. That is, although not shown in the ring oscillator 422 disclosed in FIG. 4, an additional control signal may be applied to the ring oscillator 422 to adjust the free running frequency of the oscillation clock OSCLK. .

In addition, the second enable mode of the ring oscillator 422 is an enable operation to be distinguished from the above-described first enable mode, and is controlled by the compensation adjusting unit 424 during the injection locking operation. Means an operation in which the frequency of the oscillation clock OSCLK oscillated in the oscillator 422 is changed. In this case, since the injection locking operation adjusts the frequency of the oscillation clock OSCLK based on the frequency of the second delay clock DLY_CLK, the ring oscillator 422 in the second enable mode performs the second delay clock DLY_CLK. The frequency of the oscillation clock OSCLK is adjusted to match the frequency of the oscillation clock OSCLK.

Although the control signal is not directly shown in FIG. 4, a control operation for disabling the operation of the ring oscillator 422 is also possible. That is, a disable control operation without oscillating the oscillation clock OSCLK is possible regardless of the operation of the input delay compensation unit 424 and the second delayed clock DLY_CLK.

The compensator 424 of the clock oscillator 420 may perform the ring oscillator 422 in response to variations in the second delayed clock DLY_CLK, the compensation control voltage INJECT_STR, and the temperature in the second enable mode. Adjust the amount of operating current. At this time, as described above, the compensation adjusting unit 424 changes the frequency of the oscillation clock OSCLK in the second enable mode of the ring oscillator 422, and the method includes the amount of operating current of the ring oscillator 422. It can be a way to control.

Specifically, when the elements for adjusting the operating current amount of the ring oscillator 422 are separated one by one from the compensation controller 424, the frequency of the second delayed clock DLY_CLK and the voltage level of the compensation control voltage INJECT_STR are fixed elements. There may be a change in temperature as a variable factor. For reference, the fixed element means an element that can no longer be changed after the operation of the clock oscillator 420 including the compensation control unit 424 is started, and the variable element is the opposite of the fixed element. As a meaning, it means an element that may be changed after the operation of the clock oscillator 420 starts. That is, when the value of the frequency of the second delayed clock DLY_CLK and the voltage level of the compensation control voltage INJECT_STR are set before the operation, the value does not change in the operation section of the clock oscillator 420 thereafter. However, the temperature fluctuates in an unpredictable manner in how the clock oscillator 420 fluctuates in the operation section.

First, an operation of adjusting the amount of operating current of the ring oscillator 422 corresponding to the frequency of the second delayed clock DLY_CLK by the compensation controller 424 may be described. For example, the frequency of the second delayed clock DLY_CLK is determined by the ring oscillator ( When the oscillation clock (OSCLK) oscillation is higher than the frequency of the oscillation clock (OSCLK), the oscillation delay of the ring oscillator 422 is reduced by reducing the amount of operating current of the ring oscillator 422 and thus the frequency of the oscillation clock (OSCLK) is faster. In this case, the frequency of the second delay clock DLY_CLK is adjusted. However, when the frequency of the second delay clock DLY_CLK is lower than the frequency of the oscillation clock OSCLK oscillated by the ring oscillator 422, the oscillation delay amount of the ring oscillator 422 is increased by increasing the amount of operating current of the ring oscillator 422. In this case, the frequency of the oscillation clock OSCLK will be slowed down to match the frequency of the second delayed clock DLY_CLK.

In addition, the magnitude of the operating current of the compensation adjusting unit 424 does not directly change according to the voltage level of the compensation control voltage INJECT_STR, but the ring oscillator in the compensation adjusting unit 424 according to the voltage level of the compensation control voltage INJECT_STR. The operating current amount adjustable width of 422 is determined. That is, in response to a change in the voltage level of the compensation control voltage INJECT_STR, a maximum value that can increase and a minimum value that can decrease the amount of operating current of the ring oscillator 422 may be changed by the compensation adjusting unit 424.

For example, as the voltage level of the compensation control voltage INJECT_STR is higher, the range of the maximum value that can increase and the minimum value that can decrease the operating current amount of the ring oscillator 422 in the compensation control unit 424 may be widened. Of course, as the range of the maximum value that can increase and the minimum value that can decrease the operating current of the ring oscillator 422 in the compensation adjusting unit 424 is widened, the ring oscillator 422 is controlled by the control of the compensation adjusting unit 424. Since the amount of operating current of V is fluctuated relatively more, the frequency locking accuracy between the frequency of the second delayed clock DLY_CLK applied to the clock oscillator 420 and the oscillation clock OSCLK output from the clock oscillator 420 will decrease. will be.

On the contrary, as the voltage level of the compensation control voltage INJECT_STR is lower, the range of the maximum value that can increase and the minimum value that can decrease the operation current amount of the ring oscillator 422 in the compensation control unit 424 can be narrowed. . Of course, as the range of the maximum value that can increase and the minimum value that can decrease the operating current of the ring oscillator 422 in the compensation adjusting unit 424 is narrowed, the ring oscillator 422 is controlled under the control of the compensation adjusting unit 424. Since the amount of the operating current of Rk is relatively little changed, the frequency locking accuracy between the frequency of the second delayed clock DLY_CLK applied to the clock oscillator 420 and the oscillation clock OSCLK output from the clock oscillator 420 will be increased.

In order to explain an operation of adjusting the amount of operating current of the ring oscillator 422 in response to a temperature change in the compensation controller 424, a specific configuration of the compensation controller 424 will be described. A second NMOS transistor N2 is included. That is, the compensation controller 424 may include the first NMOS transistor N1 and the compensation control voltage controlled on / off in response to the second delay clock DLY_CLK between the ring oscillator 422 and the operation node MND. The second NMOS transistor N2 adjusts the amount of current flowing between the operation node MND and the ground voltage VSS terminal according to the level of INJECT_STR.

As such, the compensation adjusting unit 424 includes NMOS transistors N1 and N2 therein, and each of the NMOS transistors N1 and N2 is controlled by the second delayed clock DLY_CLK and the compensation control voltage INJECT_STR. Therefore, it can be seen that the operation of the compensation adjusting unit 424 described above is performed according to how much current is sinked in the ring oscillator 422. That is, the increase in the amount of current flowing between the drain and the source of the NMOS transistors N1 and N2 by the control by the second delayed clock DLY_CLK and the compensation control voltage INJECT_STR indicates that the ground voltage VSS in the ring oscillator 422 is increased. This means that the magnitude of the current sinking increases, which means that the amount of operating current of the ring oscillator 422 decreases. On the contrary, the decrease in the amount of current flowing between the drain and the source of the NMOS transistors N1 and N2 by the control by the second delayed clock DLY_CLK and the compensation control voltage INJECT_STR indicates that the ground voltage VSS in the ring oscillator 422 is reduced. This means that the amount of current sinking in step 3 decreases, which means that the amount of operating current of the ring oscillator 422 increases.

On the other hand, the NMOS transistors N1 and N2, which are components of the compensation control unit 424, generally have non-linear resistance values with respect to temperature variations regardless of the level of the voltage applied to the gate. The magnitude of the current flowing between them varies nonlinearly. That is, as the temperature increases, the resistance values of the NMOS transistors N1 and N2 increase nonlinearly regardless of the control by the second delayed clock DLY_CLK and the compensation control voltage INJECT_STR. The magnitude of the current flowing between the drain and the source of N1 and N2 decreases nonlinearly. On the contrary, as the temperature decreases, the resistance values of the NMOS transistors N1 and N2 decrease nonlinearly regardless of the control by the second delayed clock DLY_CLK and the compensation control voltage INJECT_STR. The magnitude of the current flowing between the drain and the source of N1 and N2 increases nonlinearly.

As described above, since the compensation adjusting unit 424 includes the NMOS transistors N1 and N2, the ring according to the change in temperature regardless of the control by the second delayed clock DLY_CLK and the compensation control voltage INJECT_STR may be used. The amount of current sinking in the oscillator 422 is varied non-linearly, and thus the amount of operating current of the ring oscillator 422 is non-linearly varied.

Specifically, the variation in the amount of current of the compensation control unit 424 decreases relatively small in the section where the temperature is relatively low and relatively large in the section where the temperature is high. For example, if the current amount of the compensation control unit 424 decreases by 0.1 percent every time the temperature increases by 1 degree between 0 degrees and 20 degrees, which is a relatively low temperature section, the temperature is increased from 40 degrees to 21 degrees which is a relatively high temperature section. Between degrees, each time the temperature increases by 1 degree, the current amount of the compensation control unit 424 decreases by 0.15 percent.

Accordingly, the variation of the operating current amount of the ring oscillator 422 increases relatively small in the section where the temperature is relatively low, and increases relatively in the section where the temperature is high. For example, if the operating current of the ring oscillator 422 increases by 0.1 percent every time the temperature is increased by 1 degree between 0 degrees and 20 degrees, which is a relatively low temperature section, the operating temperature of the ring oscillator 422 increases by 0.1 percent. Between the figures, each time the temperature increases by 1 degree, the operating current amount of the ring oscillator 422 increases by 0.15 percent.

As described above, it can be seen that the operating current of the ring oscillator 422 not only increases nonlinearly with increasing temperature, but also increases with increasing temperature. The oscillation delay amount also increases non-linearly with temperature fluctuations, and the non-linear increase direction increases as the temperature increases.

That is, the ring oscillator may increase in a nonlinear manner with an increase in temperature, and may compensate for the nonlinear delay increase characteristic of the second clock delay unit 400 having a characteristic of increasing slightly as the temperature increases. It can be seen that the oscillation delay amount of 422 is determined.

The operation of the temperature measuring circuit according to the second embodiment of the present invention disclosed in FIG. 4 will be described with reference to FIG. 7 as follows.

First, the delay amount of the second clock delay unit 400 (TDDL) increases nonlinearly with increasing temperature, but increases at a relatively high rate in a section where the temperature is relatively low, and relatively in a section where the temperature is relatively high. Increases at a lower rate.

In addition, the oscillation delay amount of the clock oscillator 420 (ILO) increases nonlinearly with increasing temperature, but increases at a relatively low rate in a section where the temperature is relatively low, and relatively high in a section where the temperature is relatively high. Increases in proportion.

Therefore, when the delay amount of the second clock delay unit 400 and the delay amount of the clock oscillator 420 are combined (TDDL + ILO) through an injection locking operation, it is applied to the finally outputted clock OSCLK. The amount of delay that is lost is in a state of having a linear characteristic as the temperature fluctuates.

The temperature detector 440 detects a change in temperature according to the phase difference between the first delayed clock DLL_CLK and the oscillation clock OSCLK.

That is, the temperature detector 440 may have a linear characteristic according to a change in phase and temperature of the first delayed clock DLL_CLK generated by delaying the source clock REF_CLK with a constant delay amount regardless of temperature fluctuations. Depending on the phase difference of the oscillation clock (OSCLK), it is easy to measure whether or not the temperature fluctuates.

In particular, after setting the delay amount of the delay amount of the second clock delay unit 400 and the delay amount of the clock oscillator 420 at the set temperature to the same state as the delay amount of the first clock delay unit 460, The temperature detector 440 starts operation at the set edge of the first delayed clock DLL_CLK, and counts the set edge of the oscillation clock OSCLK based on a set counting frequency having a high frequency (not shown). Including an analog-to-digital converting operation, it is possible to digitize and output temperature information very quickly and simply.

In addition, if the temperature detector 440 knows in which direction the set edge of the oscillation clock OSCLK is based on the set edge of the first delayed clock DLL_CLK, the temperature detector 440 may determine whether the temperature is increased or decreased. .

Third Embodiment

5 is a diagram for explaining a temperature measuring circuit according to a third embodiment of the present invention.

Referring to FIG. 5, the temperature measuring circuit according to the third embodiment of the present invention includes a first clock delay unit 560, a frequency divider 580, a second clock delay unit 500, and a clock oscillator ( 520, and a temperature change code generator 540. In addition, the temperature fluctuation fine code generating unit 590 is further provided. Here, the clock oscillator 520 includes a ring oscillator 522 and a compensation adjuster 524. In addition, the first clock delay unit 560 includes a delay line 562 and a delay lock operation unit 564.

For reference, the first clock delay unit 560, the second clock delay unit 500, and the clock oscillator 520 may include the first clock delay unit disclosed in the temperature measuring circuit according to the second embodiment of the present invention. 460, the second clock delay unit 400, and the clock oscillator 420 are exactly the same components. Therefore, detailed descriptions of the first clock delay unit 560, the second clock delay unit 500, and the clock oscillator 520 in the description of the temperature measuring circuit according to the third embodiment of the present invention will be described later. Reference may be made to the second embodiment.

However, in the temperature measuring circuit according to the second embodiment of the present invention, there is a difference that the frequency divider 580 is not disclosed between the first clock delay unit 460 and the second clock delay unit 400. In this regard, a description of the difference in operation will be given below.

In detail, the first clock delay unit 560 receives the source clock REF_CLK and always changes it with a constant delay amount regardless of the temperature variation, and outputs it as the first delay clock DLL_CLK. That is, the first clock delay unit 560 operates so that the source clock REF_CLK and the first delay clock DLL_CLK always have a constant delay amount regardless of temperature fluctuations.

The frequency divider 580 divides the frequency of the source clock REF_CLK at a set ratio and outputs it as the divided clock DIV_CLK. That is, the frequency of the clocks applied to the first clock delay unit 460 and the second clock delay unit 400 are different from each other. The reason and the detailed operation of the frequency divider 580 are described below. The configuration and operation of the variation code generator 540 will be described later.

The second clock delay unit 500 receives the distribution clock DIV_CLK, changes the non-linear delay amount according to the temperature variation, and outputs it as the second delay clock DLY_CLK. That is, the second clock delay unit 500 receives the divided clock DIV_CLK and delays it by a predetermined delay amount and outputs it as the second delayed clock DLY_CLK. At this time, as the temperature fluctuation occurs, the set delay amount fluctuates in a state having a non-linear characteristic.

In addition, the clock oscillator 520 oscillates the oscillation clock OSCLK having the same frequency in response to the second delayed clock DLY_CLK, but the non-linearity of the second clock delay unit 500 according to the change in temperature. The oscillation delay amount fluctuates in a direction to compensate for the loss. At this time, the variation in the oscillation delay amount in the clock oscillator 520 means that the oscillation frequency of the oscillation clock OSCLK is changed.

In detail, among the components of the clock oscillator 520, the ring oscillator 522 oscillates the oscillation clock OSCLK having a frequency difference within a set range from a frequency of the second delayed clock DLY_CLK in the first enable mode. In the second enable mode, the amount of oscillation delay varies in a direction in which the frequency of the oscillation clock OSCLK matches the frequency of the second delay clock DLY_CLK.

The compensator 524 among the components of the clock oscillator 520 may perform a ring oscillator 522 in response to a change in the second delayed clock DLY_CLK, the compensation control voltage INJECT_STR, and the temperature in the second enable mode. Adjust the amount of operating current. At this time, as described above, the compensation adjusting unit 524 changes the frequency of the oscillation clock OSCLK in the second enable mode of the ring oscillator 522, and the method includes the amount of operating current of the ring oscillator 522. It can be a way to control.

The temperature variation code generation unit 540 counts the phase variation width of the oscillation clock OSCLK according to the temperature variation based on the first delay clock DLL_CLK, and thus the temperature variation code TEMP_CCODE <3: 7>. Create At this time, the reason for counting the phase variation width of the oscillation clock OSCLK based on the first delay clock DLL_CLK is possible. The frequency divider 580 allows the frequency of the oscillation clock OSCLK and the first delay clock ( This is because the frequency of DLL_CLK) is set differently.

Specifically, the frequency divider 580 divides the frequency of the source clock REF_CLK by a set ratio and divides it into the divided clock DIV_CLK, whereby the frequency of the divided clock DIV_CLK is set to be higher than the frequency of the source clock REF_CLK. It works to be as low as the difference. In addition, since the first clock delay unit 460 operates by receiving the source clock REF_CLK, the frequency of the first delay clock DLL_CLK is the same as that of the source clock REF_CLK. On the other hand, since the second clock delay unit 400 and the clock oscillator 420 operate by receiving the divided clock DIV_CLK, the frequency of the oscillation clock OSCLK oscillated by the clock oscillator 420 is set by the set ratio difference. It is lower than the frequency of (REF_CLK).

As such, the frequency of the first delayed clock DLL_CLK is higher than the frequency of the oscillation clock OSCLK by the frequency divider 580 and is set by the first clock delayed unit 560. (DLL_CLK) is not affected by the temperature fluctuation, while the oscillation clock OSCLK by the second clock delay unit 500 and the clock oscillator 520 has a linear phase change with respect to the temperature fluctuation. Therefore, the temperature change code generator 540 calculates the digital value of the oscillation clock OSCLK by counting the first delayed clock DLL_CLK without including a separate analog-to-digital converter therein, and calculates the result. It is thus possible to generate a temperature variation code TEMP_CCODE <3: 7>.

In more detail, the configuration of the delay line 462 among the components of the first clock delay unit 560 is connected in a chain form, and the delay amount in response to the change in temperature and the delay control signal DLY_CON, respectively. It can be seen that it includes a plurality of inverters INV [0: 3] that are regulated. At this time, the delay line 462 is output from each of the plurality of inverters INV [0: 3] included in the delay line 462 since the source clock REF_CLK is applied and output as the first delay clock DLL_CLK. The phase of the clock may have either phase between the phase of the source clock REF_CLK and the phase of the first delayed clock DLL_CLK.

Therefore, when the phase of the oscillation clock OSCLK is detected based on the phase of each of the plurality of clocks output from each of the plurality of inverters INV [0: 3], the temperature output from the temperature variation code generator 540. Detects code values in units smaller than one period of the first delayed clock DLL_CLK that are not counted by the change code TEMP_CCODE <3: 7>, that is, the value of the temperature change fine code TEMP_FCOND <0: 2>. It is possible to do

As such, the phases of the oscillation clock OSCLK and the clocks output from each of the plurality of inverters INV [0: 3] are compared to determine the value of the temperature fluctuation fine code TEMP_FCOND <0: 2>. The component is the temperature fluctuation fine code generator 590.

The operation of the temperature measuring circuit according to the third embodiment of the present invention disclosed in FIG. 5 with reference to FIGS. 6 and 7 is as follows.

First, referring to FIG. 7, the delay amount of the second clock delay unit 500 (TDDL) increases nonlinearly with increasing temperature, but increases at a relatively high rate in a section where the temperature is relatively low. In relatively high intervals it increases at a relatively low rate.

In addition, the oscillation delay of the clock oscillator 520 (ILO) increases nonlinearly with increasing temperature, but increases at a relatively low rate in a section where the temperature is relatively low, and relatively high in a section where the temperature is relatively high. Increases in proportion.

Therefore, when the delay amount of the second clock delay unit 500 and the delay amount of the clock oscillator 520 are combined (TDDL + ILO) through an injection locking operation, it is applied to the finally outputted clock OSCLK. The amount of delay that is lost is in a state of having a linear characteristic as the temperature fluctuates. That is, the phase of the oscillation clock OSCLK may be linearly changed in accordance with temperature variation compared to the distribution clock DIV_CLK.

Subsequently, referring to FIG. 6, since the frequency of the first delayed clock DLL_CLK is very high compared to the distribution clock DIV_CLK and the oscillation clock OSCLK, the oscillation is based on the counting value of the first delayed clock DLL_CLK. It can be seen that the temperature is measured by measuring the phase shift of the clock OSCLK.

Specifically, for example, the first delay clock DLL_CLK is 1 Ghz, and the distribution clock DIV_CLK and the oscillation clock OSCLK are 31.25 Mhz. That is, the frequency of the first delayed clock DLL_CLK has a frequency 32 times higher than that of the distribution clock DIV_CLK and the oscillation clock OSCLK.

In addition, the first delay clock DLL_CLK is in phase with the source clock REF_CLK by a first clock delay unit 560 performing a delay lock operation, and the distribution clock DIV_CLK sets the frequency of the source clock REF_CLK. Since it is only a divided clock, the phases of the first delayed clock DLL_CLK and the distributed clock DIV_CLK are in a synchronized state.

As such, when the phases of the first delayed clock DLL_CLK and the distribution clock DIV_CLK are synchronized, the counting count of the first delayed clock DLL_CLK starts counting to correspond to the edge of the oscillation clock OSCLK. Notice that the counted value is 10 at the first temperature (TEMP1).

However, from the time when the phases of the first delayed clock DLL_CLK and the distribution clock DIV_CLK are synchronized, the counting count of the first delayed clock DLL_CLK starts counting to correspond to the edge of the oscillation clock OSCLK. Notice that the counted value is 22 at the first temperature (TEMP1).

That is, the phase of the oscillation clock (OSCLK) has a large difference depending on whether the temperature is the first temperature (TEMP1) or the second temperature (TEMP2), even by counting this based on the first delay clock (DLL_CLK). It is possible to generate the temperature variation code (TEMP_CCODE <3: 7>), which is a digital value, without any calculation.

In addition, the temperature fluctuation fine code generation unit 590 divides one cycle (1 tck) of the first delayed clock DLL_CLK and compares it with the phase of the oscillation clock OSCLK, and then the temperature fluctuation fine code TEMP_FCOND <0: 2>), it is possible to measure the digital value with temperature fluctuation very precisely.

As described above, when the embodiment of the present invention is applied, a time-delay in which a linear characteristic can be applied to a change in temperature by combining two time-delay schemes having non-linear characteristics opposite to the change in temperature is mutually different. By measuring the temperature using the method, the accuracy of the temperature measurement can be greatly improved.

In addition, in implementing two time-delay schemes having opposite characteristics with respect to the change in temperature, the size of the added circuit can be minimized.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented in different positions and types depending on the polarity of the input signal.

300: clock delay unit 320, 420, 520: clock oscillation unit
340, 440: temperature detector 322: ring oscillator
324: compensation controller 460: first clock delay unit
400: second clock delay unit 462, 562: delay line
464, 564: delay lock operation unit 580: frequency divider
540: temperature variation code generation unit 590: temperature variation fine code generation unit

Claims (20)

A clock delay unit which receives the source clock and changes the non-linear delay amount according to the temperature change and outputs the delayed clock as a delay clock;
A clock oscillation unit oscillating an oscillation clock having the same frequency in response to the delay clock, the oscillation delay of which fluctuates in a direction for compensating for nonlinearity of the clock delay unit according to a change in temperature; And
A temperature detector configured to detect a change in temperature according to a phase difference between the source clock and the oscillation clock,
The clock oscillator oscillates the oscillation clock having a frequency difference within a set range from a frequency of the delay clock in a first enable mode, and sets the frequency of the oscillation clock to the frequency of the delay clock in a second enable mode. A ring oscillator having an oscillation delay varying in a matching direction, and an integrated circuit including a compensation adjusting unit configured to adjust an operating current amount of the ring oscillator in response to variations in the delay clock, compensation control voltage, and temperature in the second enable mode. .
delete The method of claim 1,
The compensation control unit,
And controlling the oscillation delay amount of the ring oscillator by decreasing or increasing the operation current amount of the ring oscillator in a direction to compensate for the nonlinearity of the clock delay unit in response to a change in temperature.
The method of claim 3,
The compensation control unit,
And an adjustable width of an operating current amount of the ring oscillator is determined in response to the level of the compensation control voltage.
The method of claim 4, wherein
The compensation control unit,
A first NMOS transistor controlled on / off in response to the delay clock between the ring oscillator and an operating node; And
And a second NMOS transistor configured to adjust an amount of current flowing between the operation node and a ground voltage terminal according to the level of the compensation control voltage.
A first clock delay unit which receives the source clock and always changes the constant delay amount as a first delay clock regardless of a change in temperature;
A second clock delay unit which receives the source clock and changes it as a non-linear delay amount according to a change in temperature and outputs it as a second delay clock;
A clock oscillation unit oscillating an oscillation clock having the same frequency in response to the second delay clock, the oscillation delay of which fluctuates in a direction compensating for nonlinearity of the second clock delay unit in response to a change in temperature; And
A temperature detector configured to detect a temperature change according to a phase difference between the first delayed clock and the oscillation clock,
The clock oscillator oscillates the oscillation clock having a frequency difference within a set range from a frequency of the second delay clock in a first enable mode, and oscillates at a frequency of the second delay clock in a second enable mode. A ring oscillator whose oscillation delay is varied in a direction of matching a clock frequency, and a compensation for adjusting an operating current amount of the ring oscillator in response to a change in the compensation voltage and temperature with the second delay clock in the second enable mode. Integrated circuit having a control unit.
The method of claim 6,
The first clock delay unit,
A delay line adjusted in response to a change in temperature and a delay control signal, the delay line delaying the source clock and outputting the first delay clock; And
And a delay lock operation unit configured to compare a phase of the source clock and the first delay clock for a delay lock operation and to adjust a value of the delay control signal according to a comparison result.
delete The method of claim 6,
The compensation control unit,
And controlling the oscillation delay amount of the ring oscillator by decreasing or increasing the amount of operating current of the ring oscillator in a direction to compensate for nonlinearity of the second clock delay portion in response to a change in temperature.
The method of claim 9,
The compensation control unit,
And an adjustable width of an operating current amount of the ring oscillator is determined in response to the level of the compensation control voltage.
The method of claim 10,
The compensation control unit,
A first NMOS transistor controlled on / off in response to the second delay clock between the ring oscillator and an operating node; And
And a second NMOS transistor configured to adjust an amount of current flowing between the operation node and a ground voltage terminal according to the level of the compensation control voltage.
The method of claim 6,
And the delay amount obtained by adding the delay amount of the second clock delay unit and the delay amount of the clock oscillation unit at the set temperature is equal to the delay amount of the first clock delay unit.
A first clock delay unit which receives the source clock and always changes the constant delay amount as a first delay clock regardless of a change in temperature;
A frequency divider for distributing a frequency of the source clock at a set ratio to generate a divided clock;
A second clock delay unit which receives the distribution clock and changes the non-linear delay amount according to the temperature change and outputs the second delay clock as a second delay clock;
A clock oscillator configured to oscillate an oscillation clock having the same frequency in response to the second delay clock, the oscillation delay of which fluctuates in a direction compensating for nonlinearity of the second clock delay unit in response to a change in temperature; And
A temperature variation code generator configured to generate a temperature variation code by counting a phase variation width of the oscillation clock based on the first delay clock based on a temperature variation
Integrated circuit comprising a.
The method of claim 13,
The first clock delay unit,
A delay line adjusted in response to a change in temperature and a delay control signal, the delay line delaying the source clock and outputting the first delay clock; And
And a delay lock operation unit configured to compare phases of the source clock and the first delay clock for a delay lock operation, and adjust a value of the delay control signal according to a comparison result.
The method of claim 14,
The delay line includes a plurality of inverters connected in a chain form and whose delay amounts are respectively adjusted in response to a change in temperature and a delay control signal,
And a temperature fluctuation fine code generator for comparing the phases of the oscillation clock and the plurality of clocks output from each of the plurality of inverters and generating a temperature fluctuation fine code according to a comparison result.
The method of claim 13,
The clock oscillator,
Oscillate the oscillation clock having a frequency difference within a set range from a frequency of the second delay clock in a first enable mode, and match a frequency of the oscillation clock to a frequency of the second delay clock in a second enable mode A ring oscillator in which oscillation delay amount is changed in a direction to make it oscillate; And
And a compensation controller configured to adjust an operating current amount of the ring oscillator in response to a change in the second delay clock, compensation control voltage, and temperature in the second enable mode.
The method of claim 16,
The compensation control unit,
And controlling the oscillation delay amount of the ring oscillator by decreasing or increasing the amount of operating current of the ring oscillator in a direction to compensate for nonlinearity of the second clock delay portion in response to a change in temperature.
The method of claim 17,
The compensation control unit,
And an adjustable width of an operating current amount of the ring oscillator is determined in response to the level of the compensation control voltage.
The method of claim 18,
The compensation control unit,
A first NMOS transistor controlled on / off in response to the second delay clock between the ring oscillator and an operating node; And
And a second NMOS transistor configured to adjust an amount of current flowing between the operation node and a ground voltage terminal according to the level of the compensation control voltage.
The method of claim 13,
And the delay amount obtained by adding the delay amount of the second clock delay unit and the delay amount of the clock oscillation unit at the set temperature is equal to the delay amount of the first clock delay unit.

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