KR102048515B1

KR102048515B1 - Ldpc encoding, decoding method and device using the method

Info

Publication number: KR102048515B1
Application number: KR1020130077296A
Authority: KR
Inventors: 신동준; 주형건
Original assignee: 주식회사 아리스케일
Priority date: 2013-07-02
Filing date: 2013-07-02
Publication date: 2019-11-25
Also published as: KR20150004489A

Abstract

An LDPC encoding and decoding method and an apparatus using the method are provided. The LDPC encoding method of the present invention includes (a) performing Low Density Parity Check (LDPC) encoding on data to be encoded, and (b) performing additional encoding on a specific bit of a code word in which the LDPC encoding is performed. Performing the steps.

Description

LDPC encoding and decoding method and apparatus using the method {LDPC ENCODING, DECODING METHOD AND DEVICE USING THE METHOD}

The present invention relates to a low density parity check (LDPC) encoding and decoding method and an apparatus using the method, and more particularly, to an LDPC encoding and decoding method for error floor improvement and an apparatus using the method. will be.

Next-generation communication systems are progressing in the form of supporting high-speed mass data transmission and reception, and turbo codes and low density parity check (LDPC) codes having a performance close to channel capacity are used to support high-speed mass data transmission and reception.

In addition, the storage device uses a high code rate error correction code to increase the density of information storage. Recently, the case of applying the LDPC code to the storage device has been increasing.

The LDPC code has a problem in that an error floor occurs due to an input range of the decoder and a decoding algorithm of the code.

In order to overcome this problem, various methods have been proposed to improve the error floor through the analysis of a similar codeword known as the cause of the error floor or a trapping set analysis.

However, the existing methods mainly focus on the theoretical analysis of the structure of the trapping set, which is the cause of the error floor phenomenon, and there are not many specific techniques proposed to remove them.

In addition, the existing methods concentrate on improving the error floor by modifying the decoding algorithm, which not only causes additional decoding complexity but also causes a loss of a transmission rate (or code rate), which makes it easy to implement and improve the error floor. It still does not provide a solution.

The present invention is to solve the above-mentioned problems of the prior art, and to provide an LDPC encoding and decoding method and an apparatus using the method for improving the error floor of the LDPC (Low Density Parity Check) code.

In order to achieve the above object, the LDPC encoding method according to an embodiment of the present invention comprises the steps of a) performing LDPC (Low Density Parity Check) encoding on the data to be encoded; and (b) the LDPC encoding is performed. Performing additional encoding on a specific bit of the code word.

In an aspect of the present invention, step (b) performs the additional encoding by using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.

In addition, in one aspect of the present invention, the LDPC encoding method further includes (c) performing puncturing on the code word.

In addition, in one aspect of the present invention, the step (c) includes the step of determining the number of bits to perform the puncturing corresponding to the number of parity bits added by the additional encoding of the step (b).

In order to achieve the above object, the LDPC decoding method according to an embodiment of the present invention comprises the steps of (a) performing a decoding on a specific bit that is previously selected and additionally coded in a code word to be decoded; (b) performing LDPC (Low Density Parity Check) decoding using the value of the specific bit decoded in the step (a).

In order to achieve the above object, the LDPC decoding method according to another embodiment of the present invention comprises the steps of (a) performing a Low Density Parity Check (LDPC) decoding on a code word that is a decoding target, (b) If the decoding of step (a) fails, performing decoding on a predetermined bit that is previously selected and additionally coded in the code word, and (c) using a value for the specific bit decoded in step (b). Performing LDPC decoding.

In one or another aspect of the present invention, in the LDPC decoding method, when a punctured bit exists in the code word, the LDPC decoding method replaces the punctured bit with a neutral value having a Log Likelihood Ratio (LLR) value of 0. It further comprises the step of decoding.

In one aspect of the present invention, the LDPC decoding method further includes (c) repeating steps (a) and (b) if the decoding of step (b) fails.

In one aspect or the other aspect of the present invention, the LDPC decoding method reflects different weights in each result of the decoding of the additionally encoded specific bits and the LDPC decoding.

In order to achieve the above object, the LDPC encoding apparatus according to an embodiment of the present invention, the LDPC encoder for performing LDPC (Low Density Parity Check) encoding on the data to be encoded and the code word on which the LDPC encoding is performed And an additional encoder that performs additional encoding on a specific bit of.

In one aspect of the present invention, the additional encoder performs the additional encoding by using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.

In one aspect of the present invention, the LDPC encoding apparatus further includes a puncturing unit for performing puncturing on the code word.

In one aspect of the invention, the puncturing unit determines the number of bits to perform the puncturing corresponding to the number of parity bits added by the additional encoding.

In order to achieve the above object, the LDPC decoding apparatus according to an embodiment of the present invention, the additional decoding unit for performing decoding on a specific bit pre-selected and additionally coded in the code word (code word) to be decoded; And an LDPC decoder configured to perform low density parity check (LDPC) decoding by using a value of a specific bit decoded by the additional decoder.

In order to achieve the above object, the LDPC decoding apparatus according to another embodiment of the present invention, the LDPC decoding unit for performing a low density parity check (LDPC) decoding on the code word (code word) to be decoded and the LDPC decoding If the negative decoding fails, an additional decoding unit which performs decoding on a predetermined bit that is previously selected and additionally encoded in the code word, the LDPC decoding unit using a value for the specific bit decoded by the additional decoding unit LDPC decoding is performed.

In one or another aspect of the present invention, when there is a punched bit in a code word, the additional decoder replaces the punctured bit with a neutral value having a Log Likelihood Ratio (LLR) value of 0 to decode.

In one or another aspect of the present invention, the LDPC decoder and the additional decoder reflect different weights to the results of each decoding.

According to one embodiment of the present invention, it is possible to ensure system performance by improving error flooring while minimizing transmission loss.

In addition, the present invention can be utilized for error correction codes of communication systems requiring real time high speed data transmission and storage devices requiring high information storage density.

The effects of the present invention are not limited to the above-described effects, but should be understood to include all the effects deduced from the configuration of the invention described in the detailed description or claims of the present invention.

1 is a diagram illustrating a configuration of an LDPC encoding apparatus according to an embodiment of the present invention.
2A is a diagram illustrating a configuration of an LDPC decoding apparatus according to another embodiment of the present invention.
2B is a diagram illustrating a position to which additional decoding is applied according to an embodiment of the present invention.
3 is a flowchart illustrating an LDPC encoding process according to an embodiment of the present invention.
4 is a flowchart illustrating an LDPC decoding process according to an embodiment of the present invention.
5 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
6 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
7 to 9 are graphs showing the results of the error floor improvement according to the embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, it includes not only "directly connected" but also "indirectly connected" with another member in between. .

In addition, when a part is said to "include" a certain component, this means that it may further include other components, without excluding the other components unless otherwise stated.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of an LDPC encoding apparatus according to an embodiment of the present invention.

The low density parity check (LDPC) encoding apparatus 100 according to an embodiment of the present invention may include an LDPC encoder 110, an additional encoder 120, a puncturing unit 130, and a code word provider 140. ) May be included.

For reference, the LDPC encoding apparatus 100 illustrated in FIG. 1 may be included in a transmitting end in case of a communication system (hereinafter, referred to as a “communication system”) requiring real time high speed data transmission, and having a high information storage density. A device (hereinafter referred to as a "storage device") may be included in the encoder.

Referring to each component, the LDPC encoder 110 may perform LDPC encoding on data to be encoded, and may generate a parity bit and include it in a codeword in which encoding is performed.

Hereinafter, the parity bits generated during LDPC encoding will be referred to as 'first parity bits'.

Meanwhile, the additional encoder 120 may perform additional encoding on a specific bit of a code word in which LDPC encoding is performed.

Here, the specific bit may be selected in advance according to a trapping-set analysis result, and the additional encoder 120 may decode the specific bit at the receiving end of the communication system or the decoding unit of the storage device. Additional encoding may be performed (eg, adding a parity bit for the specific bit to a code word) to enable reconstruction.

In this case, the additional encoder 120 may perform the additional encoding using an encoding method including one or more of repetition, Bose-Chadhuri-Hocquenghem (BCH) code, and Reed-Solomon (RS) encoding.

Hereinafter, in order to increase the reconstruction accuracy of the specific bit, a bit added to the code word through additional encoding of the additional encoder 120 may be referred to as a 'second parity bit'.

For reference, for additional encoding, a specific bit selected in advance according to the trapping set analysis result may be selected according to predetermined promises of the transmitting end and the receiving end, and the LDPC encoding apparatus 100 may use one or more (j) at a time by the following method. You can select a specific bit of).

As a first method of selecting one or more (j) specific bits at a time, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position in an error floor region through simulation.

Thereafter, the LDPC encoding apparatus 100 determines the structure of the trapping set and selects the bits having the most error in different trapping sets (total j bits are selected for each trapping set) (1-1).

As another example of the first bit selection method, the LDPC encoding apparatus 100 obtains a histogram of an error number for each codeword bit position in an error floor region through simulation.

Thereafter, the LDPC encoding apparatus 100 may select j bits having the most error (1-2).

As a second bit selection method for selecting one or more (j) specific bits at a time, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position in an error floor region through simulation. ).

Thereafter, the LDPC encoding apparatus 100 selects one bit having the most error (2-2).

Thereafter, the LDPC encoding apparatus 100 performs a simulation of decoding by inserting a known value (0 or 1) into the selected bit and performing a decoding operation to obtain a histogram of the number of errors for each codeword bit position (2-3). ).

Thereafter, the LDPC encoding apparatus 100 repeats processes 2-2 and 2-3 until j bits are selected (2-4).

As a third bit selection method for selecting one or more (j) specific bits at a time, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position in the error floor region through simulation, Identify the trapping set structure that has a large impact (3-1).

Thereafter, the LDPC encoding apparatus 100 grasps the trapping set that affects the error floor among all trapping sets including the bit having the largest error and selects all bits constituting the trapping set (3-2).

Thereafter, if the number of selected bits is less than j, the LDPC encoding apparatus 100 selects the bit having the largest error count among the unselected bits and selects the bits similarly to step 3-2 (3-3).

Thereafter, the LDPC encoding apparatus 100 repeats steps 3-3 until the j bit is selected (3-4).

If the number of bits selected is greater than j, the LDPC encoding apparatus 100 may apply a method of selecting j pieces having a relatively large error number among the bits selected in the last step, or selecting bits in a trapping set unit.

Here, the third method can select bits in a trapping set unit differently from the first method and the second method, so that the small trapping set can completely remove the trapping set.

For reference, in general, the size of the main trapping set that adversely affects the error floor in the high SNR region is relatively small.

The number of bits to choose depends on the desired system performance and complexity.

For example, if you don't need to consider the complexity a lot, the more bits you choose, the better your error floor performance. If your system complexity is your primary consideration, there are a variety of ways to get the optimal number of bits to achieve the desired performance. You can decide.

Meanwhile, the puncturing unit 130 may perform puncturing on bits of a code word in order to maintain a code rate of information bits, and the bits on which puncturing is performed may be previously selected.

In this case, the puncturing unit 130 may determine the number of bits for puncturing corresponding to the number of second parity bits on which additional encoding is performed.

For reference, the puncturing unit 130 may select a bit to be punctured based on the following criteria.

1. The perforated bits are selected to minimize performance degradation by the perforated bits.

2. The bits to be drilled should be chosen to avoid the bits contained in the main trapping set that affect the error floor.

3. The bits to be punctured choose not to produce a trapping set of short length by the bits to be punctured.

4. Select the bits to be punctured to maintain regular regular intervals (equivalent intervals) (especially for signs where parity bits are generated in the form of dual diagonals).

For reference, a specific bit, which is the target of puncturing, may be decoded by being replaced with a neutral value having a Log Likelihood Ratio (LLR) value of 0 when decoding at the receiving end, and thus, the decoding convergence speed is reduced (decoding is performed several times) In this case, a check node merging method may be applied.

Meanwhile, the code word provider 140 may include the first parity bits generated by the LDPC encoder 110 and the second parity bits and the puncturing unit 130 added by the additional encoder 120. The codeword encoded by including one or more of the bits punctured by may be stored in a specific storage or transmitted to a specific medium (receiver, decoding device) through any communication means or communication channel.

2A is a diagram illustrating a configuration of an LDPC decoding apparatus according to another embodiment of the present invention.

The LDPC decoding apparatus 200 according to another embodiment of the present invention may include an additional decoder 210 and an LDPC decoder 220.

For reference, the LDPC decoding apparatus 200 illustrated in FIG. 2A may be included in a receiving end in a communication system, and may be included in a decoding part in a storage device.

In describing each component, when the code word is received from the transmitting end of the communication system or the encoding unit of the storage device, the additional decoder 210 refers to the second parity bit included in the received code word for a specific bit. Decryption can be performed.

Here, the second parity bit is an additionally coded value for a specific bit previously selected according to the trapping set analysis result by the transmitting end of the communication system or the encoding unit of the storage device, and the additional decoder 210 refers to the second parity bit. It is possible to more precisely restore that particular bit.

In addition, when the decoding of the code word fails in the LDPC decoding unit 220 to be described later, the additional decoding unit 210 performs decoding on a specific bit by referring to the second parity bit included in the code word, and then decodes the decoding unit. A more accurate value for the specific bit in which the is performed may be transmitted to the LDPC decoder 220.

For reference, when the punctured bit exists in the code word, the additional decoder 210 may decode the punctured bit by replacing it with a neutral value having an LLR value of zero.

Therefore, when the additional decoding unit 210 performs decoding, the decoding is performed before the LDPC decoding unit 220 performs the LDPC decoding on the code word or the LDPC decoding unit 220 performs the LDPC decoding on the code word. This may be the case.

Meanwhile, when a code word is received from a transmitting end of a communication system or an encoding unit of a storage device, the LDPC decoder 220 may perform LDPC decoding on a code word by referring to a first parity bit included in the received code word. Can be.

If the LDPC decoding of the code word fails, the LDPC decoding unit 220 refers to a reconstruction value (ie, a value decoded with reference to the second parity bit) for a specific bit received from the additional decoding unit 210. LDPC decoding can be performed.

Therefore, the decoding time of the LDPC decoding unit 220 is a code word (LLR value) after receiving the code word (LLR value) from the transmitting end of the communication system or the encoding unit of the storage device, or the additional decoding unit 210 is the transmission end or storage device of the communication system. The decoding may be performed after first decoding the specific bit by referring to the second parity bit included in the codeword (received LLR value) received from the encoder.

2B is a diagram illustrating a position to which additional decoding is applied according to an embodiment of the present invention.

As illustrated in FIG. 2B, additional decoding may be applied to a value received from a channel and entering an input terminal of the LDPC decoder 220 (a), and to a decoded LLR value output from an output terminal of the LDPC decoder 220. Additional decoding may be applied (b). For example, a decoded LLR value and a value obtained through additional decoding may be combined with a predetermined weight.

3 is a flowchart illustrating an LDPC encoding process according to an embodiment of the present invention.

For reference, the LDPC encoding process illustrated in FIG. 3 may be performed by the LDPC encoding apparatus 100 illustrated in FIG. 1, that is, the transmitting unit or the encoding unit in the case of a communication system.

First, the LDPC encoding apparatus 100 performs LDPC encoding on data to be encoded (S301).

In this case, the LDPC encoding apparatus 100 may generate a first parity bit.

After S301, the LDPC encoding apparatus 100 performs additional encoding (adding a second parity bit) on a specific bit of a code word in which LDPC encoding is performed (S302).

In this case, the LDPC encoding apparatus 100 may perform additional encoding using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.

After S302, the LDPC encoding apparatus 100 punctures the bits of the code word in order to maintain the code rate of the information bits (S303).

In this case, the LDPC encoding apparatus 100 may determine the number of bits to perform the puncturing corresponding to the number of second parity bits added in S302.

After S303, the LDPC encoding apparatus 100 may include a code word including at least one of a first parity bit generated in S301, a second parity bit added in S302, and a bit punctured in S303. Transmission to the decoder (S304).

Hereinafter, the LDPC decoding process of the present invention will be described with reference to FIGS. 4 to 6.

For reference, the LDPC decoding process illustrated in FIGS. 4 to 6 may be performed by the LDPC decoding apparatus 200 illustrated in FIG. 2, that is, the receiver in the case of a communication system or the decoder in the case of a storage device. Based on the execution time, it can be classified into 1. pre-processing, 2. post-processing, and 3. hybrid-processing methods.

4 is a flowchart illustrating an LDPC decoding process according to an embodiment of the present invention.

4 is a case of preferentially decoding a specific bit by referring to a second parity bit included in a code word (received LLR value) received from an encoder in a transmission system or a storage device in a communication system. It may correspond to.

First, the LDPC decoding apparatus 200 performs decoding on a specific bit by referring to a second parity bit included in a code word (a received LLR value) that is a decoding target (S401).

In this case, when a punctured bit exists in the code word, the LDPC decoding apparatus 200 may decode the punctured bit by replacing it with a neutral value having a Log Likelihood Ratio (LLR) value of zero.

In addition, the LDPC decoding apparatus 200 reflects a weight on a value of a specific bit decoded in S401, so that the coded value decoded in S401 has a higher reliability than the existing received LLR value for the specific bit during codeword decoding. You can do that.

For reference, in the case of using a soft decision in code word decoding, the LDPC decoding apparatus 200 may obtain a new received value by combining the result of applying additional decoding on the specific bit with the received LLR value. The new received value may have a higher reliability than the existing received LLR value.

If a hard decision is used when decoding a code word, the LDPC decoding apparatus 200 may change the reception value of a corresponding position as a result of applying additional decoding to the specific bit.

After S401, the LDPC decoding apparatus 200 may perform LDPC decoding with reference to the specific bit value and the first parity bit decoded in S401 (S402).

5 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.

FIG. 5 is a case of performing LDPC decoding on a code word (received LLR value) received from an encoder in a transmission system or a storage device in the case of a communication system, and may correspond to 2. post-processing.

First, the LDPC decoding apparatus 200 decodes a code word by referring to a first parity bit included in a code word (a received LLR value) that is a decoding target (S501).

If decoding fails in S501, the LDPC decoding apparatus 200 reflects a specific weight (hereinafter, referred to as 'w1') with respect to the result decoded in S501, and refers to a specific bit by referring to the second parity bit included in the code word. Decryption is performed at step S502.

In this case, when a punctured bit exists in the code word, the LDPC decoding apparatus 200 may perform decoding by replacing the punctured bit with a neutral value having an LLR value of zero.

For reference, in the case of using a soft decision in code word decoding, the LDPC decoding apparatus 200 may obtain a new received value by combining a result of applying additional decoding on the specific bit with a received LLR value. The new received value may have a higher reliability than the existing received LLR value.

In addition, the LDPC decoding apparatus 200 may adjust the reliability by reflecting a specific weight (hereinafter, referred to as 'w2') with respect to the result decoded in S502.

For reference, since the w2 value is a value reflected when the decoding fails in S501, the reliability of the value of a specific decoded bit can be very large. In the case of w1, the value of w2 is also reflected when decoding is repeated. Since decoding is performed by applying, the value reflected in the decoding result may increase as decoding is repeated (however, w1 <w2).

As a result, w1 and w2 are for the decoded result value to have a higher reliability than the received LLR value.

After S502, the LDPC decoding apparatus 200 may perform LDPC decoding by referring to the value of the specific bit decoded in S502 and the first parity bit (S503).

6 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.

For reference, the LDPC decoding process illustrated in FIG. 6 may be performed by mixing the processes of FIGS. 4 and 5 and may correspond to 3. hybrid-processing.

First, the LDPC decoding apparatus 200 performs decoding on a specific bit by referring to a second parity bit included in a code word (a received LLR value) that is a decoding target (S601).

In this case, when a punctured bit related to the second parity bit is present in the code word, the LDPC decoding apparatus 200 may perform decoding by replacing the punctured bit with a neutral value having an LLR value of zero.

In addition, the LDPC decoding apparatus 200 may reflect a specific weight (hereinafter, referred to as 'w1') to the result decoded in S601 so that the decoded result value has a higher reliability than the received LLR value.

After S601, the LDPC decoding apparatus 200 performs LDPC decoding by referring to a value of a specific bit decoded in S601 and a first parity bit included in a code word (S602).

If the decoding fails in S602, the LDPC decoding apparatus 200 reflects a specific weight (hereinafter referred to as 'w2') in the result decoded in S602, the decoding result reflecting w2 and the second parity bits included in the code word. Referring to (S603), decoding is performed on a specific bit.

In this case, the LDPC decoding apparatus 200 may reflect a specific weight (hereinafter, referred to as 'w3') in the result decoded in S603 to make the result value decoded in S603 have a higher reliability than the received LLR value. .

After S603, the LDPC decoding apparatus 200 performs LDPC decoding with reference to a value for a specific bit in which w3 is reflected and a first parity bit in S603 (S604).

For reference, since the decoding process of S604 is performed by using the value decoded through S603, the decoding process may have a relatively higher reliability than the case of simply decoding the LLR value received from the channel. You can get performance.

If decoding fails in S604, the LDPC decoding apparatus 200 may repeat the processes of S603 and S604.

7 to 9 are graphs showing the results of the error floor improvement according to the embodiment of the present invention.

For reference, we simulate a zigzag code with code rate 1/2, codeword length (n, k) = (1000, 500), binary phase shift key (BPSK) modulation, additive white Gaussian noise (AWGN) channel, Min-sum algorithm and floating point simulation are assumed.

First, FIGS. 7 and 8 are graphs showing the maximum performance that the system can obtain when the parity bit is additionally applied to a specific bit previously selected according to the trapping set analysis result.

7 and 8 show FER performance graphs of various techniques depending on the number of bits selected, where each selected bit was selected by one bit from a different trapping set, and the three selected bits were bits 351 and 368. Bit 1 and bit 504

In FIG. 7 and FIG. 8, original represents the performance of the original code to which nothing is applied, and a known value is a selected bit of the trapping set (for reference, not only an information bit but also a parity bit) in the encoding step. It may be punctured before transmission, and the LLR value of the corresponding bit may be allocated to a maximum value (± ∞) according to the sign of the bit selected at the decoding end.

The application position of the decoding technique was applied to the received value of the LDPC decoder 220 input stage. At this time, a repetition code was selected as an additional coding method for the selected bit, and the number of repetitions used in the code was 3 times. .

When the pre-processing technique is applied, the received value of the selected bit and three related bits are soft-combined to determine the new received value, and the weight factor is assumed to be 1.

In the post-processing technique, the selected bits are decoded using soft decision majority decoding on three bits obtained by additional coding (parity bits added for a specific bit preselected according to the trapping set analysis result), and the decoded bits are decoded. Accordingly, the LLR value is allocated to the corresponding bit and determined as the new received value of the LDPC decoder 220.

That is, the output of the additive decoder 210 is applied to the LDPC decoder 220 as if it is a known bit (the reliability of the signal decoded by the additive decoder 210 is set very large (w2 = ∞)). .

It is also assumed that the repetition between the LDPC decoder 220 and the additive decoder 210 is one (w1 = 0).

In FIG. 7, the original, known, and pre-processing technique applied the maximum number of repetitions 50 times for the iterative decoding of the LDPC decoder 220, and the additional 30 times the post-processing 50 times.

That is, if the LDPC decoding unit 220 fails to decode up to 50 times of repeated decoding, additional 30 times (up to 30 times) of decoding is performed using the newly obtained value through post-processing.

As shown in FIG. 7, a simple repetition code is used for the selected specific bit, and the proposed pre-processing and post-processing techniques show an excellent error floor improvement effect compared to the original.

In addition, as the number of selected specific bits increases, the performance gain increases, and when a total of 3 bits are selected, the gain may be about 0.6 dB at FER = 3 × 10 −4.

On the other hand, Figure 8 shows a graph of the FER performance assuming a decoding complexity equal to the decoding complexity of the post-processing technique.

That is, FER performance was compared by applying the same iteration decoding count (maximum iteration count = 80) to all the techniques, and it can be seen that the results show a similar tendency to the graph of FIG. 7.

For reference, hybrid-processing combined with pre-processing and post-processing techniques showed almost the same performance as the post-processing technique in the simulation environment.

However, the number of iterations used for decoding may be reduced to obtain the same performance, and additional performance gain may be obtained when different decoding algorithms are used for the additional decoding unit 210.

FIG. 9 is a diagram illustrating a FER performance graph of a post-processing technique and a post-processing technique in which puncturing is reflected according to the number of selected bits.

The known value technique has a code rate of approximately (k-j) / (n-j), and pre-processing and post-processing have a code rate of k / (n + jm).

Therefore, when using a code supporting a low code rate, if the number of bits j selected or the number of bits jm used for additional coding is small, the transmission efficiency of the proposed scheme may be improved.

In addition, by drilling additional bits (jm) in the proposed scheme, we can support the code rate k / n of the mother code

In this case, a slight performance degradation may be obtained as compared with the case where no puncture is performed. The performance graph when the code rate of the mother code is supported by puncturing is shown in FIG. 9.

The more bits are punctured, the lower the performance. However, compared to the original, the same code rate is supported but the performance is very good.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be.

Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present invention is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present invention.

100: LDPC encoder
110: LDPC encoder
120: additional encoder
130: perforation
140: code word provider
200: LDPC decoding device
210: additional decoder
220: LDPC decoder

Claims

In the data transmission method,
Generating an encoded code word; And
Transmitting the encoded codeword,
Generating the coded code word,
Generating a first parity bit by performing Low Density Parity Check (LDPC) encoding on the data to be encoded;
Generating a first code word by adding the first parity bit to the encoding target data;
Generating a second parity bit by performing iterative coding on the bits in the first code word;
Generating a second code word by adding the second parity bit to the first code word;
Puncturing the second code word to produce a punctured code word,
Generating the second parity bit by performing iterative encoding on the bits in the first code word,
Determining a number j of bits used for the iterative encoding;
Generating the second parity bit by performing iterative encoding on the bits in the first code word based on the number j of bits used for the iterative encoding.
Data transfer method.

The method of claim 1,
Generating the second parity bit by performing iterative encoding on the bits in the first code word based on the number j of the bits used for the iterative encoding,
Selecting as many bits as the number of bits (j) used in the iterative encoding from the first code word;
Generating the second parity bit by performing iterative coding on the selected bit
Data transmission method comprising a.

delete

The method of claim 1,
Puncturing the second code word to generate the punctured code word,
Determining the number of puncture bits,
Puncturing as many bits as the number of puncturing bits from the second code word to produce the punctured code word,
The number of puncturing bits is associated with the number of second parity bits.
Data transfer method.

In the data receiving method,
Receiving an encoding code word comprising a first parity bit produced by Low Density Parity Check (LDPC) encoding and a second parity bit produced by iterative encoding; And
Decoding the encoded codeword,
Decoding the encoded code word,
Generating a back-punched code word by back-punching the coded code word;
Generating a first decoding code word by performing iterative decoding on the de-punctured code word using the second parity bit;
Performing LDPC decoding on the first decoding code word using the first parity bit to generate a second decoding code word,
The step of generating the first decoding code word by performing the iterative decoding
Determining a number j of bits used for the iterative encoding;
Generating the first decoding code word by performing iterative decoding on the de-punctured code word based on the number of bits used for the iterative encoding.
How to receive data.

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The method of claim 5,
Generating the back punched code word
Determining the number of back punched bits,
Generating the back-punched code word by back-punching as many bits as the number of the back-punched bits into the coded code word.
How to receive data.

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In the data transmission apparatus,
An encoder for generating an encoded code word; And
A transmission unit for transmitting the coded code word,
The encoder,
An LDPC encoder for generating first parity bits by performing LDPC (Low Density Parity Check) encoding on the data to be encoded, and generating a first code word by adding the first parity bits to the data to be encoded;
An iterative encoding unit generating repetitive encoding on the bits in the first code word to generate a second parity bit, and adding the second parity bits to the first code word to generate a second code word;
A perforation unit for perforating the second code word to generate a perforated code word,
The iterative encoding unit determines the number j of bits used for the iterative encoding, and performs iterative encoding on the bits in the first code word based on the number of bits used for the iterative encoding, thereby performing the second parity. Generating bits
Data transmission device.

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The method of claim 10,
The puncturing unit determines the number of puncturing bits, and punctures as many bits as the puncturing bits from the second code word to generate the punctured code words,
The number of puncturing bits is associated with the number of second parity bits.
Data transmission device.

In the data receiving apparatus,
A receiving unit for receiving an encoding code word including a first parity bit produced by Low Density Parity Check (LDPC) encoding and a second parity bit produced by iterative encoding; And
A decoder which decodes the encoded codeword,
The decoding unit,
A reverse puncturing unit generating a reverse punctured code word by reverse puncturing the coded code word;
An iterative decoding unit for performing an iterative decoding on the de-punctured code word using the second parity bit to generate a first decoding code word;
An LDPC decoder configured to perform LDPC decoding on the first decoding code word using the first parity bit to generate a second decoding code word,
The iterative decoding unit
Determining the number of bits (j) used for the iterative encoding, and performing the iterative decoding on the decoded code word based on the number of bits used for the iterative encoding to perform the first decoding code word. To generate
Data receiving device.

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The method of claim 14,
The reverse puncturing unit determines the number of bits that have been reverse punctured, and generates the reverse punctured code word by reverse puncturing as many bits as the number of the reverse puncture bits into the coded code word.
Data receiving device.