KR102048515B1 - Ldpc encoding, decoding method and device using the method - Google Patents
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
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Abstract
An LDPC encoding and decoding method and an apparatus using the method are provided. The LDPC encoding method of the present invention includes (a) performing Low Density Parity Check (LDPC) encoding on data to be encoded, and (b) performing additional encoding on a specific bit of a code word in which the LDPC encoding is performed. Performing the steps.
Description
The present invention relates to a low density parity check (LDPC) encoding and decoding method and an apparatus using the method, and more particularly, to an LDPC encoding and decoding method for error floor improvement and an apparatus using the method. will be.
Next-generation communication systems are progressing in the form of supporting high-speed mass data transmission and reception, and turbo codes and low density parity check (LDPC) codes having a performance close to channel capacity are used to support high-speed mass data transmission and reception.
In addition, the storage device uses a high code rate error correction code to increase the density of information storage. Recently, the case of applying the LDPC code to the storage device has been increasing.
The LDPC code has a problem in that an error floor occurs due to an input range of the decoder and a decoding algorithm of the code.
In order to overcome this problem, various methods have been proposed to improve the error floor through the analysis of a similar codeword known as the cause of the error floor or a trapping set analysis.
However, the existing methods mainly focus on the theoretical analysis of the structure of the trapping set, which is the cause of the error floor phenomenon, and there are not many specific techniques proposed to remove them.
In addition, the existing methods concentrate on improving the error floor by modifying the decoding algorithm, which not only causes additional decoding complexity but also causes a loss of a transmission rate (or code rate), which makes it easy to implement and improve the error floor. It still does not provide a solution.
The present invention is to solve the above-mentioned problems of the prior art, and to provide an LDPC encoding and decoding method and an apparatus using the method for improving the error floor of the LDPC (Low Density Parity Check) code.
In order to achieve the above object, the LDPC encoding method according to an embodiment of the present invention comprises the steps of a) performing LDPC (Low Density Parity Check) encoding on the data to be encoded; and (b) the LDPC encoding is performed. Performing additional encoding on a specific bit of the code word.
In an aspect of the present invention, step (b) performs the additional encoding by using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.
In addition, in one aspect of the present invention, the LDPC encoding method further includes (c) performing puncturing on the code word.
In addition, in one aspect of the present invention, the step (c) includes the step of determining the number of bits to perform the puncturing corresponding to the number of parity bits added by the additional encoding of the step (b).
In order to achieve the above object, the LDPC decoding method according to an embodiment of the present invention comprises the steps of (a) performing a decoding on a specific bit that is previously selected and additionally coded in a code word to be decoded; (b) performing LDPC (Low Density Parity Check) decoding using the value of the specific bit decoded in the step (a).
In order to achieve the above object, the LDPC decoding method according to another embodiment of the present invention comprises the steps of (a) performing a Low Density Parity Check (LDPC) decoding on a code word that is a decoding target, (b) If the decoding of step (a) fails, performing decoding on a predetermined bit that is previously selected and additionally coded in the code word, and (c) using a value for the specific bit decoded in step (b). Performing LDPC decoding.
In one or another aspect of the present invention, in the LDPC decoding method, when a punctured bit exists in the code word, the LDPC decoding method replaces the punctured bit with a neutral value having a Log Likelihood Ratio (LLR) value of 0. It further comprises the step of decoding.
In one aspect of the present invention, the LDPC decoding method further includes (c) repeating steps (a) and (b) if the decoding of step (b) fails.
In one aspect or the other aspect of the present invention, the LDPC decoding method reflects different weights in each result of the decoding of the additionally encoded specific bits and the LDPC decoding.
In order to achieve the above object, the LDPC encoding apparatus according to an embodiment of the present invention, the LDPC encoder for performing LDPC (Low Density Parity Check) encoding on the data to be encoded and the code word on which the LDPC encoding is performed And an additional encoder that performs additional encoding on a specific bit of.
In one aspect of the present invention, the additional encoder performs the additional encoding by using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.
In one aspect of the present invention, the LDPC encoding apparatus further includes a puncturing unit for performing puncturing on the code word.
In one aspect of the invention, the puncturing unit determines the number of bits to perform the puncturing corresponding to the number of parity bits added by the additional encoding.
In order to achieve the above object, the LDPC decoding apparatus according to an embodiment of the present invention, the additional decoding unit for performing decoding on a specific bit pre-selected and additionally coded in the code word (code word) to be decoded; And an LDPC decoder configured to perform low density parity check (LDPC) decoding by using a value of a specific bit decoded by the additional decoder.
In order to achieve the above object, the LDPC decoding apparatus according to another embodiment of the present invention, the LDPC decoding unit for performing a low density parity check (LDPC) decoding on the code word (code word) to be decoded and the LDPC decoding If the negative decoding fails, an additional decoding unit which performs decoding on a predetermined bit that is previously selected and additionally encoded in the code word, the LDPC decoding unit using a value for the specific bit decoded by the additional decoding unit LDPC decoding is performed.
In one or another aspect of the present invention, when there is a punched bit in a code word, the additional decoder replaces the punctured bit with a neutral value having a Log Likelihood Ratio (LLR) value of 0 to decode.
In one or another aspect of the present invention, the LDPC decoder and the additional decoder reflect different weights to the results of each decoding.
According to one embodiment of the present invention, it is possible to ensure system performance by improving error flooring while minimizing transmission loss.
In addition, the present invention can be utilized for error correction codes of communication systems requiring real time high speed data transmission and storage devices requiring high information storage density.
The effects of the present invention are not limited to the above-described effects, but should be understood to include all the effects deduced from the configuration of the invention described in the detailed description or claims of the present invention.
1 is a diagram illustrating a configuration of an LDPC encoding apparatus according to an embodiment of the present invention.
2A is a diagram illustrating a configuration of an LDPC decoding apparatus according to another embodiment of the present invention.
2B is a diagram illustrating a position to which additional decoding is applied according to an embodiment of the present invention.
3 is a flowchart illustrating an LDPC encoding process according to an embodiment of the present invention.
4 is a flowchart illustrating an LDPC decoding process according to an embodiment of the present invention.
5 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
6 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
7 to 9 are graphs showing the results of the error floor improvement according to the embodiment of the present invention.
Hereinafter, with reference to the accompanying drawings will be described the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.
Throughout the specification, when a part is "connected" to another part, it includes not only "directly connected" but also "indirectly connected" with another member in between. .
In addition, when a part is said to "include" a certain component, this means that it may further include other components, without excluding the other components unless otherwise stated.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a diagram illustrating a configuration of an LDPC encoding apparatus according to an embodiment of the present invention.
The low density parity check (LDPC) encoding
For reference, the
Referring to each component, the
Hereinafter, the parity bits generated during LDPC encoding will be referred to as 'first parity bits'.
Meanwhile, the
Here, the specific bit may be selected in advance according to a trapping-set analysis result, and the
In this case, the
Hereinafter, in order to increase the reconstruction accuracy of the specific bit, a bit added to the code word through additional encoding of the
For reference, for additional encoding, a specific bit selected in advance according to the trapping set analysis result may be selected according to predetermined promises of the transmitting end and the receiving end, and the LDPC encoding
As a first method of selecting one or more (j) specific bits at a time, the LDPC encoding
Thereafter, the
As another example of the first bit selection method, the
Thereafter, the
As a second bit selection method for selecting one or more (j) specific bits at a time, the
Thereafter, the
Thereafter, the
Thereafter, the
As a third bit selection method for selecting one or more (j) specific bits at a time, the
Thereafter, the
Thereafter, if the number of selected bits is less than j, the
Thereafter, the
If the number of bits selected is greater than j, the
Here, the third method can select bits in a trapping set unit differently from the first method and the second method, so that the small trapping set can completely remove the trapping set.
For reference, in general, the size of the main trapping set that adversely affects the error floor in the high SNR region is relatively small.
The number of bits to choose depends on the desired system performance and complexity.
For example, if you don't need to consider the complexity a lot, the more bits you choose, the better your error floor performance. If your system complexity is your primary consideration, there are a variety of ways to get the optimal number of bits to achieve the desired performance. You can decide.
Meanwhile, the
In this case, the
For reference, the
1. The perforated bits are selected to minimize performance degradation by the perforated bits.
2. The bits to be drilled should be chosen to avoid the bits contained in the main trapping set that affect the error floor.
3. The bits to be punctured choose not to produce a trapping set of short length by the bits to be punctured.
4. Select the bits to be punctured to maintain regular regular intervals (equivalent intervals) (especially for signs where parity bits are generated in the form of dual diagonals).
For reference, a specific bit, which is the target of puncturing, may be decoded by being replaced with a neutral value having a Log Likelihood Ratio (LLR) value of 0 when decoding at the receiving end, and thus, the decoding convergence speed is reduced (decoding is performed several times) In this case, a check node merging method may be applied.
Meanwhile, the
2A is a diagram illustrating a configuration of an LDPC decoding apparatus according to another embodiment of the present invention.
The
For reference, the
In describing each component, when the code word is received from the transmitting end of the communication system or the encoding unit of the storage device, the
Here, the second parity bit is an additionally coded value for a specific bit previously selected according to the trapping set analysis result by the transmitting end of the communication system or the encoding unit of the storage device, and the
In addition, when the decoding of the code word fails in the
For reference, when the punctured bit exists in the code word, the
Therefore, when the
Meanwhile, when a code word is received from a transmitting end of a communication system or an encoding unit of a storage device, the
If the LDPC decoding of the code word fails, the
Therefore, the decoding time of the
2B is a diagram illustrating a position to which additional decoding is applied according to an embodiment of the present invention.
As illustrated in FIG. 2B, additional decoding may be applied to a value received from a channel and entering an input terminal of the LDPC decoder 220 (a), and to a decoded LLR value output from an output terminal of the
3 is a flowchart illustrating an LDPC encoding process according to an embodiment of the present invention.
For reference, the LDPC encoding process illustrated in FIG. 3 may be performed by the
First, the
In this case, the
After S301, the
In this case, the
After S302, the
In this case, the
After S303, the
Hereinafter, the LDPC decoding process of the present invention will be described with reference to FIGS. 4 to 6.
For reference, the LDPC decoding process illustrated in FIGS. 4 to 6 may be performed by the
4 is a flowchart illustrating an LDPC decoding process according to an embodiment of the present invention.
4 is a case of preferentially decoding a specific bit by referring to a second parity bit included in a code word (received LLR value) received from an encoder in a transmission system or a storage device in a communication system. It may correspond to.
First, the
In this case, when a punctured bit exists in the code word, the
In addition, the
For reference, in the case of using a soft decision in code word decoding, the
If a hard decision is used when decoding a code word, the
After S401, the
5 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
FIG. 5 is a case of performing LDPC decoding on a code word (received LLR value) received from an encoder in a transmission system or a storage device in the case of a communication system, and may correspond to 2. post-processing.
First, the
If decoding fails in S501, the
In this case, when a punctured bit exists in the code word, the
For reference, in the case of using a soft decision in code word decoding, the
If a hard decision is used when decoding a code word, the
In addition, the
For reference, since the w2 value is a value reflected when the decoding fails in S501, the reliability of the value of a specific decoded bit can be very large. In the case of w1, the value of w2 is also reflected when decoding is repeated. Since decoding is performed by applying, the value reflected in the decoding result may increase as decoding is repeated (however, w1 <w2).
As a result, w1 and w2 are for the decoded result value to have a higher reliability than the received LLR value.
After S502, the
6 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
For reference, the LDPC decoding process illustrated in FIG. 6 may be performed by mixing the processes of FIGS. 4 and 5 and may correspond to 3. hybrid-processing.
First, the
In this case, when a punctured bit related to the second parity bit is present in the code word, the
In addition, the
For reference, in the case of using a soft decision in code word decoding, the
If a hard decision is used when decoding a code word, the
After S601, the
If the decoding fails in S602, the
In this case, the
After S603, the
For reference, since the decoding process of S604 is performed by using the value decoded through S603, the decoding process may have a relatively higher reliability than the case of simply decoding the LLR value received from the channel. You can get performance.
If decoding fails in S604, the
7 to 9 are graphs showing the results of the error floor improvement according to the embodiment of the present invention.
For reference, we simulate a zigzag code with
First, FIGS. 7 and 8 are graphs showing the maximum performance that the system can obtain when the parity bit is additionally applied to a specific bit previously selected according to the trapping set analysis result.
7 and 8 show FER performance graphs of various techniques depending on the number of bits selected, where each selected bit was selected by one bit from a different trapping set, and the three selected bits were bits 351 and 368.
In FIG. 7 and FIG. 8, original represents the performance of the original code to which nothing is applied, and a known value is a selected bit of the trapping set (for reference, not only an information bit but also a parity bit) in the encoding step. It may be punctured before transmission, and the LLR value of the corresponding bit may be allocated to a maximum value (± ∞) according to the sign of the bit selected at the decoding end.
The application position of the decoding technique was applied to the received value of the
When the pre-processing technique is applied, the received value of the selected bit and three related bits are soft-combined to determine the new received value, and the weight factor is assumed to be 1.
In the post-processing technique, the selected bits are decoded using soft decision majority decoding on three bits obtained by additional coding (parity bits added for a specific bit preselected according to the trapping set analysis result), and the decoded bits are decoded. Accordingly, the LLR value is allocated to the corresponding bit and determined as the new received value of the
That is, the output of the
It is also assumed that the repetition between the
In FIG. 7, the original, known, and pre-processing technique applied the maximum number of repetitions 50 times for the iterative decoding of the
That is, if the
As shown in FIG. 7, a simple repetition code is used for the selected specific bit, and the proposed pre-processing and post-processing techniques show an excellent error floor improvement effect compared to the original.
In addition, as the number of selected specific bits increases, the performance gain increases, and when a total of 3 bits are selected, the gain may be about 0.6 dB at FER = 3 × 10 −4.
On the other hand, Figure 8 shows a graph of the FER performance assuming a decoding complexity equal to the decoding complexity of the post-processing technique.
That is, FER performance was compared by applying the same iteration decoding count (maximum iteration count = 80) to all the techniques, and it can be seen that the results show a similar tendency to the graph of FIG. 7.
For reference, hybrid-processing combined with pre-processing and post-processing techniques showed almost the same performance as the post-processing technique in the simulation environment.
However, the number of iterations used for decoding may be reduced to obtain the same performance, and additional performance gain may be obtained when different decoding algorithms are used for the
FIG. 9 is a diagram illustrating a FER performance graph of a post-processing technique and a post-processing technique in which puncturing is reflected according to the number of selected bits.
The known value technique has a code rate of approximately (k-j) / (n-j), and pre-processing and post-processing have a code rate of k / (n + jm).
Therefore, when using a code supporting a low code rate, if the number of bits j selected or the number of bits jm used for additional coding is small, the transmission efficiency of the proposed scheme may be improved.
In addition, by drilling additional bits (jm) in the proposed scheme, we can support the code rate k / n of the mother code
In this case, a slight performance degradation may be obtained as compared with the case where no puncture is performed. The performance graph when the code rate of the mother code is supported by puncturing is shown in FIG. 9.
The more bits are punctured, the lower the performance. However, compared to the original, the same code rate is supported but the performance is very good.
The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be.
Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.
For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.
The scope of the present invention is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present invention.
100: LDPC encoder
110: LDPC encoder
120: additional encoder
130: perforation
140: code word provider
200: LDPC decoding device
210: additional decoder
220: LDPC decoder
Claims (17)
Generating an encoded code word; And
Transmitting the encoded codeword,
Generating the coded code word,
Generating a first parity bit by performing Low Density Parity Check (LDPC) encoding on the data to be encoded;
Generating a first code word by adding the first parity bit to the encoding target data;
Generating a second parity bit by performing iterative coding on the bits in the first code word;
Generating a second code word by adding the second parity bit to the first code word;
Puncturing the second code word to produce a punctured code word,
Generating the second parity bit by performing iterative encoding on the bits in the first code word,
Determining a number j of bits used for the iterative encoding;
Generating the second parity bit by performing iterative encoding on the bits in the first code word based on the number j of bits used for the iterative encoding.
Data transfer method.
Generating the second parity bit by performing iterative encoding on the bits in the first code word based on the number j of the bits used for the iterative encoding,
Selecting as many bits as the number of bits (j) used in the iterative encoding from the first code word;
Generating the second parity bit by performing iterative coding on the selected bit
Data transmission method comprising a.
Puncturing the second code word to generate the punctured code word,
Determining the number of puncture bits,
Puncturing as many bits as the number of puncturing bits from the second code word to produce the punctured code word,
The number of puncturing bits is associated with the number of second parity bits.
Data transfer method.
Receiving an encoding code word comprising a first parity bit produced by Low Density Parity Check (LDPC) encoding and a second parity bit produced by iterative encoding; And
Decoding the encoded codeword,
Decoding the encoded code word,
Generating a back-punched code word by back-punching the coded code word;
Generating a first decoding code word by performing iterative decoding on the de-punctured code word using the second parity bit;
Performing LDPC decoding on the first decoding code word using the first parity bit to generate a second decoding code word,
The step of generating the first decoding code word by performing the iterative decoding
Determining a number j of bits used for the iterative encoding;
Generating the first decoding code word by performing iterative decoding on the de-punctured code word based on the number of bits used for the iterative encoding.
How to receive data.
Generating the back punched code word
Determining the number of back punched bits,
Generating the back-punched code word by back-punching as many bits as the number of the back-punched bits into the coded code word.
How to receive data.
An encoder for generating an encoded code word; And
A transmission unit for transmitting the coded code word,
The encoder,
An LDPC encoder for generating first parity bits by performing LDPC (Low Density Parity Check) encoding on the data to be encoded, and generating a first code word by adding the first parity bits to the data to be encoded;
An iterative encoding unit generating repetitive encoding on the bits in the first code word to generate a second parity bit, and adding the second parity bits to the first code word to generate a second code word;
A perforation unit for perforating the second code word to generate a perforated code word,
The iterative encoding unit determines the number j of bits used for the iterative encoding, and performs iterative encoding on the bits in the first code word based on the number of bits used for the iterative encoding, thereby performing the second parity. Generating bits
Data transmission device.
The puncturing unit determines the number of puncturing bits, and punctures as many bits as the puncturing bits from the second code word to generate the punctured code words,
The number of puncturing bits is associated with the number of second parity bits.
Data transmission device.
A receiving unit for receiving an encoding code word including a first parity bit produced by Low Density Parity Check (LDPC) encoding and a second parity bit produced by iterative encoding; And
A decoder which decodes the encoded codeword,
The decoding unit,
A reverse puncturing unit generating a reverse punctured code word by reverse puncturing the coded code word;
An iterative decoding unit for performing an iterative decoding on the de-punctured code word using the second parity bit to generate a first decoding code word;
An LDPC decoder configured to perform LDPC decoding on the first decoding code word using the first parity bit to generate a second decoding code word,
The iterative decoding unit
Determining the number of bits (j) used for the iterative encoding, and performing the iterative decoding on the decoded code word based on the number of bits used for the iterative encoding to perform the first decoding code word. To generate
Data receiving device.
The reverse puncturing unit determines the number of bits that have been reverse punctured, and generates the reverse punctured code word by reverse puncturing as many bits as the number of the reverse puncture bits into the coded code word.
Data receiving device.
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