KR20200116889A - Ldpc encoding, decoding method and device using the method - Google Patents

Abstract

A low density parity check (LDPC) encoding and decoding method and an apparatus using the method are provided. According to the present invention, an LDPC encoding method comprises the steps of: (a) performing LDPC encoding on data to be encoded; and (b) performing additional encoding on a specific bit of a codeword on which the LDPC encoding has been performed.

Description

An LDPC encoding and decoding method, and an apparatus using the method {LDPC ENCODING, DECODING METHOD AND DEVICE USING THE METHOD}

The present invention relates to a LDPC (Low Density Parity Check) encoding and decoding method, and an apparatus using the method, and more particularly, to an LDPC encoding and decoding method for improving an error floor, and an apparatus using the method. will be.

Next-generation communication systems are advancing in a form that supports high-speed large-capacity data transmission and reception, and turbo codes and LDPC (Low Density Parity Check) codes having a performance close to channel capacity are used to support high-speed large-capacity data transmission and reception.

In addition, in storage devices, error correcting codes with a high code rate are used to increase the degree of integration of information storage. Recently, LDPC codes are increasingly applied to storage devices.

The LDPC code has a problem in that an error floor occurs due to an input range of a decoder and a decoding algorithm of the code.

In order to overcome this, various methods for improving the error floor through analysis of a pseudo codeword known as the cause of the error floor phenomenon or a trepping set have been proposed.

However, the existing methods are mainly researches that theoretically analyze the structure of the trapping set, which is the cause of the error-floor phenomenon, and there are not many specific techniques for removing this.

In addition, the existing methods focus on improving the error floor by modifying the decoding algorithm, which not only causes additional decoding complexity, but also causes a loss of transmission rate (or code rate), making it easy to implement and improving the error floor. It is still not able to present a solution that exists.

The present invention is to solve the problems of the prior art described above, and to provide an LDPC encoding and decoding method and an apparatus using the method for improving the error floor of LDPC (Low Density Parity Check) codes.

In order to achieve the above object, the LDPC encoding method according to an embodiment of the present invention includes: a) performing LDPC (Low Density Parity Check) encoding on data to be encoded, and (b) performing the LDPC encoding. And performing additional encoding on specific bits of the code word.

In one aspect of the present invention, in step (b), the additional encoding is performed using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.

In addition, in an aspect of the present invention, the LDPC encoding method further includes the step of (c) performing puncturing on the code word.

In addition, in one aspect of the present invention, step (c) includes determining the number of bits to be punctured in correspondence with the number of parity bits added by the additional encoding of step (b).

In order to achieve the above object, the LDPC decoding method according to an embodiment of the present invention includes the steps of: (a) decoding a specific bit previously selected and additionally encoded from a code word to be decoded, and (b) performing LDPC (Low Density Parity Check) decoding by using the value for the specific bit decoded in step (a).

In order to achieve the above object, the LDPC decoding method according to another embodiment of the present invention includes the steps of: (a) performing LDPC (Low Density Parity Check) decoding on a code word to be decoded, (b) If the decoding in step (a) fails, decoding a specific bit previously selected and additionally encoded in the code word, and (c) using a value for the specific bit decoded in step (b) And performing LDPC decoding.

In one aspect or another aspect of the present invention, the LDPC decoding method, when a puncturing bit exists in the code word, replaces the punctured bit with a neutral value having a Log Likelihood Ratio (LLR) value of 0. It further includes the step of decoding.

In one aspect of the present invention, the LDPC decoding method further includes (c) repeating steps (a) and (b) when the decoding in step (b) fails.

In one aspect or another aspect of the present invention, the LDPC decoding method reflects different weights in the decoding of the additionally coded specific bit and each result of the LDPC decoding.

In order to achieve the above object, an LDPC encoding apparatus according to an embodiment of the present invention includes an LDPC encoding unit that performs Low Density Parity Check (LDPC) encoding on data to be encoded, and a code word on which the LDPC encoding is performed. It includes an additional encoding unit that performs additional encoding on a specific bit of.

In one aspect of the present invention, the additional encoding unit performs the additional encoding using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.

In one aspect of the present invention, the LDPC encoding apparatus further includes a puncturing part for puncturing the code word.

In one aspect of the present invention, the puncturing unit determines the number of bits to be punctured corresponding to the number of parity bits added by the additional encoding.

In order to achieve the above object, the LDPC decoding apparatus according to an embodiment of the present invention includes an additional decoding unit for decoding a specific bit previously selected and additionally encoded from a code word to be decoded, and And an LDPC decoder for performing LDPC (Low Density Parity Check) decoding by using a value for a specific bit decoded by the additional decoder.

In order to achieve the above object, an LDPC decoding apparatus according to another embodiment of the present invention includes an LDPC decoding unit performing LDPC (Low Density Parity Check) decoding on a code word to be decoded, and the LDPC decoding. When the negative decoding fails, the code word includes an additional decoding unit that decodes a specific bit previously selected and additionally encoded, wherein the LDPC decoding unit uses a value for a specific bit decoded by the additional decoding unit. LDPC decoding is performed.

In one aspect or another aspect of the present invention, when there is a puncturing bit in a code word, the additional decoding unit decodes the punctured bit by replacing the punctured bit with a neutral value having a log likelihood ratio (LLR) of 0.

In one aspect or another aspect of the present invention, the LDPC decoding unit and the additional decoding unit reflect different weights in the result of each of the performed decoding.

According to an embodiment of the present invention, system performance can be guaranteed by minimizing a transmission rate loss and improving an error floor phenomenon.

In addition, it can be used for error correction codes of communication systems requiring real-time high-speed data transmission and storage devices requiring high information storage integration.

The effects of the present invention are not limited to the above effects, and should be understood to include all effects that can be inferred from the configuration of the invention described in the detailed description or claims of the present invention.

1 is a diagram illustrating a configuration of an LDPC encoding apparatus according to an embodiment of the present invention.
2A is a diagram illustrating a configuration of an LDPC decoding apparatus according to another embodiment of the present invention.
2B is a diagram illustrating a location to which additional decoding is applied according to an embodiment of the present invention.
3 is a flowchart illustrating an LDPC encoding process according to an embodiment of the present invention.
4 is a flowchart illustrating an LDPC decoding process according to an embodiment of the present invention.
5 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
6 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.
7 to 9 are graphs showing a result of improving an error floor according to an embodiment of the present invention.

Hereinafter, the present invention will be described with reference to the accompanying drawings. However, the present invention may be implemented in various different forms, and therefore is not limited to the embodiments described herein.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and similar reference numerals are assigned to similar parts throughout the specification.

Throughout the specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "indirectly connected" with another member interposed therebetween. .

In addition, when a part "includes" a certain component, it means that other components may be further provided, rather than excluding other components unless specifically stated to the contrary.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of an LDPC encoding apparatus according to an embodiment of the present invention.

The LDPC (Low Density Parity Check) encoding apparatus 100 according to an embodiment of the present invention includes an LDPC encoding unit 110, an additional encoding unit 120, a puncturing unit 130, and a code word providing unit 140. ) Can be included.

For reference, the LDPC encoding apparatus 100 shown in FIG. 1 may be included in the transmitting end in the case of a communication system requiring real-time high-speed data transmission (hereinafter, referred to as a'communication system'), and a storage device requiring high information storage density. A device (hereinafter referred to as a'storage device') may be included in the encoding unit.

In describing each component, the LDPC encoder 110 may perform LDPC encoding on data to be encoded, and in this case, a parity bit may be generated and included in the encoded code word.

Hereinafter, a parity bit generated during LDPC encoding is referred to as a'first parity bit'.

Meanwhile, the additional encoder 120 may perform additional encoding on a specific bit of a code word on which LDPC encoding has been performed.

Here, the specific bit may be selected in advance according to a trapping-set analysis result, and the additional encoding unit 120 is more accurate when decoding the specific bit at the receiving end of the communication system or the decoding unit of the storage device. Additional encoding may be performed to enable restoration (eg, adding a parity bit for the specific bit to a code word).

In this case, the additional encoding unit 120 may perform the additional encoding using an encoding method including one or more of repetition, Bose-Chadhuri-Hocquenghem (BCH) code, and Reed-Solomon (RS) encoding.

Hereinafter, in order to increase the reconstruction accuracy of the specific bit, a bit added to the code word through additional encoding by the additional encoder 120 is referred to as a'second parity bit'.

For reference, for additional encoding, a specific bit selected in advance according to the trapping set analysis result may be selected according to a predetermined appointment between the transmitting end and the receiving end, and the LDPC encoding apparatus 100 uses one or more (j pieces) at a time in the following manner. ) Can be selected.

As a first method of selecting one or more (j) specific bits at a time, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position in the error floor area through a simulation (1).

Thereafter, the LDPC encoding apparatus 100 determines the structure of the trapping set and selects the bit in which the error occurs most in the different trapping sets (a total of j bits are selected for each trapping set) (1-1).

As another example of the first bit selection method, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position in the error floor area through a simulation (1).

Thereafter, the LDPC encoding apparatus 100 may select j bits in which the error occurs the most (1-2).

As a second bit selection method for selecting one or more (j) specific bits at a time, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position in the error ridge region through a simulation (2-1). ).

Thereafter, the LDPC encoding apparatus 100 selects one bit with the most error (2-2).

Thereafter, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position by performing a simulation of decoding by creating a codeword by putting a known value (0 or 1) in the selected bit (2-3). ).

Thereafter, the LDPC encoding apparatus 100 repeats the processes 2-2 and 2-3 until j bits are selected (2-4).

As a third bit selection method for selecting one or more (j) specific bits at a time, the LDPC encoding apparatus 100 obtains a histogram of the number of errors for each codeword bit position in the error floor area through simulation, and Identify the trapping set structure that has a big impact (3-1).

Thereafter, the LDPC encoding apparatus 100 identifies a trapping set that affects the error floor among all the trapping sets including the bit having the largest error, and selects all of the bits constituting it (3-2).

Thereafter, if the number of selected bits is less than j, the LDPC encoding apparatus 100 selects a bit with the largest error number from among unselected bits and selects a bit similar to step 3-2 (3-3).

Thereafter, the LDPC encoding apparatus 100 repeats steps 3-3 until j bits are selected (3-4).

If the number of selected bits is greater than j, the LDPC encoding apparatus 100 may apply a method of selecting j with a relatively large number of errors among the bits selected in the last step, or selecting bits in units of a trapping set.

Here, in the third method, different from the first method and the second method, bits can be selected in units of a trapping set, so in the case of a small trapping set, the trapping set can be completely removed.

For reference, in general, the size of the main trapping set that adversely affects the error floor in the high SNR region is relatively small.

The number of bits to choose can vary depending on the desired system performance and complexity.

For example, if you do not need to consider complexity, the more bits you select, the better the error floor performance will be. If system complexity is the main consideration, the optimal number of bits to obtain the desired performance can be determined in various ways. Can be decided.

Meanwhile, the puncturing unit 130 may puncture the bit of the code word in order to maintain the code rate of the information bit, and the bit on which puncturing is performed may be selected in advance.

In this case, the puncturing unit 130 may determine the number of bits to be punctured corresponding to the number of second parity bits for which additional encoding has been performed.

For reference, the perforation unit 130 may select a bit to be perforated according to the following criteria.

1. The perforated bit is selected so that performance degradation by the perforated bit is minimized.

2. The bits to be punctured are selected, avoiding the bits included in the main trapping set that affect the error floor.

3. The perforated bit is selected so that a short length trapping set is not created by the perforated bit.

4. Select the punctured bits to keep as regular intervals (equal intervals) as possible (especially in the case of codes where parity bits are generated in a dual diagonal form).

For reference, a specific bit that is the target of puncture can be decoded by being replaced with a neutral value with a Log Likelihood Ratio (LLR) value of 0 when decoding at the receiving end, which reduces the decoding convergence speed (decryption is repeated several times). In this case, a check node merging method may be applied.

Meanwhile, the code word providing unit 140 includes a first parity bit generated by the LDPC encoding unit 110, a second parity bit added by the additional encoding unit 120, and a puncturing unit 130. The code word encoded by including one or more of the bits punctured by may be stored in a specific storage or transmitted to a specific medium (receiver, decoding device) through an arbitrary communication means or communication channel.

2A is a diagram illustrating a configuration of an LDPC decoding apparatus according to another embodiment of the present invention.

The LDPC decoding apparatus 200 according to another embodiment of the present invention may include an additional decoder 210 and an LDPC decoder 220.

For reference, the LDPC decoding apparatus 200 shown in FIG. 2A may be included in a receiving end in the case of a communication system, and may be included in a decoding unit in the case of a storage device.

In describing each component, when a code word is received from a transmission end of a communication system or an encoding unit of a storage device, the additional decoding unit 210 refers to a second parity bit included in the received code word, Decryption can be performed.

Here, the second parity bit is a value additionally encoded for a specific bit selected in advance according to the trapping set analysis result by the transmitting end of the communication system or the encoding unit of the storage device, and the additional decoding unit 210 refers to the second parity bit. The corresponding specific bit can be more accurately restored.

In addition, when the decoding of the code word in the LDPC decoder 220 to be described later fails, the additional decoding unit 210 performs decoding on a specific bit by referring to the second parity bit included in the code word, and decodes A more accurate value for a specific bit on which is performed may be transmitted to the LDPC decoder 220.

For reference, when there is a punctured bit in a code word, the additional decoding unit 210 may decode the punctured bit by replacing the punctured bit with a neutral value having an LLR value of 0.

Therefore, the time when the additional decoding unit 210 performs decoding is before the LDPC decoding unit 220 performs LDPC decoding on the code word or the LDPC decoding unit 220 performs LDPC decoding on the code word to decode It may be a case of failure.

Meanwhile, when a code word is received from a transmission end of a communication system or an encoder of a storage device, the LDPC decoding unit 220 performs LDPC decoding on the code word by referring to the first parity bit included in the received code word. I can.

If LDPC decoding for a code word fails, the LDPC decoding unit 220 refers to a restoration value for a specific bit received from the additional decoding unit 210 (ie, a value decoded with reference to the second parity bit). Thus, LDPC decoding can be performed.

Therefore, the decoding time of the LDPC decoding unit 220 is after receiving the code word (LLR value) from the transmitting end of the communication system or the encoding unit of the storage device, or the additional decoding unit 210 is the transmitting end or the storage device of the communication system. It may be after first decoding a specific bit by referring to the second parity bit included in the code word (received LLR value) received from the encoder of.

2B is a diagram illustrating a location to which additional decoding is applied according to an embodiment of the present invention.

As shown in FIG. 2B, additional decoding may be applied to a value received from the channel and input to the input terminal of the LDPC decoder 220 (a), and the decoded LLR value outputted from the output terminal of the LDPC decoder 220 Additional decoding can be applied (b), and as an example, a decoded LLR value and a value obtained through additional decoding can be combined with a predetermined weight.

3 is a flowchart illustrating an LDPC encoding process according to an embodiment of the present invention.

For reference, the LDPC encoding process illustrated in FIG. 3 may be performed by the LDPC encoding apparatus 100 illustrated in FIG. 1, that is, a transmitting end in the case of a communication system or an encoding unit in the case of a storage device.

First, the LDPC encoding apparatus 100 performs LDPC encoding on data to be encoded (S301).

In this case, the LDPC encoding apparatus 100 may generate the first parity bit.

After S301, the LDPC encoding apparatus 100 performs additional encoding (adding a second parity bit) on a specific bit of a code word on which LDPC encoding has been performed (S302).

In this case, the LDPC encoding apparatus 100 may perform additional encoding using an encoding method including at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.

After S302, the LDPC encoding apparatus 100 punctures the bits of the code word in order to maintain the code rate of the information bits (S303).

In this case, the LDPC encoding apparatus 100 may determine the number of bits to be punctured in response to the number of second parity bits added in S302.

After S303, the LDPC encoding apparatus 100 transmits a code word including at least one of the first parity bit generated in S301, the second parity bit added in S302, and the punctured bit in S303 to the receiving end of the communication system or the storage device. It is transmitted to the decoding unit (S304).

Hereinafter, the LDPC decoding process of the present invention will be described with reference to FIGS. 4 to 6.

For reference, the LDPC decoding process shown in FIGS. 4 to 6 may be performed by the LDPC decoding apparatus 200 shown in FIG. 2, that is, a receiver in the case of a communication system or a decoder in the case of a storage device, and LDPC decoding Based on the execution time, it can be classified into 1. pre-processing, 2. post-processing, and 3. hybrid-processing methods.

4 is a flowchart illustrating an LDPC decoding process according to an embodiment of the present invention.

4 is a case in which a specific bit is preferentially decoded by referring to a second parity bit included in a code word (received LLR value) received from a code word (received LLR value) received from a transmitting end or a storage device in the case of a communication system. 1. Pre-processing It may correspond to.

First, the LDPC decoding apparatus 200 performs decoding on a specific bit by referring to a second parity bit included in a code word (received LLR value) to be decoded (S401).

In this case, when a puncturing bit exists in the code word, the LDPC decoding apparatus 200 may decode the punctured bit by replacing the punctured bit with a neutral value having a log likelihood ratio (LLR) of 0.

In addition, the LDPC decoding apparatus 200 reflects the weight to the value of the specific bit decoded in S401, so that the value decoded in S401 has a higher reliability than the existing received LLR value for the specific bit when decoding the code word. Can be done.

For reference, in the case of using a soft decision when decoding a code word, the LDPC decoding apparatus 200 may obtain a new received value by combining the result of applying additional decoding on the specific bit with the received LLR value. , The new received value may have a higher reliability than the existing received LLR value.

If a hard decision is used when decoding a code word, the LDPC decoding apparatus 200 may change a received value of a corresponding position as a result of applying additional decoding to the specific bit.

After S401, the LDPC decoding apparatus 200 may perform LDPC decoding by referring to the specific bit value decoded in S401 and the first parity bit (S402).

5 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.

5 is a case in which LDPC decoding is preferentially performed on a code word (received LLR value) received from an encoding unit in the case of a transmission end or a storage device in the case of a communication system, and may correspond to 2. post-processing.

First, the LDPC decoding apparatus 200 decodes a code word by referring to a first parity bit included in a code word to be decoded (a received LLR value) (S501).

If the decoding fails in S501, the LDPC decoding apparatus 200 reflects a specific weight (hereinafter referred to as'w1') with respect to the result decoded in S501, and refers to the second parity bit included in the code word. Decryption is performed (S502).

In this case, when a punctured bit exists in the code word, the LDPC decoding apparatus 200 may perform decoding by replacing the punctured bit with a neutral value having an LLR value of 0.

For reference, in the case of using a soft decision when decoding a code word, the LDPC decoding apparatus 200 may obtain a new received value by combining the result of applying additional decoding on the specific bit with the received LLR value. , The new received value may have a higher reliability than the existing received LLR value.

If a hard decision is used when decoding a code word, the LDPC decoding apparatus 200 may change a received value of a corresponding position as a result of applying additional decoding to the specific bit.

In addition, the LDPC decoding apparatus 200 may adjust the reliability by reflecting a specific weight (hereinafter, referred to as'w2') with respect to the decoded result in S502.

For reference, since the w2 value is a value that is reflected when the decoding fails in S501, the reliability of the value of a specific decoded bit can be very high.In the case of w1, too, when the decoding is repeated, the value of w2 is reflected. Since decoding is performed by applying, the value reflected in the decoding result may increase as the decoding is repeated (however, w1 <w2).

Consequently, w1 and w2 are intended to have a higher reliability than the received LLR value of the decoded result value.

After S502, the LDPC decoding apparatus 200 may perform LDPC decoding by referring to the value of the specific bit decoded in S502 and the first parity bit (S503).

6 is a flowchart illustrating an LDPC decoding process according to another embodiment of the present invention.

For reference, the LDPC decoding process shown in FIG. 6 is performed by mixing the processes of FIGS. 4 and 5, and may correspond to 3. hybrid-processing.

First, the LDPC decoding apparatus 200 performs decoding on a specific bit by referring to the second parity bit included in a code word (received LLR value) to be decoded (S601).

In this case, when there is a punctured bit related to the second parity bit in the code word, the LDPC decoding apparatus 200 may perform decoding by replacing the punctured bit with a neutral value having an LLR value of 0.

In addition, the LDPC decoding apparatus 200 may reflect a specific weight (hereinafter, referred to as'w1') to the decoded result in S601 so that the decoded result value has a higher reliability than the received LLR value.

For reference, in the case of using a soft decision when decoding a code word, the LDPC decoding apparatus 200 may obtain a new received value by combining the result of applying additional decoding on the specific bit with the received LLR value. , The new received value may have a higher reliability than the existing received LLR value.

If a hard decision is used when decoding a code word, the LDPC decoding apparatus 200 may change a received value of a corresponding position as a result of applying additional decoding to the specific bit.

After S601, the LDPC decoding apparatus 200 performs LDPC decoding by referring to the value of the specific bit decoded in S601 and the first parity bit included in the code word (S602).

If the decoding fails in S602, the LDPC decoding apparatus 200 reflects a specific weight (hereinafter referred to as'w2') to the decoded result in S602, and the decoding result reflecting w2 and the second parity bit included in the code word. With reference to, decoding is performed on a specific bit (S603).

In this case, the LDPC decoding apparatus 200 may reflect a specific weight (hereinafter, referred to as'w3') to the result decoded in S603 so that the result value decoded in S603 has a higher reliability than the received LLR value. .

After S603, the LDPC decoding apparatus 200 performs LDPC decoding by referring to a value for a specific bit to which w3 is reflected and a first parity bit in S603 (S604).

For reference, since the decoding process of S604 is performed using the value decoded through S603, it can have a relatively higher reliability than the case of simply decoding the LLR value received from the channel, and even with fewer repetitive decoding, You can get performance.

If the decoding fails in S604, the LDPC decoding apparatus 200 may repeat the processes S603 and S604.

7 to 9 are graphs showing a result of improving an error floor according to an embodiment of the present invention.

For reference, as a simulation environment, concatenated zigzag codes with a code rate of 1/2, codeword length (n, k) = (1000, 500), BPSK (Binary Phase Shift Key) modulation, AWGN (Additive White Gaussian Noise) channel, A min-sum algorithm and floating point simulation are assumed.

First, FIGS. 7 and 8 are graphs showing the maximum performance that the system can obtain when a parity bit is additionally applied to a specific bit selected in advance according to a trapping set analysis result.

7 and 8 show graphs of FER performance of various techniques according to the number of selected bits, where each selected bit is selected by 1 bit from a different trepping set, and the selected three bits are bit 351 and 368. Bit times and bit 504

In FIGS. 7 and 8, original indicates the performance of the original code to which nothing is applied, and the known value is a bit selected from the trepping set in the encoding step (for reference, not only the information bit but also the parity bit can be selected), the channel May be punctured prior to transmission, and the LLR value of the corresponding bit may be assigned a maximum value (±∞) according to the sign of the bit selected at the decoding stage.

The location of the decoding technique was applied to the received value of the input terminal of the LDPC decoder 220, and at this time, a repetition code was selected as an additional coding method for the selected bit, and the number of repetitions used for the code was 3 times. .

When applying the pre-processing technique, a new received value was determined by soft combining the received values of the selected bit and three related bits, and the weight factor was assumed to be 1.

In the post-processing technique, the selected bit is decoded using soft decision majority decoding for 3 bits obtained by additional coding (parity bits added for a specific bit previously selected according to the trapping set analysis result), and the code of the decoded bit is decoded. Accordingly, the LLR value is allocated to the corresponding bit to determine the new reception value of the LDPC decoder 220.

That is, the output of the additional decoding unit 210 is applied to the LDPC decoding unit 220 like a known bit (the reliability of the signal decoded by the additional decoding unit 210 is set very high (w2=∞)). .

In addition, it is assumed that the repetition between the LDPC decoding unit 220 and the additional decoding unit 210 is one (w1 = 0).

In FIG. 7, for repetitive decoding of the LDPC decoder 220, the original, known, and pre-processing techniques applied a maximum number of repetitions of 50 times, and post-processing applied an additional 30 times to the basic 50 times.

That is, if the LDPC decoding unit 220 fails to decode even after repetitive decoding up to 50 times, additional 30 times (up to 30 times) of repetitive decoding are performed using a value newly obtained through post-processing.

As shown in FIG. 7, when a simple repetition code is used for a selected specific bit and the proposed pre-processing and post-processing techniques are applied, it can be seen that the error floor improvement effect is superior to that of the original.

In addition, as the number of selected specific bits increases, the performance gain increases, and when a total of 3 bits are selected, a gain of about 0.6 dB may be obtained at FER = 3X10-4.

Meanwhile, FIG. 8 shows a graph of FER performance assuming the same decoding complexity as that of the post-processing technique.

That is, the FER performance was compared by applying the same number of iterations of decoding (maximum number of iterations = 80) to all techniques, and it can be seen that this result shows a similar trend to the graph of FIG. 7.

For reference, the hybrid-processing technique that combines the pre-processing technique and the post-processing technique showed almost similar performance to the post-processing technique in the simulation environment.

However, in order to obtain the same performance, the number of repetitions used for decoding may be reduced, and additional performance gains may be obtained when different decoding algorithms are used in the additional decoding unit 210.

Meanwhile, FIG. 9 is a diagram showing an FER performance graph of a post-processing technique according to the number of selected bits and a post-processing technique in which puncturing is reflected.

The known value technique has a code rate of approximately (k-j)/(n-j), and pre-processing and post-processing have a code rate of k/(n+jm).

Therefore, when a code supporting a low code rate is used, if the number of bits j to be selected increases or the number of bits jm used for additional coding is small, the transmission efficiency of the proposed scheme may be improved.

In addition, if the proposed scheme is punctured by an additional bit (jm), the code rate k/n of the mother code can be supported.

In this case, performance may be slightly deteriorated compared to that without puncturing, and a performance graph when puncturing is applied to support the code rate of the mother code is as shown in FIG. 9.

As the number of bits to be punctured increases, the performance decreases slightly, but it can be seen that the performance is very good while supporting the same code rate compared to the original.

The above description of the present invention is for illustrative purposes only, and those of ordinary skill in the art to which the present invention pertains will be able to understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. will be.

Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting.

For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as being distributed may also be implemented in a combined form.

The scope of the present invention is indicated by the claims to be described later, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

100: LDPC encoding device
110: LDPC encoding unit
120: additional encoding unit
130: perforation
140: code word provider
200: LDPC decoding device
210: additional decoding unit
220: LDPC decoding unit

Claims (5)

In the data transmission method,
Generating an encoded code word; And
And transmitting the encoded code word,
Generating the encoded code word,
Generating a first parity bit by performing first encoding on the encoding target data; and
Generating a first code word by adding the first parity bit to the encoding target data,
Generating a second parity bit by performing a second encoding on the bits in the first code word; and
And generating a second code word by adding the second parity bit to the first code word.
Data transfer method. The method of claim 1,
Generating the encoded code word,
Determining the total number of bits to be selected;
The step of selecting some bits of the second code word based on the total number of bits to be selected.
Data transfer method. The method of claim 2,
The step of determining the total number of bits to be selected is
Determining the total number of bits to be selected based on at least two or more factors.
Data transfer method. The method of claim 3,
The at least two or more factors include at least one of system performance and complexity.
Data transfer method. The method of claim 1,
The first encoding is LDPC (Low Density Parity Check),
The second encoding includes at least one of repetition, Bose-Chadhuri-Hocquenghem (BCH), and Reed-Solomon (RS) encoding.
Data transfer method.

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