KR102044381B1 - Method of manufacturing silicon wafer, silicon wafer manufactured therefrom and solar cell comprising the semiconductor wafer - Google Patents

Abstract

The present invention relates to a method for manufacturing a silicon wafer, a silicon wafer manufactured therefrom and a solar cell comprising the same. In one embodiment of the present invention, (a) coating a boric acid diluted in deionized water on one side of the silicon wafer, (b) coating a phosphorus source mixed with two or more dopants on the other side of the silicon wafer, ( c) heat-treating the silicon wafer to simultaneously perform the diffusion process of boron according to step (a) and phosphorus according to step (b), and (d) coating aluminum glass on the surface of the silicon wafer on which boron is diffused. (E) heat treating the silicon wafer to gather impurities in the silicon wafer with the aluminum glass, and (f) etching the silicon wafer to form the boron-rich layer formed by the step (c). It provides a silicon wafer manufacturing method comprising the step of removing the aluminum glass according to step (d).

Description

Method of manufacturing silicon wafer, silicon wafer manufactured therefrom, and solar cell comprising same TECHNICAL FIELD OF THE SYMBOL OF SOUFACTURING SILICON WAFER, SILICON WAFER MANUFACTURED THEREFROM AND SOLAR CELL COMPRISING THE SEMICONDUCTOR WAFER}

The present invention relates to a method for manufacturing a silicon wafer, a silicon wafer manufactured therefrom, and a solar cell including the same, and more particularly, by using a co-diffusion technique of boron and phosphorus, an emitter and a back field are more efficiently than the conventional silicon wafer. The present invention relates to a silicon wafer manufactured therefrom and a solar cell comprising the same.

In the silicon solar cell industry, since silicon wafer costs account for 40% or more of the final solar cell price, thin silicon wafers are continuously required to reduce solar cell manufacturing costs and solar power generation costs. Accordingly, research on thinning silicon to make the silicon wafer have a thinner thickness has been actively conducted.

Regarding the thinning of silicon, for example, if the thickness of the silicon wafer is lowered to less than 100 μm while maintaining the light collection efficiency and surface passivation characteristics of such thin silicon, it is similar to that of a solar cell having a silicon wafer of 200 μm thickness in the prior art or Higher efficiency can be obtained. In addition, according to the above example, it is possible to use a smaller amount of silicon wafer by reducing the thickness of the silicon, there is an effect that can significantly reduce the cost of solar power generation.

Meanwhile, in the process of manufacturing an ultra-thin silicon wafer, the process of forming an aluminum backside field using a conventional aluminum paste process is inexpensive and simple, but as the thickness of the silicon wafer decreases, a thick aluminum paste may cause warpage of the silicon wafer. Cause. In addition, according to the conventional ultra-thin silicon wafer manufacturing process, due to the aluminum-silicon eutectic layer (Al-Si eutectic layer) formed during the aluminum back-field process, the back reflectivity at the silicon / aluminum electrode interface is lowered, the conventional conventional ultra-thin Silicon wafer manufacturing processes have limitations in producing high efficiency solar cells.

Boron to replace the aluminum backfield has higher solubility in silicon than aluminum and also maintains high reflectivity at the silicon / aluminum interface because no second phase is formed along the boron backfield, thus forming a highly efficient solar cell. Seems highly likely. However, in order to apply boron to ultra-thin silicon wafers because the activation temperature for boron doping is higher than that of phosphorus, several steps of diffusion are required to apply boron to the ultra-thin silicon wafer. There is a problem of reducing efficiency.

The present invention has been made to solve the above problems, the technical problem to be achieved by the present invention is to perform the process of simultaneously performing the co-diffusion process of phosphorus and boron, the boron rich layer removal using aluminum spin on glass and the removal of impurities in the wafer at the same time The present invention provides a method for manufacturing a silicon wafer, a silicon wafer manufactured therefrom, and a solar cell including the same, which can simplify the process and reduce manufacturing costs.

The technical problem to be achieved by the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned above may be clearly understood by those skilled in the art from the following description. There will be.

In order to solve the technical problem, an embodiment of the present invention, (a) coating a boric acid diluted in deionized water on one surface of the silicon wafer, (b) a phosphorus source mixed with two or more dopants of the silicon wafer Coating the surface, (c) heat treating the silicon wafer to simultaneously perform the diffusion process of boron according to step (a) and phosphorus according to step (b), and (d) the silicon wafer with boron diffusion Coating aluminum glass on the surface of (e) heat treating the silicon wafer to gather impurities in the silicon wafer with the aluminum glass, and (f) etching the silicon wafer to perform the step (c). It provides a silicon wafer manufacturing method comprising the resulting boron-rich layer and removing the aluminum glass according to step (d).

In one embodiment of the present invention, the silicon wafer may be a thin silicon wafer having a thickness of 60 μm or less.

In one embodiment of the present invention, the boric acid is a hydrate of metaboric acid (HBO ₂ ) or boron oxide (B ₂ O ₃ ), the phosphorus source is silicon oxide (SiO ₂ ) and phosphorus pentoxide (P ₂ O ₅ ) It is formed in the form of a mixed paste, the mass ratio of phosphorus pentoxide (P ₂ O ₅ ) may be 0.5% to 1.0%.

In an embodiment of the present invention, the method may further include the step (a-1) of hydrophilizing the silicon wafer before the step (a).

In one embodiment of the present invention, by the step (c), one surface of the silicon wafer is formed with phosphorus emitter glass (Phosphorus Silicate Glass, PSG) in turn, the other surface of the silicon wafer is a boron back surface field , A boron rich layer (BRL) and boron silicate glass (BSG) are formed in this order, the step (f) is the silicon silicate, the boron rich layer and the etching of the silicon wafer by etching the hydrofluoric acid and It may be a step of removing the boron silicate glass.

In one embodiment of the present invention, the step (c) is a step of baking the silicon wafer at a first temperature and heat treatment of the silicon wafer at a second temperature higher than the first temperature to perform the diffusion process of boric acid and phosphorus It may include the process of performing.

In an embodiment of the present disclosure, the step (e) may include baking the silicon wafer at a third temperature and curing the silicon wafer at a fourth temperature higher than the third temperature. .

In one embodiment of the present invention, the step (c) is performed using a rapid heat processor of nitrogen atmosphere, the step (e) may be performed using a rapid heat processor of a mixed atmosphere of oxygen and nitrogen. have.

In one embodiment of the present invention, the first temperature and the third temperature may be 130 ℃ to 450 ℃, the second temperature is 800 ℃ to 950 ℃, the fourth temperature may be 700 ℃ to 900 ℃. .

The method of claim 1, wherein the coating performed in (a), (b) and (d) step is a spin coating, the aluminum glass is aluminum spin-on aluminum mixed with aluminum oxide In the step (f), the silicon wafer may be etched with hydrofluoric acid (HF) to remove the boron-rich layer formed according to step (c) and the aluminum glass according to step (d).

In addition, to solve the above technical problem, another embodiment of the present invention provides a silicon wafer manufactured according to the silicon wafer manufacturing method described above.

In addition, to solve the above technical problem, another embodiment of the present invention provides a solar cell including a silicon wafer manufactured according to the silicon wafer manufacturing method described above.

According to the present invention, it is possible to control the doping profile of the emitter and the back field by controlling the concentration of the low-cost spin-on dopant source, and the entire process of wafer fabrication by using the Rapid Thermal Annealing (RTA) method for the co-diffusion process of phosphorus and boron. It can save time.

In addition, according to the present invention, it is possible to increase the solar cell efficiency and simplify the process by removing the boron-rich layer that seriously reduces the solar cell efficiency when forming the boron backside field while simultaneously removing impurities from the wafer using aluminum spin-on glass. have.

 In addition, according to the present invention, boron has a high solubility with respect to silicon to form a strong back-field even with a thin dopant source thin film layer, it is possible to implement an ultra-thin silicon solar cell having a high efficiency without warping phenomenon Can be.

In addition, according to the present invention, by applying a co-diffusion process of phosphorus and boron to the solar cell manufacturing process it is possible to reduce the solar cell manufacturing process cost and time compared to the process of doping the boron and phosphorus double of the existing solar cell manufacturing process. .

In addition, according to the present invention, it is possible to simplify the manufacturing process of the ultra-thin silicon wafer and to reduce the manufacturing cost and time of the solar cell including the silicon wafer and the silicon wafer.

The effects of the present invention are not limited to the above-described effects, but should be understood to include all the effects deduced from the configuration of the invention described in the detailed description or claims of the present invention.

1 is a flowchart illustrating a procedure of a method of fabricating a silicon wafer according to an embodiment of the present invention.
2 and 3 illustrate detailed processes of some procedures constituting a silicon wafer manufacturing method according to an embodiment of the present invention.
4 is a schematic diagram sequentially showing a process of a silicon wafer manufactured according to the silicon wafer manufacturing method according to an embodiment of the present invention.
5 to 12 are diagrams for explaining the results of the experiment performed on the silicon wafer according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In addition, the accompanying drawings are intended to facilitate understanding of the embodiments disclosed herein, but are not limited to the technical spirit disclosed herein by the accompanying drawings, all changes included in the spirit and scope of the present invention. It is to be understood to include water, equivalents and substitutes. And the part not related to the description in order to clearly describe the present invention in the drawings are omitted, the size, shape, shape of each component shown in the drawings may be variously modified, the same / similar parts for the entire specification Identical / similar reference numerals are used.

The suffixes "module" and "unit" for components used in the following description are given or used in consideration of ease of specification, and do not have distinct meanings or roles from each other. In addition, in describing the embodiments disclosed herein, when it is determined that the detailed description of the related known technology may obscure the gist of the embodiments disclosed herein, the detailed description is omitted.

Throughout the specification, when a part is said to be "connected (connected, contacted or coupled) with another part, it is not only when it is" directly connected (connected, contacted or coupled) ", but also in between. This includes cases in which "indirectly connected (connecting, contacting or coupling)" therebetween. Also, when a part is said to "include (or prepare)" a component, it is not to exclude other components, but to "include (or prepare)" other components, unless specifically stated otherwise. That means you can.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In addition, terms including ordinal numbers, such as first and second, as used herein may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

1 is a flowchart illustrating a procedure of a silicon wafer manufacturing method (hereinafter, referred to as a silicon wafer manufacturing method) according to an embodiment of the present invention.

In the silicon wafer manufacturing method according to the present embodiment (a) coating boric acid diluted in deionized water on one surface of the silicon wafer (s120), (b) a phosphorus source mixed with two or more dopants on the other surface of the silicon wafer Coating (s130), (c) heat treating the silicon wafer to simultaneously perform diffusion process of boron according to (a) step 120 and (b) step (s130) (s140) and (d ) Coating aluminum glass on the surface of the silicon wafer on which boron is diffused (s150), (e) heat treating the silicon wafer and gathering impurities in the silicon wafer with the aluminum glass (s160), (f (C) etching the silicon wafer to remove the boron-rich layer formed in step (s140) and (d) removing the aluminum glass in step (s150) (s170).

In this embodiment, the silicon wafer may be a thin silicon wafer, and the thickness of the thin silicon wafer herein may be 60 μm or less, preferably 30 μm to 60 μm, but is not limited thereto. The thin silicon wafer may also be referred to as ultra thin silicon wafer.

In addition, the silicon wafer manufacturing method according to the present embodiment may further include the step (a-1) of hydrophilizing the silicon wafer as step (a-1) before step (a) of s120, (a-1 In operation S110, the silicon wafer may be hydrophilized using Piranha cleaning.

In the above step, the boric acid is a hydrate of metaboric acid (HBO ₂ ) or boron oxide (B ₂ O ₃ ), and the phosphorus source mixed with the two or more dopants is silicon oxide (SiO ₂ ) and phosphorus pentoxide (P ₂ O ₅ ). It is formed in the form of a mixed paste, the mass ratio of phosphorus pentoxide (P ₂ O ₅ ) may be 0.5% to 1.0%. That is, the value of P ₂ O ₅ / (SiO ₂ + P ₂ O ₅ ) may be 0.005 (0.5%) to 0.01 (1%).

In addition, the phosphorus source in which the two or more dopants are mixed may be a phosphorus source in which two different types of spin on dopants are mixed in a specific concentration ratio. For example, the phosphorus source in which the two or more dopants are mixed may be formed in a form in which the first phosphor on dopant and the second spin on dopant are mixed with P ₂ O ₅ in a ratio of 1: 1 to 1: 5.

In addition, by (c) step (s140), one surface of the silicon wafer is sequentially formed with an phosphor emitter and an silicate glass, and the other surface of the silicon wafer is formed with a boron backside field, a boron rich layer, and a boron silicate glass in that order. Can

Accordingly, step (f) (s170) may be a step of removing the silicate glass, the boron rich layer and the boron silicate glass by etching the silicon wafer with hydrofluoric acid.

In addition, referring to FIG. 2 which shows the detailed process of step (c) (s140), (c) step (s140) is performed at a first temperature by using a rapid thermal annealing (RTA) in a nitrogen atmosphere. Baking the silicon wafer (s141) and heat-treating the silicon wafer at a second temperature (second temperature> first temperature) higher than the first temperature to perform diffusion of boric acid and phosphorus ( s142).

In addition, referring to FIG. 3 showing the detailed process of step (e) (s160), (e) step (s160) is the silicon at a third temperature using a rapid heat processor of the atmosphere mixed with oxygen and nitrogen A process of baking the wafer (s161) and a process of curing the silicon wafer (s162) at a fourth temperature (fourth temperature> third temperature) higher than the third temperature (s162).

For example, the first temperature and the third temperature may be 130 ° C to 450 ° C, the second temperature may be 800 ° C to 950 ° C, and the fourth temperature may be 700 ° C to 900 ° C, but is not limited thereto. . In addition, the present invention may be implemented such that the fourth temperature is lower than the second temperature in step (c) (s140), and (a) (s120), (b) (s130) and (d) (s150). The coating carried out in the step may be spin coating.

FIG. 4 is a schematic diagram sequentially illustrating a process of a silicon wafer manufactured according to the silicon wafer manufacturing method described above with reference to FIGS. 1 to 3, and will be described in more detail with reference to FIG. 4. .

First, a silicon wafer 401 is prepared to proceed with step (a) (s120). The silicon wafer 401 may be p-type or n-type. In addition, step (a-1) (s110) of hydrophilizing the silicon wafer 401 may be performed before proceeding to step (a) (s120).

Next, as in step (a) (s120), the boric acid layer 402 is formed by coating boric acid diluted in deionized water on the bottom surface of the silicon wafer 401. Boron has a high solubility with respect to silicon to form a strong back field even with a low thin dopant source thin film layer, it is possible to implement an ultra-thin silicon solar cell with high efficiency without the occurrence of warpage.

Next, as shown in step (b) (s130), a phosphorus source of which concentration is adjusted by mixing two kinds of spin on dopants is coated on the top surface of the silicon wafer 401 to form an in spin on dopant layer 403.

Next, as in step (c) (s140), the silicon wafer 401 is heat-treated. At this time, the heat treatment process may be performed in a rapid heat processor in a nitrogen atmosphere. Specifically, when the silicon wafer 401 is baked at a relatively low temperature and the diffusion process of boron and phosphorus is performed at a temperature higher than the first temperature, the phosphorus spin-on dopant layer 403 may be a phosphorus emitter. Divided into a layer 404 and an silicate glass layer (PSG) 405, wherein the boric acid layer 402 is a boron backside field layer (B-BSF) 406, a boron rich layer (BRL) 407, a boron silicate glass layer (BSG) 408.

As such, by simultaneously diffusing boron and phosphorus through a single heat treatment process, the wafer manufacturing process may be simplified, and manufacturing time and cost may be reduced.

Next, as a subsequent process for removing the unnecessary boron rich layer 407 and removing impurities formed in the silicon wafer 401, (d) an aluminum glass is placed on the bottom surface of the boron silicate glass layer 408 as in step (s150). Spin coating to form aluminum glass layer 409. Here, the aluminum glass layer may be an aluminum spin on glass layer.

Next, as in step (e) (s160), the silicon wafer 401 coated with the aluminum glass layer 409 is heat-treated. At this time, the heat treatment may be performed in a rapid heat processor of the atmosphere mixed with oxygen and nitrogen. Accordingly, impurities formed in the silicon wafer 401 can be removed. In the oxygen atmosphere, the boron rich layer 407 may be a boron silicate glass layer (BSG).

Next, as in step (f) s170, an etching process is performed to remove the boron-rich layer 407. In this case, the etching process may be performed using hydrofluoric acid, and the insulator glass layer 405, the boron rich layer 407, and the boron silicate glass layer 408 may be removed by the etching process.

As described above, at the same time as removing impurities of the silicon wafer, the boron-rich layer that seriously reduces the solar cell efficiency when forming the boron backplane field may be removed to increase the solar cell efficiency and simplify the process.

5 to 12 are diagrams for explaining the results of the experiment performed on the silicon wafer according to an embodiment of the present invention.

Figure 5 shows the sheet resistance of the boron backplane and phosphorus emitter diffused in N ₂ atmosphere and 950 ℃, 501 is the silicon sheet resistance according to the concentration of boric acid, 502 is the silicon sheet resistance according to the concentration of phosphorus pentoxide It is shown.

Referring to Figure 5, (a) in step (s120) according to an embodiment of the present invention can adjust the boron dopant concentration according to the amount of dilute boric acid in deionized water, (b) different from step (s130) Two kinds of phosphorus spin on dopants can be mixed and the phosphorus dopant concentration can be adjusted. As described above, it can be seen that the sheet resistance of the phosphor emitter and the boron backplane is easily controlled by controlling the concentration of the spin-on dopant.

In addition, as shown in FIG. 6, when the aluminum glass is coated on the lower surface of the boron silicate glass as in step (e), the aluminum glass gathers impurities such as iron in the silicon wafer.

FIG. 7 shows the results of D-SIMS analysis of the boron backplane, where 701 and 702 show the D-SIMS profile of boron and the D-SIMS profile of phosphorus after 50 seconds of co-diffusion and 5 minutes of Al-SOG curing. , (c) The co-diffusion process of phosphorus and boron and the dopant profile after curing the aluminum glass according to step (s140) are analyzed using D-SIMS.

Referring to FIG. 7, as can be seen from the boron profile, the boron-rich layer of 45 nm was present on the surface after the co-diffusion process of phosphorus and boron, but after the aluminum curing process, it was confirmed that the decrease was within 5 nm.

The silicon surface in which the boron-rich layer is present has a hydrophilic characteristic. Based on this, the silicon wafer in which the boron-rich layer is present after boron doping and the aluminum cure after boron doping to confirm that the boron-rich layer is removed. The contact angle measurements of the silicon surface subjected to the ring process were compared, and the results are shown in FIG. 8. In FIG. 8, 801 shows the surface of the silicon wafer before the process proceeds, 802 shows the surface of the silicon wafer where the boron-rich layer is present after the boron diffusion, and 803 shows aluminum spin-on glass coating and curing on the silicon wafer. After the (Al-SOG curing process) shows the surface of the silicon wafer.

When the surface of each silicon wafer of 801 to 803 was immersed in a hydrofluoric acid solution and 10 mL of deionized water was dropped on the surface, the contact angle was not measured on the surface of the silicon wafer in which the boron-rich layer was present. On the other hand, the surface of the silicon wafer cured aluminum spin-on glass in the oxygen atmosphere showed a contact angle of about 91% of the surface of the silicon wafer that was not processed.

That is, according to the present invention, it can be seen that the boron-rich layer can be effectively removed by proceeding to step (e) step (s160) and (f) step (s170) after step (s150).

Figure 9 shows the effective minority carrier lifetime (901) measured by Miro-PCD and emitter saturation current value (902) measured by QSSPC, 901 is measured before and after Al-SOG curing The effective minority carrier lifetime is shown, and 902 is the saturation current density (J ₀ ) result on the phosphorus and boron double doped surface.

As a result of measuring the effective minority carrier life of the wafer by the Micro-PCD method as shown in 901, the effective minority carrier life of the silicon wafer was reduced to 40 후 after the co-diffusion process. Afterwards, it was found that the original wafer life level was restored (180 kPa).

In addition, the emitter saturation current before and after aluminum spin-on glass curing was measured by QSSPC method as shown in 902.In the case of boron, the emitter saturation current was changed from 611 fA / cm ² to 296 fA / cm ² by aluminum curing process. It was confirmed that the phosphorus was reduced from 734 fA / cm ² to 200 fA / cm ² by the aluminum curing process.

FIG. 10 is a flowchart illustrating a process of applying the above-described silicon wafer to an ultra-thin p-type silicon solar cell. As shown in the flowchart of FIG. 10, an aluminum back field solar cell having a basic structure using an ultra-thin p-type silicon wafer. A boron backplane solar cell having a wah and a PERT structure was manufactured.

In order to prevent warpage of the ultra-thin silicon wafer during the formation of the aluminum backside field, aluminum was thinly deposited to a thickness of 2 μm using electron beam deposition.

After boron and phosphorus diffusion process and aluminum curing, the boron backplane PERT solar cell used photolithography for partial contact of the back electrode.

In addition, pyramid texturing of 2-3 μm was performed to increase light collection of ultra-thin silicon solar cells.

The results of experiments on the ultra-thin p-type silicon solar cell manufactured through the flowchart shown in FIG. 10 are shown in FIG. 11, and FIG. 11 is a boron backplane solar cell having a basic structure solar cell of an aluminum back field and a PERT structure. Shows the current-voltage curve and external quantum efficiency.

Referring to FIG. 11, when compared with an aluminum back field solar cell, the boron back field solar cell shows high quantum efficiency in a long wavelength region due to a low recombination rate at the back side, and shows a higher open circuit voltage.

In addition, the low external quantum efficiency at the front side of the boron backside field solar cell can be improved by adjusting the emitter dopant concentration, and tuning the thickness of the dielectric at the back side can show higher passivation effect and back reflectance.

As shown in FIG. 12, a four-point bending test was performed to determine a critical curvature radius according to aluminum thickness, and thin aluminum was deposited on an pyramid-textured 50 μm ultra-thin silicon wafer by an electron beam (e-beam) deposition method. The wafer with the screen printed on the paste was subjected to a heat treatment process to form a backside field.

Optical photo taken just before the destruction of the ultra-thin silicon wafer.The measured critical curvature radius was compared with the critical curvature radius predicted by the formula.For silicon with aluminum paste, the predicted value has a very large critical curvature radius. And showed a big difference. This is because the surface of the aluminum paste is uneven and the interface between the back surface layer and silicon is not flat.

It can be seen that silicon wafers made of thin aluminum by e-beam deposition have a low critical curvature radius similar to that of silicon wafers without aluminum. Therefore, a solar cell using a boron backplane and thin aluminum may have a low critical curvature radius and may be useful for a flexible solar cell.

Hereinafter, a silicon wafer manufacturing experiment example according to the silicon wafer manufacturing method described above will be described in more detail with reference to FIGS. 5 to 12.

For the co-diffusion process of boron and phosphorus, boric acid and phosphorus spin-on dopant (P-SOD) are applied to the present invention. Boric acid (H ₃ BO ₃ ) is a hydrate of boron oxide (B ₂ O ₃ ) and has low cost, high safety and purity (99.999%, Sigma-Aldrich) compared to conventional boron spin-on dopants (B-SOD). Has advantages. A dilute solution of boric acid in deionized (DI) water can be utilized as a spin-on diffusion source and the dehydration-diffusion process can supply enough boron to form a strong boron backside field (BSF).

Boron diffusion from boric acid to silicon consists of two-stage dehydration of boric acid. Hydrate of metaboric acid (HBO ₂ ), or B ₂ O ₃ is first formed at a temperature of 130 ° C. or higher. When metaboric acid is heated above 250 ° C., anhydrous boron oxide (B ₂ O ₃ ) begins to form and 90% by weight of metaborate is in the form of B ₂ O ₃ at 350 ° C.

For phosphorus emitters, two P-SODs (P504 and P507, Filmtronics) are mixed at different dopant compound (P2O5) concentrations (0.0625 wt% and 1.0 wt% in solids content) and a mixture of P507 and P504 The ratio was adjusted from 1: 1 to 1: 5. A p-type, oriented CZ Si wafer having a resistivity of 1 to 5 Ω · cm and a thickness of 525 μm was used, and the wafer was cleaned in a Pirana solution to make the wafer surface hydrophilic prior to spin coating. Dopant diffusion was performed at 950 ° C. for different diffusion treatment times in a rapid heat treatment process (RTP) system followed by low temperature baking at 130 to 450 ° C. Borosilicate glass (BSG) and phosphoric silicate glass (PSG) were removed by hydrofluoric acid (HF) immersion and the sheet resistance (R _sheet ) was measured by a four point probe. D-SIMS analysis was performed on samples made at co-diffusion process conditions meeting both boron and phosphorus target process window.

The boron-rich layer (BRL) is a Si-B compound and its composition is proposed as most SiB ₆ . BRL exhibits an amorphous structure and consists mainly of boron and silicon and contains low concentrations of oxygen. BRL needs to be removed because it acts as a strong recombination site. Since BRL is impermeable to HF, it is not easily removed by the etching method of HF. The method for removing the BRL according to the present embodiment is to perform an oxidation process, for example, at a high temperature of 850 ° C or higher. The Al-SOG layer has a good gettering effect that strongly removes Fe, which is suspected of reducing the minority carrier life of the bulk wafer involved in the boron diffusion process.

Therefore, according to one embodiment of the present invention, Al-SOG is applied onto the BSG by spin coating after the co-diffusion process and cured in an atmosphere of N ₂ mixed with O ₂ in an RTP system at 800 ° C., so that the BRL is a single step heat treatment cycle. Was removed and carrier life was restored. D-SIMS (Cameca, IMS 4FE7) analysis was used to observe the depth of BRL for each treatment step. Surface hydrophilicity was analyzed by contact angle measurement using CMOS cameras (Thorlabs). In contact angle measurements, three types of polished Si wafer surfaces were prepared: 1) Si wafer before performing the diffusion process, 2) boron diffused Si and 3) boron diffused, Al-SOG and hardened Si. All surfaces were immersed in HF solution and 10 μl of DI water was dropped one drop on each surface. The contact angle was then calculated by low coupled line symmetry droplet shape analysis using CMOS camera images. Carrier life recovery was also measured by QSSPC (quasi-state photoconductivity) and micro-PCD (photoconductivity collapse). QSSPC was performed on WCT-120 and micro-PCD was performed on MDP spots.

According to this experimental example, two types of solar cells were manufactured: a standard structure cell having Al-BSF and a p-PERT structure cell having B-BSF. A 1 cm ² size cell was fabricated into a 50 μm-thick, (100) oriented p-type wafer of 1 to 5 Ω · m resistivity. Si wafers were textured into shallow pyramids 3 μm high using commercial additives (SEA, SEAtex pS). Emitter and BSF formation for a standard cell was performed by a co-diffusion process of phosphorus and aluminum with one RTP cycle. 2 μm thick thin aluminum was deposited by e-beam evaporation on the rear electrode. Ti (50 nm) and Ag (2 μm) were deposited sequentially on the front electrode by the lift-off procedure. Edge isolation processes for accurate cell determination and electrical short-circuit protection on the emitter and back are achieved by SF ₆ reactive ion etching. SiO _x and SiN _x deposited by PECVD were used in both front and rear passivation cases. For PERT cells with B-BSF, co-diffusion and Al-SOG post-cure procedures were applied. Back metallization was also performed by photolithography and the partial contact area of the back Al electrode was adjusted to be 1.13%. Cell performance was measured by artificial sun (Oriel LSC-100) and external quantum efficiency (EQE) was also analyzed.

10 shows a flow chart of the fabrication process for Al-BSF and p-PERT solar cells.

A four-point bending test was conducted using a tensile tester (Instron 5948) to observe the effect of backside aluminum thickness on the mechanical properties of ultra-thin Si wafers textured with shallow pyramids in relation to the four point bending test. Was performed. The silicon wafer was cut into strips and applied to a untextured flat surface at a loading rate of 5 μm / s. Three different wafers with different Al thicknesses, a wafer without deposited aluminum, a wafer with 2 μm thick thin film Al deposited, and a screen printed Al deposited Si wafer 30 μm thick were prepared. For the deposited and screen printed samples, the emitter formation process was performed at 950 ° C. in an RTP system to make similar structures for each of the co-diffused PERT cell and the screen printed Al-BSF cell. The screen printed Al paste sintering process involved two steps: 1) burning at 380 ° C. for 15 seconds in an oxygen surrounding atmosphere and 2) baking at 780 ° C. for 5-7 seconds. Three samples were then cut into shapes having a width of 3 mm and a length of 13 mm using laser scribing for a four point bending test. Critical bending radii were analyzed by optical microscopy images.

As can be seen in Figure 5, the R _sheet of B-BSF and P-emitter can be tuned by adjusting the dopant concentration and diffusion time. With this feature, boron and phosphorus co-diffusion can be applied for B-BSF and P-emitter formation in p-type Si solar cells. The target windows of B-BSF and P-emitter for high efficiency PERT cell fabrication are 30-50 Ω / □ and 80-100 Ω / □, respectively. In the experimental example it can be seen that the co-diffusion conditions that meet both the emitter and the BSF target window are 50 sec diffusion with 1 wt% boric acid and 0.68 wt% P-SOD in N ₂ RTP. By D-SIMS analysis, the junction depths of the P emitters were 330 nm and 250 nm for boron under co-diffusion conditions according to this experimental example. A boron-enriched layer of ˜40 nm from the surface, with a B concentration above the solubility limit in Si, was observed from the boron profile only after the co-diffusion process, indicating the presence of BRL.

까지 증가하였고, 그것은 수소 말단기를 가진 베어(bare) Si 웨이퍼 표면의 그것(80.3°)과 비슷하다. 이런 접촉각 측정 결과들은 BRL이 Al-SOG 경화에 의해 효과적으로 제거되었음을 보여 준다.To observe the removal of BRL, D-SIMS analysis was performed after PSG and Al-SOG removal by HF soaking. As shown in FIG. 7, the surface BRL decreased from ˜40 nm to ˜5 nm after 5 minutes of Al-SOG curing and the junction depth of boron is ˜200 nm. During the process of curing Al-SOG in a high temperature oxygen atmosphere, B in the BRL is oxidized, and chemical removal by HF is possible in a subsequent process. Final _sheet resistance (R _sheet ) of both P-emitter and B-BSF was measured after Al-SOG curing. The R _sheet of P-emitter decreased from 90 Ω / □ to 60 to 70 Ω / □ and the R _sheet of B-BSF increased from 30 Ω / □ to 45 to 55 Ω / □. Removal of BRL was confirmed by contact angle measurements of diffused Si wafers. It is well known that the surface of a clean Si wafer becomes hydrophobic by HF immersion due to hydrogen end groups. However, the presence of BRL on the Si surface prevents hydrogen termination reactions during HF immersion, making the Si surface hydrophilic. In the water contact angle measurement, as can be seen in FIG. 8, the Si surface after the boron diffusion showed a very low contact angle. The reason for this is that it showed high hydrophilicity because of BRL that could not be removed after the diffusion process. For Al-SOG hardened wafers, most of the BRL was removed, so the contact angle of the wafer was up to 72.9

Increased up to that of a bare Si wafer surface with hydrogen end groups (80.3 °). These contact angle measurement results show that the BRL was effectively removed by Al-SOG curing.

Electrostatic attraction between the negatively charged composite in Al-SOG and the positively charged impurity Fe in the wafer bulk helps to remove impurities. The impurity removal effect of Al-SOG was confirmed by measuring the emitter saturation current density (J ₀ ) by the effective minority carrier lifetime measurement using micro-PCD and QSSPC method. Bulk life was measured by acid etchant of HF: HNO ₃ : CH ₃ COOH (HNA) after removal of the emitter and BSF and iodine-ethanol solution passivation was used.

As shown at 901 of FIG. 9, the minority carrier life after the co-diffusion process decreased significantly from 180 to 200 μ㎲ to 40 μ㎲. Al-SOG cure was performed at RTP for 1 to 5 minutes, and it was clear that the increase in effective minority carrier lifetime in the initial cure step was due to the removal of BRL, and the amount of additional impurity removal also increased with increasing cure time. Increases. Based on this result, 5 minutes of Al-SOG post-cure was selected for the cell fabrication conditions. For QSSPC measurements, antireflective coating layers of PECVD SiOx and SiNx were deposited and then subjected to HF immersion for each boron and phosphorus double side diffusion and Al-SOG post-cured samples.

The J ₀ results shown in 902 in Figure 9 is also Al-SOG after - BRL removal by curing and removal of impurities is 611 fA / cm ² to 296 fA / cm ² and from ^{734 fA / cm 2 200 fA /} cm 2 from Shows that J ₀ is reduced.

1101 and 1102 of FIG. 11 are schematic diagrams of a standard cell with Al-BSF and a PERT cell with B-BSF.

The IV characteristics of the solar cell are shown in 1104 of FIG. 11 and 1103 are shown for both standard cell with Al-BSF and PERT cell with B-BSF under the standard cell global AM1.5 spectrum (100 mW / cm ² ). Show variables 1105 represents the EQE spectrum of the highest performance cell of the two cells and 1103 represents the average value. Compared to standard cells with Al-BSF, higher EQE was observed for PERT cells with B-BSF in the near infrared spectral range of 900 to 1200 nm, and this improved spectral response reduced surface simultaneously with improved back reflectance. It is obvious that this is due to the rate of recombination. In the short wavelength region below 500 nm of a PERT cell with B-BSF, the lower EQE value is due to the higher dopant concentration of the emitter which increased frontal recombination. The emitter sheet resistance (R _sheet ) of the PERT cell after the Al-SOG curing process was 60 to 70 Ω / □, which is 20 to 30 Ω / □ lower than the target emitter resistance. When the emitter doping concentration is adjusted to an R _sheet of 80 to 100 Ω / □ by adjusting the mixing ratio of P-SOD, higher EQE values can be obtained in the short wavelength band.

Compression depth and loading force were measured during the four point bending test and critical bending radius was measured. A sample schematic is shown in 1202 of FIG. 12, where 1202 comprises a pyramid cross-section textured Si wafer (bare Si wafer) that does not contain an Al electrode in the order from top to bottom and e-beam deposited Al having a thickness of 2 μm. A Si wafer with a Si wafer and a screen printed Al of 30 μm thick is shown.

In order to measure the maximum tensile stress at the surface of the Si wafer with Al, a double layer composite beam model was used in which the samples consisted of Al / Si bilayers.

1201 in FIG. 12 sequentially shows the critical bending radii measured from the optical image and the expected results from the composite beam model (experimentally calculated (scatter plot with error bars) and expected (white scatter) Gray line with dot plot) critical bending radius). 1204 also shows optical microscopic images of exposed Si, deposited Al and screen printed Al taken before rupture in a four point bend test in the order from top to bottom.

The maximum tensile stress on the 50 μm-thick Si surface calculated using a critical bending radius of 21.1 mm was 154 MPa. Using the composite beam model, the bend radii for 2 μm deposited Al and 30 μm screen printed Al samples were expected to be 21.9 mm and 27.0 mm, respectively, and the bending strength of the bilayer sample was at the same level as the bare wafer. Value was shown. The total thickness increased by the deposition of the Al film shifts the neutral axis plane towards the Si surface and induces greater tensile stress at the Si surface, resulting in increased bending radius. The critical bending radius of the Al deposited wafer is 23.1 mm, which is similar to that of the exposed Si wafer, while showing a maximum value of 31.8 mm for screen printed Al wafers. The difference between the expected bend radius and the calculated bend radius appears to be related to the formation of the Al-Si eutectic layer. In particular, in screen printed Al Si wafers, a non-uniform Al-Si eutectic layer is formed from the heat treatment process, and this non-uniformity plays a key role in reducing the bending strength. The ultra-thin c-Si PERT structured solar cell with B-BSF was developed by a co-diffusion process according to one embodiment of the present invention, which does not require a thick Al film to form the backside field. It is more suitable for flexible solar cell development than BSF-based standard structure solar cell.

The description of the present invention described above is for illustrative purposes, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present invention.

Claims (12)

In the silicon wafer manufacturing method for manufacturing a boron backside field solar cell,
(a) coating boric acid diluted in deionized water on one surface of the silicon wafer;
(b) coating a phosphorus source mixed with two or more dopants on the other side of the silicon wafer;
(c) heat treating the silicon wafer to simultaneously carry out a diffusion process of boron according to step (a) and phosphorus according to step (b);
(d) coating aluminum glass on the surface of the silicon wafer where boron is diffused;
(e) heat treating the silicon wafer to gather impurities in the silicon wafer with the aluminum glass;
(f) simultaneously removing the boron-rich layer formed according to step (c) and the aluminum glass according to step (d) as the silicon wafer is etched,
The coating performed in steps (a), (b) and (d) is spin coating,
The aluminum glass is aluminum spin on glass,
The step (f) is a step of removing the boron-rich layer formed according to the step (c) and the aluminum glass according to the step (d) by etching the silicon wafer with hydrofluoric acid (HF). Wafer Manufacturing Method.
The method of claim 1,
The silicon wafer is a silicon wafer manufacturing method, characterized in that the thin silicon wafer having a thickness of 60 ㎛ or less.
The method of claim 1,
The boric acid is a hydrate of metaboric acid (HBO ₂ ) or boron oxide (B ₂ O ₃ ),
The phosphorus source is formed in the form of a paste in which silicon oxide (SiO ₂ ) and phosphorus pentoxide (P ₂ O ₅ ) are mixed, and wherein the mass ratio of phosphorus pentoxide (P ₂ O ₅ ) is 0.5% to 1.0%. Wafer Manufacturing Method.
The method of claim 1,
A method of manufacturing a silicon wafer further comprising the step (a-1) of hydrophilizing the silicon wafer before step (a).
The method of claim 1,
In the step (c), a phosphorus emitter and an silicate glass are sequentially formed on one surface of the silicon wafer, and a boron backside electric field, a boron rich layer, and a boron silicate glass are sequentially formed on the other surface of the silicon wafer.
The step (f) is to etch the silicon wafer with hydrofluoric acid to remove the silicate glass, the boron rich layer and the boron silicate glass.
The method of claim 1,
The step (c) includes baking the silicon wafer at a first temperature and performing a process of diffusing boric acid and phosphorus by heat treating the silicon wafer at a second temperature higher than the first temperature. Silicon wafer manufacturing method.
The method of claim 6
The step (e) comprises the step of baking the silicon wafer at a third temperature and the step of curing the silicon wafer at a fourth temperature higher than the third temperature.
The method of claim 1
Step (c) is carried out using a rapid heat processor in a nitrogen atmosphere,
The step (e) is a silicon wafer manufacturing method, characterized in that carried out using a rapid heat treatment of a mixed atmosphere of oxygen and nitrogen.
The method of claim 7, wherein
The first temperature and the third temperature is 130 ℃ to 450 ℃,
The second temperature is 800 ° C. to 950 ° C.,
The fourth temperature is a silicon wafer manufacturing method, characterized in that 700 ℃ to 900 ℃.
delete A silicon wafer manufactured according to the method of manufacturing a silicon wafer of claim 1.
A solar cell comprising a silicon wafer manufactured according to the method of manufacturing a silicon wafer of claim 1.

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